description of the pre-amplifier-shaper with layout

NIKHEF, Amsterdam, 08-09-99, JDS

Pre-Amplifier-shaper layout.1

Description of the Pre-amplifier-shaperwith layout.

Introduction:

Simulation.

Till now we have restricted our self to developing and optimising a circuit only inschematic form. In practise however a layout must be made and tested. The step betweenthese two development points is making a layout and simulate with its extracted form.The difference between this simulation and the simulation of the schema is the possibilityin the extracted form to calculate the parasitic capacitors in the layout. This makes thesimulation more accurate.

Schema.

During the comparing of layout and schema (LVS) a lot of errors were found. They werecaused by the fact that till now I had used the standard component library (TECH.QUE)instead of the special AMS0.6 library (PRIM.LIB). After redrawing the schema with theright symbols the problems were gone.

The second change is making the schema hierarchical. Therefor the layout of the pre-amp, the shaper and the bias circuit can be made separately.



The schema of the top-level.

In figure 1 the schema of the top lever is drawn. In this level the preamplifier, the shaperand the bias circuit are symbols, under which a schema, layout and extracted of thecircuit is found.This is also very convenient for simulation, because with switches in 'Analog Artist' wecan choose which of the forms is used in the simulation.To make the influence of the parasitic capacitors visible two extracted form weregenerated, one with and one without the parasitic capacitors.

Figure 1: the top-level schema.



The Pre-amplifier.

In figure 2 the schema of the preamplifier is drawn.

Figure 2: The schema of the pre-amplifier.

The base of the schema is still the same as in earlier documents.The only change is the way the sizes of the components are shown. The width total andthe number of gates are always visual.Based on this schema a layout is made. An impression of this layout is given in figure 3.

Figure 3: The layout of the pre-amplifier.



The layout must meet certain requirements. These are:

1. A pitch of 40 µm.2. The input FET should have multiple gates.3. Some shielding between neighbour channels.4. Bias, power and resistor control as a common bus.

The first demand is due to the form of the detector. The detector has a pitch between thestrips of 40 µm. This pitch causes the design to be relatively long and narrow.Within 40 µm it's possible to make a 15 gate FET with in the figure on top a shieldingline of N-well connectors.The layout is divided into two parts: The left three-quarter and the right quarter.The left three-quarter is the input FET (M0); the rest of the schema is in the other quarter.



The shaper.

In figure 4 the schema of the shaper is drawn.

Figure 4: The schema of the shaper.

Figure 5: The layout of the shaper.

In figure 5 an impression of the layout of the shaper is given.To make compare in size between the pre-amp and the shaper possible, I tried to makethe scale of both plots equal. The shaper looks a little bit wider as the preamplifier,



because the earth rail is drawn in this design as well as on top as on the bottom. Theserails are commonly used by the shaper above and below them.



The simulations.

The most interesting part off course is the simulation of the circuit in extracted form withall the parasitic capacitors. To show the difference between the steps I combined in onegraphic the simulation results of the schema, the extracted without parasitic capacitorsand the extracted with parasitic capacitors.

The pre-amplifier.

In figure 6 the results for the preamplifier are given. In this simulation the shaper wasconnected to the output of the amplifier.As expected in this case the simulation of the schema and the extracted without theparasitic capacitors are the same. With parasitic capacitors the amplifier is a little slower.

Figure 6: Simulation results of the pre-amplifier.

The shaper.

The same has been done with the shaper. The results of the simulation of the wholecircuit are drawn in figure 7. A strange thing in this figure is a DC shift between theschema and the extracted circuits.Also in this case the extracted with parasitic capacitors is a bit slower as without.



Figure 7: The simulation results of the whole circuit.

In figure 8 the influence of the detector capacity on the end result is drawn.Clear is the fact that the capacity should be kept as small as possible, to keep the speedand the signal as high or great as possible.

Figure 8: The influence of the input C.



The bandwidth of the circuit.

In figure 9 the bandwidth of the pre-amplifier is drawn. Clear is that the influence on thebandwidth from the parasitic capacitors on the bandwidth small is.

Figure 9: The bandwidth of the Pre-amplifier.

In figure 10 the bandwidth of the total circuit is drawn. As in figure 9 the influence on thebandwidth of the parasitic capacitors is small.

Figure 10: The bandwidth of the total circuit.



Figure 11: The influence on the bandwidth of the detector capacitor.

Figure 11 shows the influence of the detector capacitor on the bandwidth. Clear is theimportance of keeping the detector capacity as small as possible.



The noise contribution of the circuit.

The noise of the circuit is calculated for the whole circuit only. In figure 12 the noisecharacteristic of the circuit is drawn.

Figure 12: The noise characteristic of the circuit.

The only thing this shows is spectrum of the noise. How bad or good it is, is hardly todetermine from these graphics.Again the noise calculation is done based on the schematic, the extracted withoutparasitic capacitors and on the extracted with parasitic capacitors. The last one of thesegraphics is the lowest one. I think this is caused by the fact that parasitic capacitors formsome kind of low pass filter.To calculate the signal noise factor we need the equivalent noise at the input in electrons.The calculations below give these numbers.

( )( ) ( ) 1192

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(Schematic)

( )( ) ( ) 1191

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(Extracted)

( )( ) ( ) 1092

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(Extracted, capall)

Again the extracted with parasitic capacitors has the lowest noise contribution.



The influence of the detector capacity on the noise.

Till now the noise simulations were made with a detector capacity of 20 pF. To illustratethe importance of an as low as possible detector capacity the simulations were alsocalculated for 5 detector capacity's, see figure 13.

Figure 13: noise spectrum for 5 detector capacity's.

Below the calculation are made for the number of electrons noise.

( )( ) ( ) 243

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(0 pF)

( )( ) ( ) 443

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(5 pF)

( )( ) ( ) 657

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(10 pF)

( )( ) ( ) 874

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(15 pF)

( )( ) ( ) 1092

minmax

12000*1,10=

− outputYoutputY

Gkrmsnoise(20 pF)



0

200

400

600

800

1000

1200

0 5 10 15 20

Capacity (pF)

Noi

se (

elec

tron

s)

Figure 14.

Visual in figure 14 is a linear connection between noise and capacity.

description of the pre-amplifier-shaper with layout

Documents