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PROJECT
Title- SIMULATION AND SYNTHESIS OF 8 BIT RISC PROCESSOR. Platform- RTL Coding (Verilog HDL). Duration- 2 months. Members- Himanshu Gautam , Chandrakant Vashistha , Anoop Srivastav. Description- This project includes the Design of 8 bit RISC Processor and modeling of its component
using Verilog HDL. It is basically an effective computational Engine Designed for basic operation. The instruction set formulated here gives an insight into the kind of hardware which execute them properly. Along with sequential and combinational blocks of registers and more complex block of ALU and Memories have been designed and simulated. This design include additional functionality of calculating LCM, HCF, Factorial.
Project Goal:
Design and Development of simple but effective Hardware Architecture based on RISC Design philosophy.
Design Challenges:
Development of Top level architecture. Implementation of an ISA. State Encoding for Control Unit. Two separate ALU’s. Synchronization of interrupts. Instantiation of sub Modules in top Module.
Enhancements:
Compatible Hardware Coding for calculation of LCM, HCF, Factorial. Design of two separate ALU’s for evaluating more complex Instructions.
Results:
Calculation of LCM, HCF are simulated and verified. Data transfer operation among temporary registers are all checked in ModelSim 10.1a Simulator. Synthesis of top level module is also done on pre synthesis EDA Tool.
Project Cost: Nill.
Contact Information:
Name- Himanshu Gautam
Mob- 8130482681
Email- [email protected]
Address- Rajender Nagar Sahibabad Ghaziabad UP India.