department of electronic engineering chung yuan christian ...department of electronic engineering...
TRANSCRIPT
![Page 1: Department of Electronic Engineering Chung Yuan Christian ...Department of Electronic Engineering Chung Yuan Christian University Critical-PMOS-Aware Clock Tree Design Methodology](https://reader033.vdocuments.site/reader033/viewer/2022060600/60544111e2736564255aa1a2/html5/thumbnails/1.jpg)
Department of Electronic EngineeringDepartment of Electronic EngineeringChung Yuan Christian UniversityChung Yuan Christian University
Critical-PMOS-Aware Clock Tree Design Methodology for
Anti-Aging Zero Skew Clock Gating
Critical-PMOS-Aware Clock Tree Design Methodology for
Anti-Aging Zero Skew Clock Gating
Shih-Hsu Huang, Chia-Ming Chang, Wen-Pin Tu, Song-Bin Pan
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
IntroductionIntroduction
The most common clock distribution is to insert a The most common clock distribution is to insert a number of buffers along the paths from the clock number of buffers along the paths from the clock source to the flipsource to the flip--flops forming a clock tree structure.flops forming a clock tree structure.Clock skew minimization is always an important topic Clock skew minimization is always an important topic in the design of synchronous sequential circuit.in the design of synchronous sequential circuit.Since the clock signal is the most active signal in the Since the clock signal is the most active signal in the circuit, it is also important to distribute the clock circuit, it is also important to distribute the clock signal with low power.signal with low power.Clock gating has been recognized as one of the most Clock gating has been recognized as one of the most effective techniques to reduce the power effective techniques to reduce the power consumption.consumption.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
IntroductionIntroduction
In deep sub-micron era, the NBTI (negative bias temperature instability) effect is a serious concern for the long-term reliability of a circuit.Under a target lifetime (e.g., ten years), the NBTI delay degradation of a PMOS transistor increases with its active probability.The NBTI effect is one source of the clock skew.In this paper, we present the first attempt for anti-aging zero skew clock gating.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries – Buffered Clock TreePreliminaries – Buffered Clock Tree
Buffered Clock TreeBuffered Clock Tree
Small skew but large power
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries – Gated Clock TreePreliminaries – Gated Clock Tree
Clock GatingClock Gating
Larger skew!
Lesser Power!
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries –Conventional Clock Tree
Preliminaries –Conventional Clock Tree
TypeType--Matching Clock Tree can reduce the skew due Matching Clock Tree can reduce the skew due to clock gating.to clock gating.
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Zero skew!
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries – NBTI DelayPreliminaries – NBTI Delay
NBTI (Negative Bias Temperature Instability) effect NBTI (Negative Bias Temperature Instability) effect becomes serious due to thinner gate oxide.becomes serious due to thinner gate oxide.NBTI increases threshold voltage (i.e. increasing NBTI increases threshold voltage (i.e. increasing delay).delay).
P+P+
N
Gate
Source Drain
Bulk
Oxide
Si Si Si Si
HH H H
VG=0
P+P+
N
Gate
Source Drain
Bulk
Oxide
Si Si Si Si
HH H H
VG=Vdd
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries –NBTI while using AND gate
Preliminaries –NBTI while using AND gate
Analyzing the AND gate in a general gated clock tree.Analyzing the AND gate in a general gated clock tree.P3 is P3 is activedactived while En=1while En=1The aging delay of PMOS P3 The aging delay of PMOS P3 is proportional to is proportional to the the activeactiveprobability of En signal probability of En signal
C
EnY
P1 P2
N2
N1P3
N3
VDD
Vss
C
C En
En
Y1
Aging!
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries –Skew Due to Degradation DifferencePreliminaries –Skew Due to Degradation Difference
C
EnY
P1 P2
N2
N1P3
N3
VDD
Vss
C
C En
En
YProbability 20% Different Delay
Degradations!
C
EnY
P1 P2
N2
N1P3
N3
VDD
Vss
C
C En
En
YProbability 60%
Delay = 0.3
Delay = 0.5
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Preliminaries –Weakness of Conventional Clock Tree
Preliminaries –Weakness of Conventional Clock Tree
As time goes by, the NBTI effect causes the aging As time goes by, the NBTI effect causes the aging skew if the probabilities of enable signals are skew if the probabilities of enable signals are different.different.
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Aging skew!
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Conventional Clock TreeConventional Clock Tree
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Conventional Clock Tree in Circuit LevelConventional Clock Tree in Circuit Level
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System VLSI / CAD Lab.System VLSI / CAD Lab.
If registers areIf registers are risingrising--edgeedge--triggeredtriggered
en7 affects U7/P3 en5 affects U5/P3 en1 affects U1/P3
Aging effect needs to be considered in every level
Conventional Clock Tree in Circuit LevelConventional Clock Tree in Circuit Level
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System VLSI / CAD Lab.System VLSI / CAD Lab.
en7 affects U5/P1 en5 affects U1/P1 En1 affects nothing
Only one “free” level in the clock tree
If registers are fallingIf registers are falling--edgeedge--triggeredtriggered
Conventional Clock Tree in Circuit LevelConventional Clock Tree in Circuit Level
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System VLSI / CAD Lab.System VLSI / CAD Lab.
en7 affects U7/P3 en5 affects U5/P3 en1 affects U1/P3
Aging effect needs to be considered in every level
en7 affects U5/P1 en5 affects U1/P1 En1 affects nothing
Only one “free” level in the clock tree
Conventional Clock Tree in Circuit LevelConventional Clock Tree in Circuit Level
At least n-1 levels
are the “must” level
in conventional clock tree
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System VLSI / CAD Lab.System VLSI / CAD Lab.
How to solve this aging skew problem ?How to solve this aging skew problem ?
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Since the PMOS transistors at the same level Since the PMOS transistors at the same level have different active probabilities, we can have different active probabilities, we can increase the active probabilities of clock gates increase the active probabilities of clock gates to ensure that the clock gates at the same to ensure that the clock gates at the same level always have the same active probability.level always have the same active probability.
How to solve this aging skew problemHow to solve this aging skew problem
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System VLSI / CAD Lab.System VLSI / CAD Lab.
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The delay degradation of each clock gate is linearly proportional to the active probabilities of PMOS transistors.
40 power units
20 power units
30 power units
20 power units
8 power units
6 power units
Aging skew!124 power units
Conventional Clock Tree –an Example
Conventional Clock Tree –an Example
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System VLSI / CAD Lab.System VLSI / CAD Lab.
CY
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The delay degradation of each clock gate is linearly proportional to the active probabilities of PMOS transistors.
Conventional Clock Tree –an Example
Conventional Clock Tree –an Example
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System VLSI / CAD Lab.System VLSI / CAD Lab.
CY
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40 power units
40 power units
8 power units
If the active probabilities of clock gates at the If the active probabilities of clock gates at the same level are the same, the NBTI delay same level are the same, the NBTI delay degradations will be the same.degradations will be the same.
20 power units
20 power units
6 power units
40 power units
40 power units
8 power units
176 power units
Conventional Clock Tree –an Example
Conventional Clock Tree –an Example
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Although weAlthough we can eliminate the aging skew by can eliminate the aging skew by increasing the active probabilities of clock gates , it increasing the active probabilities of clock gates , it requires extra 52 power units.requires extra 52 power units.
CLK
U1
U2
U3
U4
U5
U6
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D QD Q
D QD Q
D QD Q
D QD Q
U7C Y
176 units124 units
Conventional Clock Tree –an Example
Conventional Clock Tree –an Example
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Drawback of Conventional TreeDrawback of Conventional Tree
IIn worst case, every level is the n worst case, every level is the ““mustmust”” levellevelIIt t requiresrequires large power to eliminate aging skew large power to eliminate aging skew
Aging effect needs to be considered in every level
Only a ‘free’ level in the clock tree
172units134 units
Too many
“must” levels Requires large power
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree (1/2)Anti-Aging Clock Tree (1/2)
Since the NBTI only affects PMOS transistors, by Since the NBTI only affects PMOS transistors, by carefully planning the clock signal propagation paths, carefully planning the clock signal propagation paths, we can let the active probabilities do not affect the we can let the active probabilities do not affect the degradation difference.degradation difference.
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P1 P2
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N1P3
N3
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N2
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11
NBTI !!
111
0Avoid PMOS
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree (2/2)Anti-Aging Clock Tree (2/2)
In our design methodology, we use NANDIn our design methodology, we use NAND--typetype--matching clock tree.matching clock tree.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree in Circuit LevelAnti-Aging Clock Tree in Circuit Level
P1 P2
N2
N1
en1
VDD
en1
Vss
P1 P2
N2
N1
en5
VDD
en5
Vss
P1 P2
N2
N1
en7
VDD
en7
Vss
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System VLSI / CAD Lab.System VLSI / CAD Lab.
If registers are rising-edge-triggered
Anti-Aging Clock Tree in Circuit LevelAnti-Aging Clock Tree in Circuit Level
P1 P2
N2
N1
en1
VDD
en1
Vss
P1 P2
N2
N1
en5
VDD
en5
Vss
P1 P2
N2
N1
en7
VDD
en7
Vssen7 affects nothing en5 affects U1/P1 en1 affects nothing
Aging effect needs to be considered in even levels
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree in Circuit LevelAnti-Aging Clock Tree in Circuit Level
IfIf registers are fallingregisters are falling--edgeedge--triggeredtriggered
en7 affects U5/P1 en5 affects nothing en1 affects nothing
Aging effect needs to be considered in odd levelsexcept for level 1
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree in Circuit LevelAnti-Aging Clock Tree in Circuit Level
en7 affects nothing en5 affects U1/P1 en1 affects nothing
Aging effect needs to be considered in even levels
en7 affects U5/P1 en5 affects nothing en1 affects nothing
Aging effect needs to be considered in odd levelsexcept for level 1
At most ⎩n/2 ⎭ levels
are the “must” level
in our anti-aging clock tree
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree –an Example
Anti-Aging Clock Tree –an Example
Aging skew!
40 power units
20 power units
30 power units
20 power units
8 power units
6 power units
124 power units
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree –an Example
Anti-Aging Clock Tree –an Example
40 power units
20 power units
30 power units
20 power units
8 power units
6 power units8 power units
126 power units
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Anti-Aging Clock Tree –an Example
Anti-Aging Clock Tree –an Example
After tenAfter ten--year operation, the clock skew of clock tree year operation, the clock skew of clock tree is still 0 ps. Compared with is still 0 ps. Compared with AND-type antianti--aging aging clock tree, it saves a lot of power consumption.clock tree, it saves a lot of power consumption.
126 power units124 power units
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Advantages of Anti-Aging Clock TreeAdvantages of Anti-Aging Clock Tree
In worst case, only levels need to be consideredIt requires less power consumption to eliminate aging skewIt is still a type-matching clock tree. Therefore, our anti-aging clock tree has all the benefits of type-matching clock tree.
Aging effect needs to be considered in only 2i level
Aging effect needs to be considered in only 2i+1 level
At most ⎩n/2 ⎭ levels
are the “must” level
in anti-aging clock tree
126 power units124 power units
Save power
n/2⎢ ⎥⎣ ⎦
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
ILP Formulations – Formula 1ILP Formulations – Formula 1
Formula 1Formula 1–– If clock gate u is active at control step s in the original If clock gate u is active at control step s in the original
clock tree, then clock gate u must be also active at clock tree, then clock gate u must be also active at control step s in the anticontrol step s in the anti--aging clock tree.aging clock tree.
, ,u s u sX a≥
CLK
U1
U2
U3
U4
U5
U6
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D QD Q
D QD Q
D QD Q
D QD Q
U7C Y CLK
U1
U2
U3
U4
U5
U6
CY
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E
CY
CY
Een6
en2
en4
C
EY
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CY
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CY
Een1
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D QD Q
D QD Q
D QD Q
D QD Q
U7C Y
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System VLSI / CAD Lab.System VLSI / CAD Lab.
CY
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CY
CY
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D QD Q
D QD Q
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C Y
ILP Formulations – Formula 2ILP Formulations – Formula 2
Formula 2Formula 2–– Consider the antiConsider the anti--aging clock tree. If clock gate u is aging clock tree. If clock gate u is
active at control stepactive at control step s, then its predecessor gate v s, then its predecessor gate v must be also active at control step s.must be also active at control step s.
, ,v s u sX X≥
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System VLSI / CAD Lab.System VLSI / CAD Lab.
ILP Formulations – Formula 3ILP Formulations – Formula 3
Formula 3Formula 3
–– Consider the antiConsider the anti--aging clock tree. If clock gate u and aging clock tree. If clock gate u and clock gate v are atclock gate v are at the same the same ““mustmust”” level, they must level, they must have the same active probabilityhave the same active probability..
, ,u s v ss B s B
X X∈ ∈
=∑ ∑
CY
E
E
CY
CY
Een6
en2
en4
C
EY
E
CY
en3
CY
Een1
en5
D QD Q
D QD Q
D QD Q
D QD Q
C Y
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System VLSI / CAD Lab.System VLSI / CAD Lab.
ILP Formulations for Enable Logics –Objective Function
ILP Formulations for Enable Logics –Objective Function
MinimizationMinimization
–– Our objective function is to minimize the power Our objective function is to minimize the power consumption overheadconsumption overhead..
, , , ,u s u s u s u su A s B u A s B
X P a P∈ ∈ ∈ ∈
× − ×∑∑ ∑∑
CLK
U1
U2
U3
U4
U5
U6
CY
E
E
CY
CY
Een6
en2
en4
C
EY
E
CY
en3
CY
Een1
en5
D QD Q
D QD Q
D QD Q
D QD Q
U7C Y CLK
U1
U2
U3
U4
U5
U6
CY
E
E
CY
CY
Een6
en2
en4
C
EY
E
CY
en3
CY
Een1
en5
D QD Q
D QD Q
D QD Q
D QD Q
U7C Y
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results - Design FlowExperimental Results - Design Flow
We use six benchmark circuits, which are targeted to We use six benchmark circuits, which are targeted to TSMC 0.13TSMC 0.13μμm process technology, to test the m process technology, to test the effectiveness of our design methodology.effectiveness of our design methodology.Our Design FlowOur Design Flow
Type-matching clock tree synthesisExtended LINGO Release 10.0 as the ILP solver for
the modification of logics of enable signals
Synopsys PrimePower for gate-level power analysis
SOC Encounter to obtain the placements of gate-level netlists
SOC Encounter to perform ECO placement
Synopsys Hspice perform reliability simulation
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results - ComparisonsExperimental Results - Comparisons
We derive the following four clock trees for We derive the following four clock trees for comparisons.comparisons.–– TreeTree--AA
The ANDThe AND--typetype--matching clock tree.matching clock tree.–– TreeTree--BB
The antiThe anti--aging ANDaging AND--typetype--matching clock tree. Note that matching clock tree. Note that this clock tree is the antithis clock tree is the anti--aging version of Treeaging version of Tree--A. A.
–– TreeTree--CCThe NANDThe NAND--typetype--matching clock tree.matching clock tree.
–– TreeTree--D (our clock tree)D (our clock tree)This clock tree is the antiThis clock tree is the anti--aging version of Treeaging version of Tree--C. C.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results –Original Clock Skew
Experimental Results –Original Clock Skew
0
40
80
120
160
200
S15850.1 S38584 S38584.1 IDCT2 Motion Sha1
Tree-A Tree-B Tree-C Tree-D (Ours)
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results –Five-Year Clock Skew
Experimental Results –Five-Year Clock Skew
0
40
80
120
160
200
S15850.1 S38584 S38584.1 IDCT2 Motion Sha1
Tree-A Tree-B Tree-C Tree-D (Ours)
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results –Ten-Year Clock Skew
Experimental Results –Ten-Year Clock Skew
0
40
80
120
160
200
S15850.1 S38584 S38584.1 IDCT2 Motion Sha1
Tree-A Tree-B Tree-C Tree-D (Ours)
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results –Power Consumptions
Experimental Results –Power Consumptions
Power Consumptions of four type trees (Power Consumptions of four type trees (μμww).).
0
5
10
15
20
25
S15850.1 S38584 S38584.1 IDCT2 Motion Sha1
Tree-A Tree-B Tree-C Tree-D (Ours)
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Experimental Results –Analysis to Circuit S35932
Experimental Results –Analysis to Circuit S35932
The slopes of TreeThe slopes of Tree--B and TreeB and Tree--D are small, while the D are small, while the slopes of Treeslopes of Tree--A and TreeA and Tree--C are large.C are large.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
OutlineOutline
IntroductionIntroductionPreliminariesPreliminariesThe Drawback of Conventional Clock TreeThe Drawback of Conventional Clock TreeAntiAnti--Aging Clock TreeAging Clock TreeILP Formulations for Enable Logic ModificationILP Formulations for Enable Logic ModificationExperimental ResultsExperimental ResultsConclusionsConclusions
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System VLSI / CAD Lab.System VLSI / CAD Lab.
ConclusionsConclusions
We present the first attempt for ensuring that the We present the first attempt for ensuring that the clock skew is always zero during the circuit life.clock skew is always zero during the circuit life.Our criticalOur critical--PMOSPMOS--aware clock tree design aware clock tree design methodology includes two main aspects.methodology includes two main aspects.–– We prove that the number of We prove that the number of ““mustmust--levelslevels”” of NANDof NAND--
typetype--matching clock tree is the lower bound that any matching clock tree is the lower bound that any clock tree can achieve. clock tree can achieve.
–– We propose a 0We propose a 0--1 ILP approach to minimize the power 1 ILP approach to minimize the power consumption.consumption.
Benchmark data consistently show that our Benchmark data consistently show that our methodology can eliminate the degradation methodology can eliminate the degradation difference with almost negligible power consumption difference with almost negligible power consumption overhead.overhead.
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System VLSI / CAD Lab.System VLSI / CAD Lab.
Thank you !Thank you !