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Department of ECE

Prepared by D.Manjula Rani and K.Ch.Prathap Kumar M.

CVSR COLLEGE OF ENGINEERING, GHATKESAR.

SUBJECT : VLSI DESIGN

FACULTY : D. Manjula Rani

K.Ch.Prathap Kumar M.

VLSI HANDBOOK

CONTENTS

S.

No. Title

Page

No.

1 Syllabus 2

2 Lesson Plan 3

3 Course Objectives 4

4 Prerequisites 5

5 Topics covered

6.1 Core Topics

6.2 Topics Covered beyond the syllabus

5-6

6 Text books and References 6

7 Action & Assessment plan (to improve the course plan to meet the objectives)

8.1 Actions

8.1 Assignments

8.2 Assessment plan for Actions

6

8 Lecture Notes (Unit-wise) 9

UNIT-1

1.1 Introduction to VLSI Technology

1.2 Operation of MOS, PMOS, NMOS

1.3 Fabrication of NMOS & PMOS

1.4 Fabrication of CMOS

1.5 Oxidation, Lithography, Diffusion

1.6 Ion implantation, Metallisation, Encapsulation

1.7 Probe testing

1.8 Integrated Resistors and Capacitors

Total classes to complete UNIT-I

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UNIT-II

2.1 Drain to source current vs voltage relationships of MOS

2.1 MOS transistor Threshold voltage and Figure of merit

2.3 Pass transistor, NMOS Inverter

2.4 Determination of Pull-up to Pull-down ratio

2.5 CMOS Inverter analysis and design

2.6 Bi-CMOS Inverters

2.7 Total classes to complete UNIT-II

UNIT-III

3.1 VLSI Design Flow, MOS Layers

3.2 Stick Diagrams

3.3 Design Rules and Layout, CMOS Design rules for wires

3.4 Contact cuts, Layout Diagrams for NMOS and CMOS Inverters and Gates

3.5 Scaling of MOS circuits

3.6 Limitations of Scaling

3.7 Total classes to complete UNIT-III

UNIT-IV

4.1 Logic Gates and other complex gates

4.2 Switch Logic, Alternate gate circuits, Basic circuit concepts

4.3 Sheet Resistance RS and its concept to MOS

4.4 Area Capacitance of Layers

4.5 Calculation of Delays

4.6 Driving Large Capacitive Loads, Fan-in and Fan-out

4.7 Wiring Capacitances, Choice of Layers

4.8 Total classes to complete UNIT-IV

UNIT-V

5.1 Subsystem Design, Shifters, Adders

5.2 ALUs

5.3 Multipliers

5.4 Parity generators, Comparators

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5.5 Zero/One Detectors, Counters

5.6 High Density Memory Elements

5.7 Total classes to complete UNIT-V

UNIT-VI

6.1 Design of PLAs

6.2 Design of FPGAs

6.3 Design of CPLDs

6.4 Standard Cells

6.5 Design of PALs

6.6 Exercise problems

Total classes to complete UNIT-VI

UNIT-VII

7.1 VHDL Synthesis

7.2 Circuit Design Flow, Circuit Synthesis

7.3 Simulation, Layout

7.4 Design capture tools

7.5 Design verification tools

7.6 Test Principles

7.7 Total classes to complete UNIT-VII

UNIT-VIII 144

8.1 CMOS Testing, Need for testing 172

8.2 Test Principles, Design Strategies for test

8.3 Chiplevel Test Techniques

8.4 System Level Test Techniques

8.5 Layout Design for improved Testability

8.6 Total classes to complete UNIT-VIII

8.7 TOTAL NO OF CLASSES

1. SYLLABUS

VLSI DESIGN

UNIT I

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INTRODUCTION : Introduction to IC Technology – MOS, PMOS, NMOS, CMOS &

BiCMOS technologies- Oxidation, Lithography, Diffusion, Ion implantation, Metallisation,

Encapsulation, Probe testing, Integrated Resistors and Capacitors.

UNIT II

BASIC ELECTRICAL PROPERTIES : Basic Electrical Properties of MOS and

BiCMOS Circuits: Ids-Vds relationships, MOS transistor threshold Voltage, gm, gds,

Various pull ups, CMOS Inverter

analysis and design, Bi-CMOS Inverters.

UNIT III

VLSI CIRCUIT DESIGN PROCESSES: VLSI Design Flow, MOS Layers, Stick

Transistors Layout Diagrams for NMOS and CMOS Inverters and Gates, Scaling of MOS

circuits, Limitations of Scaling.

UNIT IV

GATE LEVEL DESIGN : Logic Gates and Other complex gates, Switch logic, Alternate

gate circuits, Basic circuit concepts, Sheet Resistance RS and its concept to MOS, Area

Capacitance Units, Calculations - - Delays, Driving large Capacitive Loads, Wiring

Capacitances, Fan-in and fan-out, Choice of layers

UNIT V

SUBSYSTEM DESIGN : Subsystem Design, Shifters, Adders, ALUs, Multipliers, Parity

generators, Comparators, Zero/One Detectors, Counters, High Density Memory Elements.

UNIT VI

ARRAY SUBSYSTEMS:

SRAM, DRAM, ROM, serial access memory, cam.

UNIT VI I

SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN : PLAs, FPGAs, CPLDs,

Standard Cells, Programmable Array Logic, Design Approach.

UNIT VIII

CMOS TESTING : CMOS Testing, Need for testing, Test Principles, Design Strategies

for test, Chiplevel Test Techniques, System-level Test Techniques, Layout Design for

improved Testability.

TEXTBOOKS :

1. Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian

Dougles and A.Pucknell, PHI, 2005 Edition

2. Principles of CMOS VLSI Design – Weste and Eshraghain, Pearson

Education, 1999

3. Modern VLSI Design – Wayne Wolf, Pearson Education, 3rd

Edition, 1997

4.VHDL-Programming by example-Douglas perry Third Edition

REFERENCES :

1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P. Uyemura,

Thomson Learning.

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2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.

3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.

5. VLSI Technology – S.M. SZE, 2nd

Edition, TMH, 2003.

2 LESSON PLAN

S.No Name of the Topic

No of

Classes

UNIT-I

1 Introduction to VLSI Technology 1

2 Operation of MOS, PMOS, NMOS 1

3 Fabrication of NMOS & PMOS 1

4 Fabrication of CMOS 1

5 Oxidation, Lithography, Diffusion 1

6 Ion implantation, Metallisation, Encapsulation 1

7 Probe testing 1

8 Integrated Resistors and Capacitors 1

Total classes to complete UNIT-I 8

UNIT-II

9 Drain to source current vs voltage relationships of MOS 2

10 MOS transistor Threshold voltage and Figure of merit 1

11 Pass transistor, NMOS Inverter 1

12 Determination of Pull-up to Pull-down ratio 2

13 CMOS Inverter analysis and design 1

14 Bi-CMOS Inverters 1

Total classes to complete UNIT-II 8

UNIT-III

15 VLSI Design Flow, MOS Layers 1

16 Stick Diagrams 2

17 Design Rules and Layout, CMOS Design rules for wires 2

18 Contact cuts, Layout Diagrams for NMOS and CMOS Inverters

and Gates

3

19 Scaling of MOS circuits 1

20 Limitations of Scaling 1

Total classes to complete UNIT-III 10

UNIT-IV

21 Logic Gates and other complex gates 1

22 Switch Logic, Alternate gate circuits, Basic circuit concepts 2

23 Sheet Resistance RS and its concept to MOS 1

24 Area Capacitance of Layers 1

25 Calculation of Delays 1

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26 Driving Large Capacitive Loads, Fan-in and Fan-out 1

27 Wiring Capacitances, Choice of Layers 1

Total classes to complete UNIT-IV 8

UNIT-V

28 Subsystem Design, Shifters, Adders 1

29 ALUs 2

30 Multipliers 1

31 Parity generators, Comparators 1

32 Zero/One Detectors, Counters 2

33 High Density Memory Elements 1

Total classes to complete UNIT-V 8

UNIT-VI

34 Design of PLAs 2

35 Design of FPGAs 1

36 Design of CPLDs 1

37 Standard Cells 1

38 Design of PALs 1

39 Exercise problems 1

Total classes to complete UNIT-VI 7

UNIT-VII

40 VHDL Synthesis 1

41 Circuit Design Flow, Circuit Synthesis 2

42 Simulation, Layout 1

43 Design capture tools 1

44 Design verification tools 1

45 Test Principles 2

Total classes to complete UNIT-VII 8

UNIT-VIII

46 CMOS Testing, Need for testing 1

47 Test Principles, Design Strategies for test 2

48 Chiplevel Test Techniques 2

49 System Level Test Techniques 1

50 Layout Design for improved Testability 2

Total classes to complete UNIT-VIII 8

TOTAL NO OF CLASSES 65

3. COURSE OBJECTIVES:

1. Understand the growth of IC Technology by conducting a quiz/seminar.

2. Understand the impact of the physical and chemical processes of integrated circuit

fabrication technology on the design of integrated circuits.

3. Understand physics of the Crystal growth, wafer fabrication and basic electrical

properties of silicon wafers.

4. Learn how to design MOS circuits using stick diagrams and layouts-Assignments

5. Understand the design of logic gates and subsystems using MOS transistors.

6. Learn different testing strategies of CMOS circuits.

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7. Developing a miniproject /paper presentation on

4. PREREQUISITES BY TOPIC:

1. The fundamental operation of semiconductor devices and their circuit applications.

2. The physical principles of semiconductors, emphasizing silicon technology; operating

principles and device equations for PN diodes, biasing, and elementary circuit

applications of diodes.

3. Basic operating principles and device equations for MOS capacitors and transistors, and

bipolar junction transistors.

4. The basics of transistor amplifier and logic circuit design using MOS transistors

5. Topics to be covered

5.1: Topics covered

Fabrication and electrical properties of MOS transistors

VLSI circuit design processes and layout diagrams

Gate level and subsystem design using MOS transistors

Semiconductor integrated circuit design approach

VHDL synthesis and CMOS testing

5.2: Topics to be covered beyond the syllabus

Non ideal I-V effects of characteristics of MOS transistor

Transmission Gates

6. Text books and References

TEXTBOOKS :

1. Essentials of VLSI circuits and systems – Kamran Eshraghian, Eshraghian

Dougles and A.Pucknell, PHI, 2005 Edition

2. Principles of CMOS VLSI Design – Weste and Eshraghain, Pearson

Education, 1999

3. Modern VLSI Design – Wayne Wolf, Pearson Education, 3rd

Edition, 1997

4.VHDL-Programming by example-Douglas perry Third Edition

REFERENCES :

1. Chip Design for Submicron VLSI: CMOS Layout & Simulation, - John P.

Uyemura, Thomson Learning.

2. Introduction to VLSI Circuits and Systems - John .P. Uyemura, JohnWiley, 2003.

3. Digital Integrated Circuits - John M. Rabaey, PHI, EEE, 1997.

5. VLSI Technology – S.M. SZE, 2nd

Edition, TMH, 2003.

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7. Assignments:

Instructions:

All the assignments should be in either printed MS Word or Written documents with the

following requirements.

1) Cover page with name, course name and course section.

2) A page with assignments tasks.

3) Solutions/Explanations.

Two assignments are given to the students during the course.

Assignments:

1. Describe the two commonly used methods for obtaining integrated capacitor.

2. With neat sketches, explain in detail, all the steps involved in electron lithography

process.

3. What is Moore’s law? Explain its relevance with respect to evolution of IC

Technology.

4. With neat sketches explain the fabrication of CMOS inverter using p-well process.

5. Explain in detail about NMOS enhancement mode of operation.

6. Explain various regions of CMOS inverter transfer characteristics.

7. For a CMOS inverter, calculate the shift in the transfer characteristic curve

When βn/βp ratio is varied from 1/1 to 10/1.

8. Explain nMOS inverter and latch up in CMOS circuits?

9. Derive an equation for IDS of an n-channel Enhancement MOSFET operating

in Saturation region.

10. An nMOS transistor is operating in saturation region with the following parameters.

VGS = 5V; Vtn = 1.2V ; W/L = 110; μnCox = 110 μA/V 2.

Find Transconductance of the device.

11. What are design rules? Why is metal- metal spacing larger than poly –poly spacing.

12. Draw the stick diagram and mask layout for a CMOS two input NOR gate and

Stick diagram of two input NAND gate.

13. Draw the stick diagram and a translated mask layout for nMOS inverter circuit.

14. Explain the following

(a) Double metal MOS process rules.

(b) Design rules for P- well CMOS process

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15. Describe three sources of wiring capacitances. Explain the effect of wiring capacitance

on the performance of a VLSI circuit.

16. Define and explain the following:

i. Sheet resistance concept applied to MOS transistors and inverters.

ii. Standard unit of capacitance.

17. Explain the requirement and functioning of a delay unit.

18. Two nMOS inverters are cascaded to drive a capacitive load CL=14Cg as shown in

Figure. Calculate the pair delay Vin to Vout in terms of τ for the given data.

Inverter -A

LP.U= 12λ , WP.U = 4 λ , LP.d = 1 λ , WP.d = 1 λ

Inverter -B


9. Lecture Notes (Unit-wise)

9.1 Unit-1

1.1) Introduction to VLSI Technology:

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1Q). Explain the term SSI, LSI, VLSI and reference of feature size, number of transistor per chip and applications?

UNIT -1

Logic families: --Transistor is invented by Williams B. schockley in 1947. --Walter H. Brattains & J. Bardeen of bell laboratory developed first IC in 1960. MOS FAMILIES: NMOS is good but it has some amount of power dissipation. CMOS possess the least power dissipation as at least one of the devices is off. This technology is dominant fabrication process for relatively high performance and cost effective VLSI circuits.

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With such progress in RISC chips, it is possible to process 35 million instructions per second. The scaling and processing is possible in BICMOS technology. It is the compromise between CMOS and Bipolar technology. By these 100 million instructions per second is possible. GaAs(Gallium Arsenide)technology: By using this ultra high speed logic / fast digital processors are developed.

The IC Era: The silicon ICs that they’re made an extremely rapid growth in the number of transistors (miniature) being integrated (measure of complexity) into circuits on single silicon chip. MOORE’S Law (prediction): The number of transistors integrated on a single chip doubles for every 18 months. MOORE’S predictions have largely come true except for an increasing divergence between prediction and actual over last few years due to the problems associated with complexities involved in designing and testing such very large circuits.

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Moore’s Law: Gordon Moore: co-founder of Intel.

Predicted that number of transistors per chip

would grow exponentially (double every 18

months).

Exponential improvement in technology is a

natural trend: steam engines, dynamos, and

automobiles.

Speed &power performance of available technology:

YEAR

Technology Invention Of transistor

Discrete components

SSI MSI LSI VLSI ULSI

GSI

Approximate no. of transistor per chip incommercial product

1 1 10 100-1000

1000-20000

20000-106

106-108

>108

Typical products

- Transistor

Planar devices gates FFS

Counter Mux,adders

8-bit Up ROM &RAM

16 &32 bit processor

Special processor

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VLSI FUTURE TRENDS: 1998: 2 MILLION GATE/DIE 2001: 5 MILLION GATE/DIE 2002: 1 GIGABIT MEMORY CHIPS 2003: 10 n.m PATTERNS, LINE WIDTH 2004: COMMMERCIAL SUPER COMP. 10T. FLIP FLOPS 2010: NEORO – COMPUTER USING LOGIC

STRUCTURE BASED ON HUMAN BRAIN

BICMOS,GA.As ICs CMOS…..BIPOLAR WILL VANISH BY 2000 VDD…3.3V -> 1.5V, TECH…..0.6uM

In this crossing each boundary requires new design methodologies, simulation methods and new methods for determining and routing communication and for handling complexity.

Truly 1970s, 1980s and now 1990s may be well described as IC era .

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The cost of fabrication Current cost: $2-3 billion.

Typical fab line occupies about 1 city block,

employs a few hundred people.

Most profitable period is first 18 months-2 years.

Cost factors in ICs For large-volume ICs:

–packaging is largest cost;

–testing is second-largest cost.

For low-volume ICs, design costs may swamp all

manufacturing costs.

Challenges in VLSI design

Multiple levels of abstraction: transistors to

CPUs.

Multiple and conflicting constraints: low cost and

high performance are often at odds.

Dealing with complexity Divide-and-conquer: limit the number of

components you deal with at any one time.

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Group several components into larger

components:

–transistors form gates;

–gates form functional units;

–functional units form processing elements;

–etc.

Short design time: Late products are often

irrelevant.

Hierarchical name

Interior view of a component:

–components and wires that make it up.

Exterior view of a component = type:

–body;

–pins.

2Q)Explain the structures of NMOS enhancement mode, depletion mode and PMOS enhancement transistors?

NMOS and PMOS: A MOSFET with p-type substrate, n-type source and n-type drain regions, the channel that has to be formed on the surface should be n-type region. Such a p-type substrate MOSFET is called an n-channel MOSFET.

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STRUCTURE of Enhancement Mode MOSFET:

SYMBOL:

In this, electrons as in figure replace holes. In other words an n-channel is formed by the +ve voltage at the gate which exceeds the threshold voltage (VT) and current flows. N-Channel Depletion Mode MOSFET:

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The n-channel depletion mode mosfet is different from n-channel enhancement mode MOSFET in having a channel by forming a thin n-type layer embedded underneath the gate. When a +ve voltage applied at the drain, a current flows through this channel even if the voltage at gate is 0 volts. As the gate voltage becomes more +ve , the channel becomes denser carrying a greater current (or) as the gate voltage becomes more negative, the channel becomes thinner carrying a smaller current. If the gate voltage decreases beyond threshold voltage, no current flows. The drain (o/p) characteristics from n-channel MOS, which may be, used either the enhancement or depletion mode.

P-Channel Enhancement Mode: In this MOSFET with n-type substrate and with p+source and drain regions, on the other hand, the channel is p-type and device is called PMOS.

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Symbols

When voltages are applied to the drain, source and gate of p-channel enhancement MOS as shown in fig

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A thin layer of channel for holes is formed underneath the gate and current, which consist of holes moving from source to drain flows. When the voltage of the gate becomes more -ve, the channel becomes denser and greater current flows. The channel has a thickness of less than 100 Å (in contrast, the insulation Layer between gate and substrate has thickness of the order of 100 Å ).The stream of holes is restricted to a very thin layer close to the surface, unlike the bipolar transistor where the stream of holes and electrons flows in a much deeper place. When the voltage at the gate increases toward a +ve voltage, the channel gets thinner and beyond a certain value, which is called ‘threshold voltage’, the channel is not completely formed and no current flows. [VGS

> VT => Id=0]

Comparison of P-MOS and N-MOS :- N-channel MOS have some inherent performance advantages over PMOS. The mobility of electrons, which are carriers in the case of an NMOS, is about 2.5 times greater than that of holes, which are carriers in PMOS .Thus n-channel is faster than p-MOS.

PMOS well suited technology and is less expensive than NMOS.

PMOS enhancement is very popular in MOS systems because it is much easier to produce than n-MOS.

PMOS device must have more than twice the area of the NMOS device to achieve the same resistance .The NMOS can be smaller for the same complexity than PMOS devices.

The higher packing density of NMOS also makes it faster in switching applications due to smaller junction areas.

For all the above reasons it is clear that NMOS circuits are more desirable than PMOS circuits. However, the more extensive process control needed for n-channel fabrication makes them expensive and unable to compete economically with PMOS.

conductivity factor k is high for NMOS and k is low for PMOS

Threshold voltage (VT) is high for NMOS and VT is low for PMOS.

Turn-on time (ton) is less for NMOS and high for PMOS.

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1.2)operation of MOS,PMOS,NMOS transistors

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1.3)Fabrication of CMOS inverter

Basic CMOS Technology

In early days of technology, the control gate of the MOS transistor was made with

aluminum instead of polycrystalline silicon. It was difficult to align the metal over the

channel precisely; an offset in one direction or other would create a non-functioning of the

transistor. To overcome these problems, the poly-silicon gate was introduced. This

polysilicon would be deposited before source/drain diffusion. During the diffusion, source

and drain regions are self-aligned with respect to the gate. This self-alignment structure

reduces the device size. In addition, it eliminates the large overlap capacitance between

gate and drain, while maintaining a continuous inversion layer between source and drain. In

the case of metal gate process, Al deposition has to be carried out almost at the end of

fabrication because further high temperature processing would melt Al. In case of self-

aligned poly silicon gate technology, these restrictions are also circumvented.

Basic n-well CMOS process

In a standard n-well process, one of the first things made is the n-well in a p type substrate.

Once the n-well is created, the active areas can be defined. The MOSFET is build within

this active area. A very thin layer of silicon dioxide is grown on the surface. This will be

used to insulate the gate from the surface. The thin layer of SiO2 is grown and covered with

Si3N4. This will act as a mask during the subsequent channel stop implant and field oxide

growth. The channel stop implant is to prevent conduction between unrelated transistor

source/drains. A thick additional layer oxide grows in both directions vertically where

Si3N4 is absent. Layer of silicon dioxide under the polysilicon gate (which will be created

later) is known as gate oxide and that is not directly under the gate of a transistor is known

as field oxide. The field oxide provides isolation between transistors. A threshold

adjustment implant would be the next process step. This is carried out to balance off the

threshold voltage differences. The P-MOS results in a higher threshold voltage level than

nMOS with normal doping concentrations. With additional negative charges buried inside

the channel, VT for pMOS could be controlled.

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(a)

Formation of n-well

(b)

Gate oxide covered with silicon nitride in the active areas

Polysilicon deposition is carried out and gate definition is then completed using the mask

shown in fig (c). Note that the connection between two gate inputs in a CMOS inverter is

achieved using the poly silicon. The source and drain diffusions for pMOS is carried out

using p-type diffusion. Boron is the most popular element used for this step. Similarly,

source and drain diffusions for nMOS is carried out using n-type diffusion. Phosphorous

and Arsenic can both be used for this step. Additional oxide is created, and then the contact

holes are cut in the oxide down to the diffusions and polysilicon. These contacts can be

filled by metal permitted to flow into the holes. The drains of pMOS and nMOS transistors

are connected by a metal line in order to take the output from the CMOS inverter.

©

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Top view of Poly silicon mask

(d)

Poly silicon gate definition is completed

(e)

Transistor source/drain diffusion is completed

(f)

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Cross section of a CMOS inverter in an n-well process

P-well process

Prior to the n-well process p-well process was popular. P-well process is preferred in

circumstances where balanced characteristics of the nMOS and pMOS are needed. It has

been observed that the transistors in the native substrate tend to have better characteristics

than that was made in a well. Because p devices inherently have lower gain than devices, n

well process amplifies this difference while a p-well process moderates the difference. The

standard p-well process steps are is similar to n-well process, except that a p-well is

implanted instead of an n-well as a first step. Once the p-well is created, the active areas

and subsequently poly gates can be defined. Later diffusions can be carried out to create

source and drain regions. Finally, metal is deposited and patterned for contacts.

Twin-Tub process

It is also possible to create both a p-well and an n-well for the n-MOSFET's and p-

MOSFET respectively in the twin well or twin tub technology. Such a choice means that

the process is independent of the dopant type of the starting substrate (provided it is only

lightly doped).

A simplified sketch of twin-well CMOS process cross section

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MOS inverters: MOS inverters all use an enhancement-mode device (EMD) as a switching transistor to pull the O/P, because it can be switched off when I/P signal to its gate is low. In the off mode it draws negligible current from supply. The pull –up can be simple resistor, an EMD operating as a current source with its gate connected to the positive supply, a depletion-mode device (DMD) operating as current source with its gate short circuited to its source, or a PMOS EMD acting as a pull-up switch. Switching –circuit as discussed below:

1). The Passive –Load NMOS Inverter: The simple NMOS inverter consists of an inverting FET and a pull-up resistor, as shown in figure. 1.vin <VT the transistor is in ‘off’, vout is pulled up to +ve supply voltage. In this case o/p is complement of i/p. 2.Vin>VT the transistor is ‘on’ and current flows from the vDD supply through resistor ‘r’ to gnd. If R were sufficiently large, vout could be ‘pulled down’ well below VT , thus complementing the i/p.

Depletion mode is used as pull-up is formed by connecting gate of upper transistor to

source.

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The major problem with this inverter is the physically large pull-up resistor

required. For a typical process, the on resistance of the FET (The resistance from the

source to drain of the FET when gate voltage is high) might be in the order of 10 KΩ and

sheet resistance (resistance of a square area) of the diffusion layer might be about 20 Ω/sq.

The load or pull-up resistance must be larger than the on resistance or pull-down

resistance of the FET in order for the O/P to go low when the pull-down transistor is

conducting. If the pull-up resistor is to be at less than ten times larger than on resistance of

the pull-down FET, then the value of the load resistance must be 100 KΩ, which requires

a diffused pull-up resistor of 5000 squres length. This is unacceptably large.

The width of the pull-down transistor can be increased to give an aspect ratio (L/W of

the gate) of L/W=0.1 for the gate of the pull-down. This device requires a pull-up resistor

500 squares in size, but overall gate area is still unacceptably large.

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2). The Active –Load NMOS inverter:

a). PMOS Inverter: A much smaller inverter can be designed with a FET used as

active load. The load can be enhancement-mode device or depletion- mode device.

An enhancement-mode FET has no channel with zero gate-to-source voltage, and

must have either a separate gate bias voltage or have its gate connected to its drain

in order to be used as an active load.

Depletion-mode device has a conducting channel with zero gate bias, and will

not turn off until sufficient reverse bias is applied to its gate. To be used as a load

device, the gate is connected to the source. The earliest MOS inverters consisted of

p-channel FETs (PMOS devices) with aluminum metal gates and used an

enhancement-mode pull-up configuration with negative logic, as shown in figure.

Once feasible NMOS devices became available, they quickly replaced PMOS

devices. Depletion-mode pull-ups have replaced enhancement-mode pull-ups due

to their superior switching speed, as well as fact that the threshold voltage drop

from gate to source required for enhancement-mode devices can only pull the O/P

up to within a threshold voltage of positive rail. Enhancement-mode devices can

be made to pull up to the positive rail, but this requires a separate gate bias which

is greater than VDD by at least one threshold voltage.

The major disadvantage of an NMOS load device is the fact that it never turns off

and the inverter dissipates power whenever the pull-down device is on, just as

passive resistance inverter does. This is one of the major concerns for popularity of

CMOS design when power dissipation is a major concern.

b). NMOS inverter:

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The first type of active load investigated was enhancement-mode pull-up in

figure, with the gate tied to the positive rail to keep the device on until the O/P

voltage reaches threshold voltage below positive supply, at which point the pull-up

switches off.

NMOS inverters today usually depletion-mode loads devices as shown in above figure due to their better speed and pull-up characteristics. This will taken as the standard NMOS inverter, and NAND and NOR gates will be designed based upon this inverter. The depletion-mode inverter requires a separate ion-implant step to change the threshold voltage of the pull-up FET from enhancement to depletion type. This implant step is shown by a box around the pull-up device in the Stick drawing and by dotted lines to outline the implant area on the layout drawing.

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The output from between the source of pull-up and drain of pull-down. The pull-up depletion transistor and it is usually to achieve proper inverter logic threshold. The relative locations of the saturation regions of pull-up and pull-down differ in their characteristics, due to difference in the threshold voltage of transistor.

1. While the input voltage is below the VT of pull-down transistor, no current flows in that transistor, o/p voltage is constant VDD drain to source voltage across pull-up transistor is equal to zero.

2. Vin increased above enhancement mode Threshold, current begins to flow in the pull-down transistor. The output voltage decreases slowly as i/p voltage is first increased above VT subsequent increase in i/p voltage, until the point reached where pull-down leaves its saturation region.

VINV-> The i/p voltage at which Vin= Vout is known as logic threshold voltage. The resistive impedance of MOS transistor is proportional to length –to-width ratio of its gate region. ZPu =(Lpu /Wpu )is increase relative to Zpd=(Lpd / Wpd ) then Vinv decreases.

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Down –going transistor approximately ‘f’ times the transit time of pull-down transistor.

Up-going transistor approximately ‘k’ times fan-out time’s factor of pull-down transistor.

To reduce R, W width should increase maximum. This is required diffusion process will increase. So the value of W is minimum and fixed, so we can make W increase gradually in number of stages i.e cascading of inverters.

Transfer characteristics of n-MOS inverter:

To obtain inverter transfer characteristics we superimpose Vgs=0 depletion mode characteristic curve on the family of curves for the enhancement mode device.

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Q).Give the outline schematic for manufacture of VLSI ICs and explain it? Answer:

Preparation silicon Wafer: Silicon material , diffusion,

oxidation: Silicon semiconductor devices are fabricated on thin, single-crystal substrates

called “Wafers”. These wafers are sliced from a cylindrical ingot of silicon and lapped and polished before processing. Depending upon crystal size, wafers vary in diameter from less than one inch to several inches. Electrical characteristics of the wafer substrate are determined by the doping type and concentration, which are contributed during crystal growing process. Electrical junctions are formed in the substrate by introducing the opposite

type of dopant to a concentration that exceeds the bilk doping by means of solid state diffusion. Junctions can be obtained in selected regions by masking those areas of the silicon surface that are not be doped with a suitable thick layer of silicon dioxide. The oxide layer is grown by exposing the wafer to an oxidizing ambient of oxygen or water vapor, or both, at an elevated temperature in the range 9000C to 12000C. This is done in opened-ended cylindrical quartz tubes that are resistance-heated in special “diffusion furnaces”. This furnace provides precise control of temperature over a considerable length of the tube called “flat

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zone”. Oxidation conditions are maintained so that an excess of oxidizing reactants exist in the tube atmosphere. This is done by introducing the reactants at one end of the furnace tube and allowing free exhaustion at the other end. Under this condition, temperature remains the controlling factor in oxidation, making it possible to grow a uniform oxide layer on many wafers within the furnace zone. Once oxide is suitably patterned by diffusion. Diffusion of dopants is usually accomplished by a two-step process. The first,

called “predeposition” is used to introduce dopant impurities to only a shallow depth in the silicon. The furnace atmosphere is now comprised of a gaseous compound of the dopant atom, which coats the wafer surface. The compound in turn reacts with the silicon to form a dopant-rich surface layer, which serves as a source of dopant for further diffusion in the second step. This step is called “drive-in diffusion”, diffuses the dopant impurities into the silicon to the desired concentration profile. Diffusion is generally done in an inert gas atmosphere, but an oxidation step usually follows to form a productive layer over the diffused regions.

Mask and etching: 1)In order to use silicon dioxide as a selective

diffusion barrier, it is necessary to define the oxide coverage on the silicon material. This is accomplished by so-called photolithographic or masking process. The process patterns the oxide in a sequence that employs three key materials, a photographic “mask” a photosensitive material called “ photoresist” and a silicon dioxide etching acid. The pattern on the mask is

imaged on the photoresist film which, in turn, protects specific areas of the oxidized water from attack, when it is exposed to an oxide enchant. 2) Masks are photographically produced plates that have opaque device size

patterns repeated on them. In this two steps are used. In first step the reduction image is repated for second reduction, to produce repeating the pattern in matrix fashion is called “ step and repeat”. The positioning of repeated patterns must be done to exacting tolerances, since alignment of successive device levels depends on exact pattern positioning across the entire mask. The second step reduction pattern is then contact-printed to form the final masks or “ working plates”. The working plates can be comprised of any of several materials, the most common being emulsion on glass. More durable opaque thin films, such as chrome metal, are also extensively used. The masks can be produced to have opaque patterns on a clear background or vice versa, depending on the material to be removed in subsequent etching and the type of photoresist used. 3). Photo resist, the second material, is an enchant resistant polymer is photosensitive when applied in this layers. The resist of “negative” type, it will be soluble certain liquid developers unless polymerized by exposure to intense light. Bu means of contact printing with the appropriate mask, the polymerization will notb occur under the opaque mask areas. The photoresist and suitable mask can

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thus be used to obtain a device-pattern, etch-resistant film which is used, in turn, for selective etching of the silicon dioxide film. 4). The material used to etch the oxide is a solution of Hydrofluoric acid (HF). Usually, it is used in a buffered form containing ammonium fluoride to ensure more constant etching characteristics. When the photoresist patterned wafer is exposed to this solution, the oxide will be attacked in areas not covered by resist. For diffusion masking, the oxide is entirely removed from the regions by an enchant. Oxide enchant may be required for extra diffusions, contact openings, or thinning oxide regions. These remasking steps must be performed so that subsequent layers are accurately located with respect to preceding ones. This registration is ensured by a technique called “mask alignment” with mask aligner.

5). Masking techniques are also employed when diffusion regions are to be connected to form circuits. The interconnection medium used is a metal film or combination of films. After etching contact openings through the oxide down to the diffused regions, the wafer is coated with a thin metal film, usually by evaporation. The metal to be deposited is heated in a vacuum system until vaporizes, uniformly coating the wafer surface. Aluminum is the metal used most often. The metal film is then defined into the desired pattern by the same photoresist methods as by selecting a suitable metal enchant.

Assembly: 1)The separation of individual circuits from the wafer substrate

is the most commonly done by a procedure called “scribing and breaking”. This is accomplished by taking advantage of the natural tendency of the silicon wafer to cleave along certain crystal planes. During the ingot sawing operation, the wafer was asymmetry, or flat, to index the orientation into account. When the completed wafer is oriented and scored with a diamond scribe, including localized crystallographic stress, it is broken along the lines into the separate fragments called “dice”.

2).The next step is dice encapsulation. Besides being a productive enclosure for the device, a package must also provide a means for connecting the contact points on the die to the external leads. The dice are mounted on package substrate, usually means of thermal solder type attachment. This “die attach” step, in addition to mechanically securing the die in this package, provides an electrically conductive connection to the silicon substrate. This also allows the heat generated in the circuit to be dissipated by conduction into the package.

3). Connection to the contact points or “pads” on the die is then accomplished by wire bonding. In this “lead binding” operation, one end of a fine metal wire typically 1 mil in diameter is attached to the die pads and the other end is

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attached to the package bonding “lands”. The package is tube heated in such a manner that the lands in turn are connected to the external package leads. Lead bonding is separated for each pad to be connected. Other method are automated methods by which all contact points are made simultaneously developed , but these require speed of wafer preparation or highly specialized packages

4). The last assembly operation is to finalize the encapsulation by isolating the sensitive circuit from its environment. By attaching over the package substrate while it is in an inert gas ambient, the die is hermetically sealed. Direct encapsulation of the die in plastic materials is also possible for certain circuits require special wafer preparation.

Metallization: It is process by which the components of ICs are connected

together by ‘Al’ conductors. The fabrication process forms on the wafer that creates wires and transistors. Wafer contains many circuits fabricated as Batch process. This process is efficient because we can produce many identical chips by processing a single Wafer. By changing the masks that determine what patterns are laid on the chip, to make particular circuit on the chip. To build it on an IC fabrication line, we must go one step further and design the Layout, or patterns on the masks. The rectangular shapes in the layout (stick’s diagrams and layout diagrams) for transistors and wire which confirms the circuit in the schematic. Creating layouts is very time-consuming and very important- the size of the layout determines the cost of manufacture the circuit, and shapes of the elements in layout determine the speed of the circuit as well.

Photolithography: The purpose of this is to open windows whenever

diffusion is to be done and retaining Sio2 remaining areas. During manufacturing, this step (photographic printing) process is used to transfer the layout patterns from the masks to the Wafer. The pattern left by the mask are used to selectively change the wafer: Impurities are added at selected locations in the wafer, done by diffusion and insulating materials by Oxidation (Sio2), the conducting materials are added at the top of the wafer as well ( Metallization).

Oxidation: It is a process where by oxygen molecules from a gas above the

substrate or surface material cause the growth of the oxide on the surface. Since substrate or surface is silicon material, the oxidation process produces Sio2. The aped at which silicon dioxide layer grows is a function of doping concentration and temperature of substrate during oxidation. It serves as a very high good insulator between substrate or surface material. These fabrication steps require very high temperature (>11000C), small amounts of toxic chemicals, and extremely clean environment.

Diffusion: It is process for fabricating technology dependent transistor. In

this impurity atoms moves from high concentration region to low concentration

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region to get desire width of source and drain of MOS transistor. From mask information the gate terminal laid on silicon substrate by using polysilicon material.

Separation of ICs: This is done by Dicing Saw method. In this method

the individual chip is separated from Wafer. Because the no manufacturing process is perfect, some chips on the wafer may not work. Since at least one defect is almost sure to occur on each Wafer, Wafers are cut into smaller, working chips, the largest chip that can be reasonably manufactured today is over 1,5 cm on a side, while Wafer is in the 20-25cm. Each chip is individually tested; the ones that pass the test are saved after the wafer is diced into chips. The working chips are placed in the packages familiar to digital designers. In some packages, tiny wire of Gold wires connect the chip to the package’s pins while the package body protect the chip from handling and the elements, in others, solder bumps directly connect the chip to the package.

Package and Tests: To give strength to IC and protection from

environment packages are required. Testing is a process of verification to make process parameters within the tolerances acceptable for the product. Pads: The dimensions for metal bonding pads have not scaled with decrease in feature size of the process. The size of capillaries used for attaching bonding wires, which are several mils in diameter for bonding actual circuit on “silicon” wafer to IC pin pads.

IC technology manufacturing is a powerful technology for two reasons: All circuits can be made out of a few types of transistors and wires, and any combination of wires and transistors can be built on a single fabrication line just by changing the masks that determine the pattern of the components on the chip, ICs run very fast because the circuits are very small

Silicon wafer preparation: 1). Oxidizing.

2). Removing organic residues.

3). Backside crystalline damage.

Characteristics of Substrate:

1). Surface crystalline orientation: It has a major impact on the electrical device characteristics (reflected in

carrier mobility & Qox terms) & also strongly influences process development.

The introduction of impurities into crystal by ion implantation relies on

collision with atoms at lattice sites to slow the impaging ion. The surface

orientation also strongly affects the thermal oxide growth.

2). Wafer diameter, Wafer thickness & surface flatness: The mechanical & chemical polishing of active device surface after wafer sawing will enhance the wafer flatness, nevertheless, the tolerance on this specification

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will affect the ability to keep 1:1 mask image in focus when exposing a photo resist coated wafer, which makes a tight flatness specification more difficult to

achieve. The defocusing of the image of a large field at wafer surface is aggravated by the presence of a dielectric film holding the surface in tension or

compression, as a result, the wafer will warp. The wafer thickness must be increased at large diameters to reduce this effect.

Silicon occurs in naturally in the form of sand. Chemically it is known as Sio2. Silicon accounts about 26% of earth crust. The stages of process of wafer preparation are: 1). Chemical reduction:By chemical process, sand is treated, to produce impure silicon. This is to be further purified to a better degree, typically of the order of 1 part in 106 i.e. impurity atom for 10 10 silicon atoms. This is achieved by Zone refining. 2).Zone refining: The impure silicon, obtained from reduction process, in the form of rod, is heated to produce a small molten zone. Impurities in the zone tend to float to the zone boundaries. If the molten region is slowly moved from one end of the rod to the other the impurities collect at the ends (due to temperature along the length of the rod) and so impurities can be removed. In thermal process temperature is about 12000C. This process is repeated several times to get the required degree of purity. The degree of purity will be tested by knowing the conductivity’ σ’of silicon rod. For device applications, the silicon must flaw-free as possible. i.e it must have a regular structure. Such a single crystal structure is obtained by crystalline pulling is known as “CZOCHRALSKI” process.

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3). Crystall pulling “CZOCHRALSKI” process:

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Previously produced single crystal silicon is used as seed crystal. This is touched as the surface of the melt then slowly rotated & with drawn. Now if controlled amount of impurities are added to the melt, p-type or n-type silicon can be obtained. Speed of with draw: 50mm/hr. The ignot obtained is sliced into wafers of 0.3mm to 0.5 mm thick, using a diamond impregnated cutting edge. The wafers are ground & lapped. One face of each wafer is polished to a mirror finish & inspected under microscopic because, the surface must be smooth & on this side Sio2 is grown so that the thickness is uniform. Wafer diameter: 75mm or 100 mm. Wafer thickness: 0.1 to 0.25mm.

OXIDATION The growth of thermal oxide from silicon substrate is the fundamental process

step of MOS device fabrication, a reproducible, low resulting defect density, contamination-free process technology for gate dielectric for the device &

surface to – interconnection dielectric layer. This is an essential step in the planar-diffused process of silicon technology. Oxide layers are used as elements in active & passive devices on silicon functional process. Function of oxide layers: 1).It protect silicon surface from undesirable atoms. 2). As a dielectric. 3). For dielectric Isolation (for ICs). 4). Impurity masking during diffusion. Oxidation Kinetics: The chemical reaction associated with oxide growth involve either an oxygen(dry) or water vapor(wet) ambient.

Si + O2 - Sio2--(1) and Si + 2H2o Sio2 + 2 H2. The evaluation of Hydrogen from 2nd reaction through the oxide layer out of the ambient will result in some reactivity with oxygen atoms is gone, resulting in a more porous film. The dry oxidation process uses high-purity oxygen(O2 – N2 mixture). The wet oxidation introduces water vapor into the furnace tube. The ratio of silicon consumed from the substrate to the resulting oxide film thickness is 0.45. The thermal oxidation of silicon results from diffusion of oxidizing species through

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the existing oxide layer to react at the substrate surface, in a steady-state condition, the following flux densities must be equal. 1). The transport of the reactant from bulk gaseous ambient to oxide surface.

2). The diffusion of the species through existing oxide layer. 3). The reaction-rate at the oxide-silicon surface. Types Of Oxides: 1). Thermal Oxides: Such oxides are formed by thermally activated reaction of silicon with oxygen or wafer. 2). Anoidic oxides: these are formed by anodization. In a liquid medium, electrodes are placed & charged ions move. Negative ions towards positive electrode & positive ions towards negative electrode. Then oxide layers will be formed on the silicon wafer. This is similar to ‘electrolysis’ process. 3). Deposited oxides: Oxide layer is deposited on the silicon wafer by vacuum deposition process. Silicon wafer placed in a vacuum chamber is deposited with oxide layer. It costly process. Thermal oxidation method is commonly used. Again there are divided into 3 types. 1). Wet Oxidation:

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Dry oxygen is passed along with steam (from boiled & distilled deionized water) over wafers. Diffusion coefficient lies between the dry and steam methods. Dry oxides are more sensitive to cleaning treatment. Steam oxides difficult to combolt. So wet oxidation method gives best results.

Different colors can be get after oxidation : Bluish Green, Yellowish,

Violet etc.

2). Dry oxidation: dry oxygen is passed over wafer in a furnace.

Si+ O2 Sio2. Growth rate of oxidation is evaluated by a term known as

diffusion coefficient ‘D’. D(O2) at 10500C = 2.82X10

-14 cm

2/sec.

Thickness of oxide layer is 5-10 µm simple applications.

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3). Steam oxidation: Oxide layer is deposited on the silicon-wafer by

steam is passed over silicon wafer. Diffusion coefficient ‘D’ is D(H2 O) at

10500C = 9.5X10

-10cm

2/sec.

Si + 2H2o Sio2 + 2 H2. Growth rate of steam oxidation process is high.

Q).Explain the properties of the thin oxide (Sio2)? Answer: OXIDE PROPERTIES: 1). The index of refraction of dry oxides

decreases with increasing temperature, the apparent density of oxides grown at 8000C is 3% more than those grown above 11900C. The etch rate of thermal oxides at 1000A0/min but varies with temperature and etch solution. The etch rate also varies with oxide density and thus with oxidation temperature. Measurement shows that high-pressure oxides grown at 7250C and 20 atm exhibit a higher index of refraction, higher density. For thin oxides, the role of the interface in determining oxide properties is important. 2). Masking properties: A silicon dioxide layer can provide a selective mask against the diffusion of dopant atoms at elevated temperature, a very useful property in IC processing. A predeposition of dopant by ion implantation, chemical diffusion are important at or near the surface of the oxide. During high-temperature drive-in step, diffusion in the oxide must be slow enough with respect to diffusion in the silicon that dopants do not diffuse through the oxide in the masked region and reach silicon surface. The values of diffusion constants for various dopants in Sio2 depend on the concentration, properties and structure of Sio2. A commonly used n-type impurities P, Sb and As, as well as the most frequently used p-type impurity B, all have very small diffusion coefficients in oxides and are compatible with oxide masking. ______________________________________________ Dopants Diffusion Constants at 11000C (cm2/Sec) ______________________________________________ B 3.4 X 10-17 to 2.0 X 10-14 Ga 5.3 X 10-11

P 2.9 X 10-16 to 2.0 X 10-13

As 1.2 X 10-16 to 3,5 X 10-15

Sb 9.9 X 10-17

_____________________________________________ Oxide grown in dry oxygen have best electrical properties but sometimes wet oxidation is preferred. Like when thin oxides are required in MOSFETs for fabricating gate oxides then dry oxidation is preferred for fabricating thicker oxide regions like field oxide, wet oxidation is used.

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Thin Oxides: In sub-micron range MOS VLSI very thin oxide (50 to 200

A0)) are grown on crystalline silicon. These oxides show good electrical characteristics and provide long term reliability. Oxides also serve as dielectrical material for MOS devices. The growth of thin oxides must be slow to obtain uniformity and reproducibility. A number of growth techniques are there like dry oxidation, wet oxidation, reduced pressure techniques and high pressure/low temperature OXIDATION. Ultra thin oxides and thickness less than 50 A0 can be grown by using nitric acids, boiling water and air at room temperature. Rapid thermal oxidation performed in controlled oxygen ambient with heating provided by tungsten-halogen lamps is also used to grow thin oxides.

Properties of Thin Oxides: 1). At reduced temperature oxide density

increases. 2). Index of refraction of dry oxides decreases with increasing temperature. 3). Density of oxides grown at low temperatures is more than that grown at higher temperature. 4). Etch rates of Thermal oxides varies with oxide density and with oxidation temperature. 5). Higher pressure oxides exhibit higher index of refraction, higher density and slower etch rates in buffered HF than steam oxide. 6). Silicon dioxide layer provides a selective mask against the diffusion of dopant at elevated temperature.

Q).With neat sketches explain the electron lithography process?

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PHOTOLITHOGRAPHY The purpose of this is tom open ‘windows’ whenever diffusion is to be done &

reaction Sio2 remaining areas. In the fabrication process this step is done after oxidation. Photolithography is also done before metallisation, whenever metal contacts are to build up. This process is carried out in a clean room where UV light is not present. Yellow color light of a particular wavelength are employed so that, light in UV range is not present, since UV light effect the photo resists. The operation is carried out in a clean bench, where, dust free; pre clean air is blown continuously.

The different steps in photolithography are: 1). Wafer cleaning. 2). Mask preparation. 3). Photo resist coating. 4). Exposure to UV light. 5). Developing. 6). Etching. 7). Removal of photo resist & cleaning. NEGATIVE PHOTORESIST: (a mixture of resin & photosensitizer) Cross-

links upon absorption of UV radiation, the resulting high-molecular weight polymer chains are insoluble in negative photo resist developer solvent solution. Transparent areas of mask correspond to areas on wafer where the protective

photo resist coat of negative photo resist remains. Disadvantages: 1). The necessary cross-linking of long polymer chains to inhibit dissolution by developer limits the fundamental resolution of negative resists. 2). The negative photo resist developer is largely composed of a solvent to remove the low-molecular weight, non cross-linked polymer resin, this solvent is absorbed to some degree by exposed negative resist, which swells the remaining resist film. Positive resist developer is a solution, which doesn’t result in image swelling. 3). In stop-repeat aligners, a high-intensity, short duration exposure is necessary to maintain high effective throughput. The reciprocity of a photosensitive medium is extent to which intensity X time product necessary for exposure (given thickness) remains constant over range of intensity indeed reciprocal, while negative resist are not ohms, the determination of proper exposure time (using light integrator) is difficult for negative resists. 4). Negative resists are also more sensitive to low levels of exposure energy than positive resists, in othetrwords, the negative resist have less contrast. The reflectivity & scattering of incident light from the wafer film below (an aluminum metalliztion layer) tends to cross-link resist in areas outside the original image.

Source of photo resist are: 1) KODAK (Kodak photo resist).

2). KMER: Kodak metal etch resistor. 3). KTFR: Kodak thin film resistor. 4). VISTAK: Indian telephony industries. 5). AGFA: Positive, negative.

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6). Dynmo-chem.

Photoresist coating types: 1). Dip coating. 2). Spry coating. 3). Spin coating – practically it is used & it gives uniform coating. 4). Flow Coating.

Photolithography Steps: 1) Apply resist Adhesion promoter to wafer: For most surface film

that is to be coated with resist (SiO2, Si3N4, Polysilicon)& Adhesion promoter is initially applied. Adhesion promoter (hex methyl disilazane (HMDS)) is applied to wafer surface by spin-coating technique using high rpm, high-acceleration-rate wafer chuck, the wafer is held by vacuum.

2) Application of resist: Again using a spin-coat wafer chuck system, a

precise amount of resist is dispensed onto wafer surface, allowed to dwell momentarily & then spun at high rpm to throw excess resist off the wafer into a collecting bowling-shape shroud. The chuck spin speed, spin time & acceleration rate selected to produce a particular resist film thickness & uniformity. The resist is filtered during application to remove particular contamination.

3) Resist exposure: After alignment, the photo resist coat is exposed to UV

through the transparent and opaque mask areas. The selection of proper exposure time and focus is typically made from inspection of the resulting patterned image, on a step-and-repeat reduction aligner, a focus-and-exposure matrix is commonly produced initially on a non-product wafer and the optimum developed image is selected after inspection to determine exposure characteristics often measure of a reference photo resist line width in the mask kerfs made to assist in selecting optimum conditions.

4) Resist develop: The exposed resist film is then subjected to a developer

solution to produce the latent resist pattern. The dissolution ratio between exposed and unexposed areas in commonly large (positive photo resist), but the developed time and temperature must nevertheless be controlled quiet accurately. The quenching of the developer action by a subsequent rinse follows immediately. Batch impression developer bath with agitation. The rinse follows immediately after develop time expires while the wafer continues to spin.

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5) Resist post bake (After SiO2 etching): The final resist treatment

step (prior to etching of exposed film) is post bake at elevated temperature (30mm bake at 1200 C in oven). This step increases the etch resistance of the coating, enhances the resist adhesion to the underlying layer, and drives off remaining solvents.

Careful consideration must be given to the temperature and time of post baking so that the plastic flow of resist film doesn’t severely alters the developing image, in some cases, a slight reflow of the resist may be used for the side wall profile to control in the resulting etched film, if the resist and film are removed at comfortable etch rates. This sequence of steps describes the conventional photo resist processing techniques. Alternative steps are taken to produce resist sidewall profiles with a slope suitable for metallization lift-off procedures.

6) Removal of photo resist: The complete removal of photo resist coat

after etching is a key process step to eliminate contamination in subsequent processing. Resist removal is complicated by exposure to a high temperature ion implantation or plasma etch procedure.

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Q).Explain the photolithography process? What are recent developments in lithography

Advanced photolithography:

Electron beam exposure

X-ray lithography full wafer

Photo

Resolution(R)µm 0.1 0.25 1.0

Through o/p (N) Wafers/Hr

10 75 40

System cost (C) K$

3000 225 700

Clean room area (A) Sq.Ft.

65 12 50

Figure of merit N(103) /

(C+10A)+R2

274 3480 33

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1).Electron beam Lithography: The resolution in electron

Lithography is much higher –than photolithography due to small wavelength (less than 1 angstrom) of the 10-15 KeV electrons. In such case the resolution is not limited by diffraction, but by electron scattering in target materials including the resist by various operations of electron. This method is widely used for pattern generating functions. Some of these applications are mask-fabrication for photo or X-ray lithography, direct reaction with some materials on the wafer and direct writing on the wafer. It is classified into two types: 1). Scanning. 2). Projection type. The scanning type is divided into two categories i.e. Restore and vector scanning. Figure shows the exposure sceme. In this CAD system, the VLSI pattern is made. The O/P format from CAD systems is converted into the internal format of individual exposure systems. The data is decomposed into simple elements (trapezoids or rectangles depending on machines) by electron exposure machines. Since, the electron beam exposure machines handles data function also, it is bigger than the optical printers. Some special products such as microwave transistors. The direct writing has been applied in some low-volume production devices. These direct writing M/Cs are also applied in development stages of VLSI and in personalization pf ASICs to minimize the mask related cost, and development time.

2). X-ray Lithography: In this the diffraction effects and resolutions

are improved by reducing the wave length. If wave length is reduced further than deep UV, all optical materials turns to opaque due to fundamental absorption. But transmission increases again in the X-ray region. The development of this type in 1972. In this Lithography, X-ray source illuminates a mask which casts shadow on a resist coated wafer. The main components of this type process are 1). A mask comprised of a device pattern made of X-ray absorbing materials, 2). An X-ray resist and 3). X-ray source. Figure shows the several materials for X-ray absorption. The absorption co-efficient of an element material of density ρ and atomic number Z is proportional to ρZ4 λ3 over wide range of wave lengths. In this type, the resolution and placement accuracy obtained so far is 0.2 µm and 0.3µm respectively.

Epitaxy Epitaxy is Greek word. Epi means ‘ON’ taxi means ‘Growth’. Growth of Si atoms or crystals on the surface of Si itself is called epitaxial growth. Epitaxial Si layer grown onto the starting crystalline substrate material. Bipolar device IC technologies have long been developed dependent on the epitaxial layer during device fabrication. In CMOS that

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an epitaxial layer be present on the substrate prior to beginning of fabrication. The impurity concentration in the epi layer is relatively independent of the background concentration of the wafer substrate. The epi layer can therefore be a high resistive layer with a low resistivity, bulk region below. The high resistivity epi layer is attractive for reducing junction capacitance and threshold voltage body effect coefficients. The low-resistivity substrate is selected to reduce the localized substrate resistance and substantially reduce the gain of one of the parasitic bipolar transistor type.

Experimental Setup:

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The deposition of an epitaxial layer can be performed in a cold-wall system with wafers lying horizontally on an inductively heated susceptor. In this Si atoms deposited on the wafer surface be sufficiently mobile so as to allow for incorporation into a crystalline lattice site.

Epitaxial Si can be grown using any of the following reactions

Silicon tetrachloride is used as the source and it is reduced to silicon at high temperature.

SiCl4 + 2H2 Si + 4HCl 1150 - 12500C, 0.4 - 1.5µm/min.

SiHCl3 + H2 Si + 3HCl 1100 - 12000C, 0.4 - 2 µm/min.

SiH2Cl2 Si + 2HCl 1050 - 11500C, 0.4 - 3µm/min.

SiH4 Si + 2H2 0950 - 10500C, 0.2 - 0.3µm/min. To get n-type silicon epitaxial wafer. Phosphine gas is used as impurity source. (For p-type bi borne is used).

Epitaxy is carried to achieve: 1). Near perfect crystalline structure for the active regions of the device. The substrate acts as a path for carriers if the crystalline structure is not perfect, device characteristics will be effected (leakage etc.).The presence of flaws (crystal defects) leads to reduction of lifetime of the carriers. 2). Series resistance associated with the device can be reduced. Epitaxial process a single crystal silicon (silicon atom layer) from the gas phase is deposited on existing crystal wafer (silicon wafer). The epitaxial layer may be p-type or n type. By epitaxial growth, the series resistance associated with the substrate can be reduced without changing the characters of the semiconductor device. Advantages of Sicl4: 1). It is easy to purify. 2). It is non toxic & inexpensive. 3). The reaction making silicon from Sicl4 takes place at surface and not on the boat

or reaction changes walls. Disadvantages : 1). The growth process is accompanied by different phenomenon. 2). Sicl4 requires higher temperature. By epitaxy, crystal is grown slowly, so near perfect crystalline structure will be obtained & the conductivity of grown layer can be controlled effectively. In czpchralski pulling method, crystal defects will be there & controlling conductivity difficult. Because of crystal defects, electrical properties will be affected.

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Q).With help of a neat schematic describe the ION Implantation process? Why it is prefer for VLSI fabrication? What are advantages and disadvantages? Q). Compare thermal diffusion process with ION Implantation process?

ION IMPLANTATION Ion implantation is a technique for introducing a precise quantity of impurities into the substrate by accelerating a beam of ionized impurity atoms in vacuum to impinge on the wafer surface. The impurities may be added to material in selective areas, where locally from reaching the substrate by photoresist coat or thermal oxide layer of sufficient thickness. In diffusion process the diffused portion of the IC through windows is not diffused exactly perpendicular to the surface of the substrate, instead it diffused laterally under Sio2 layer (Horizontally) also shown in figure. But the length and width of these diffused areas accounts the characteristics of ICS. To avoid this we can use another technique to overcome this difficulty called ion implantation whose block diagram is shown below.

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The ion source must be able to provide a relatively high current level of desired ion species( in 10µA to 1mA range) in order to reduce process time. The ionization coefficient describes the number of ionizing collisions produced by an electron passing through gas(per unit length per unit pressure). The resulting ions that penetrate the screen opposite the cathode are accelerated by electric field between the screen and extraction electrode. The beam column is evacuated to reduce ion gas molecules collisions, which could result in unwanted deflection or charge neutralization of the ion. The e/m ratio of the material is specific to the material. So when the ions traveling with e/m we can adjust electrically to travel only specific ions towards the target & they impurities can be eliminated. The magnetic field analyzer bents ion beam towards the target. The scanned plates the ion beam can be deflected. The characteristics of the devices are superior.

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The beam current provides the number of ions per second incident upon the wafer. A major advantage of ion implantation is the accuracy to which this dosage can be controlled over range of 1010 to 1017 ions/cm2. Specifications: Target temperature: 196 to 3000C Pressure in beam chamber: 10-5 to 10-2 PASCAL’s. Depth of ion implantation: 0.01µ to 5µ( Not possible with thermal diffusion). The ion beam current: 1 nA to 20mA. The ion beam CSA : 0.1 to 1 cm2

Disadvantages: Cost is High $500,000.

Q).Clearly explain the diffusion process in IC fabrication?

DIFFUSION Any fabrication process is the impurity profiles of all junction nodes, the targeted junction depth affects the design rules of device length & node-to-node spacing. While the surface concentration must be sufficient to provide ohmic contacts to metal to inter connect. The integral of the profile determines the electrical sheet resistivity; the shape of profile in the vicinity of junction depth determines the junction capacitance. Thermal diffusion is an important physical process in IC fabrication. In this process particles moves from region to high concentration to region of low concentration. Diffusion of impurity atoms on silicon crystal takes place at elevated temperature 900-11000C. 1). Substitutional Diffusion : Here the silicon atoms of the present crystal will be displaced by impurity atoms because of its high thermal energy. Impurity may be donor or Acceptor. n-type Impurities are : Phosphorous, Arsenic & Antimony. p-type Impurities are : Boron, Aluminum & Iridium. 2). Interstial Diffusion: Here the impurity atoms doesn’t replace the silicon atom, but occupies Vacant places or Voids in the lattice. Gold, Copper & Nickle are the impurities, which diffuse interstially into silicon atom. This type of diffusion depends on the nature of the Impurity atoms. It is low temperature process. Interstial diffusion is done to reduce carrier lifetime and increasing switching speed. For Digital ICs the method is employed.

Diffusion process is governed by Fick’s first law : F = D ∂N/∂x---(1)

Where N-- number of impurity particles per unit volume.

x-- Distance measured from the surface into which diffusion takes place.

D-- Diffusion coefficient m2 / sec.

F-- Particle flux density between two surfaces in semiconductor wafer.

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Statement: The particle diffusion rate(from high concentration to low concentration, is proportional to the concentration gradient ∂N/∂x of impurity atoms. Negative sign is there because particle from & concentration gradient are in opposite direction(particles move from higher to lower concentration, so the gradient sign is opposite. Fick’s second law: ∂N/∂t = D∂2N/∂x2 The rate of change of impurity concentration with respect to time is proportional to the second derivative of the concentration gradient with respect to co-

ordinates. Value of D depends upon doping impurity temperature, time. N -- Based upon this we can control F. The impurity distribution takes place in two ways: 1). Constant source diffusion. 2). Limited source diffusion. 1). Constant source diffusion: 1). Suppose in the diffusion process, the silicon wafer is exposed to a volume of gas containing number of impurity atoms(say n-type impurity) per unit volume. 2). Let the distribution of these impurity atom is uniform through out the gas. 3). The impurity atoms will get diffused into wafer, along the thickness of the wafer due to high thermal energy possessed by impurity atoms, Assume that impurity atom concentration at the surface of the wafer is N0 & it remains constant throughout the diffusion process, then the distribution of impurity atom, along the thickness of the wafer surface will be as shown:

N0--- Concentration of impurity atom on the surface.

t-- time, x--- distance along the thickness of the wafer. The curves are obtained by starting by solving differential equation ∂N/∂t = D∂2N/∂x2 with boundary conditions, that N0 is constant through from t=0 to ∞N(x)=0 at t=0 in the beginning (when diffusion is not started impurity concentration = 0). The solution of the differential equations is N(x,t)=N0[ 1-erfx/(2√Dt)]

where erf - error function. Or

N(x,t) = N0 erfc/(2√Dt) where erfc - complementary error function. Any error function Y erf Y = 2/√x ∫ e –x2 dx. erfc =1-erf y. So we get that type of curves. Because we are assuming that the concentration of impurity atoms ‘N0’ is constant, it is constant current source diffusion.

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2). Limited Source diffusion: Here diffusion takes place in two steps. 1). Predeposition : A fixed number of impurity atoms are deposited on silicon wafer during a short time. 2). Driven deposition: Now, the impurity source is removed and pre deposited impurity atoms will get diffused into the wafer. Here the boundary conditions are N(x) = 0 at t=0 for x>0 i.e. before diffusion, the impurity atoms will zero. Q = ∫ N(x) dx for all where Q is total number of impurity atoms per unit area. A fixed number of impurity atoms are deposited. N(x,t) = (Q /√∏D t) ∫ e –x2/4Dt. This is known as Gaussian distribution. The area under these curves will be the same since Q is fixed. Junction profiles will be different in both cases. Impurity in the form of ‘Diffusion source’.

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Impurities type Donor (N) Acceptor(P)

Solid P BN

Liquid Pocl3 Phosphorous oxide

Gas P2o5 phosphine

Parameters affecting Diffusion process: 1). Diffusion Temperature: High temperature gives more & thus higher relocities to the diffused impurities. Diffusion coefficient ‘D ‘ depends on temperature ‘T’.

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2). Diffused time: As the diffusion time is more, more number of carriers will get diffused to a great depth, so junction depth depends on the time. 3). Surface cleanliness: The silicon surface & the diffusion furnace must be absolutely clean. Otherwise impurities of doping will be last & also the characteristics of the junction will be affected. 4). Solid solubility: it is the maximum value of N0(impurity ion concentration on the surface) which can be deposited(or dissolved) on silicon wafer. Problem on Diffusion :

Metallization Generally Aluminum is used for metallization to interconnection it is done before encapsulation.

It has properties: 1). Deposition rate and grain size control. 2). Adhesion to

underlying dielectric films. 3). Temperature limitations is subsequent process steps after deposition interconnect. 4). Ductile nature of interconnect, susceptibility to micro cracking. 5). Diffusivity of metal into silicon. 6). Growth of metal oxide surface layer. 7). Susceptibility to corrosion & attack by water vapor. Properties:1). It is cheap. 2). High electrical Conductivity. 3). Thickness of Aluminum conductor 1500A0. 4). Sheet resistance is 0.187 ohm / Square. Process: It is process by which the components of IC are connected together by aluminum conductor. First the entire wafer is coated with aluminum. Then by using metallization masks, ‘aluminum’ is removed from the portions where contacts are not to be taken or conducting region is not required aluminum is deposited by vacuum deposition technique.

Vacuum deposition technique:

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Here the substrate is commonly deposited by metal evaporation of a solid source in a high vacuum chamber with subsequent condensation on substrate targets. The yield of target atoms released for each incident ion, the deposition rate onto the wafer substrate is proportional to the incident ion density & sputtering yield. The sputtering rate also increases with temperature. The sputtering yield of the target material using ions generated in a gas discharge is reduced due to increased gas-ejected target atoms collisions at the operating gas pressure (5 to 40(10-3)torr) with subsequent redeposit ion onto the target.

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Encapsulation : There are different methods by which encapsulation can be done, for digital ICs conducting tools are used to conduct the pins of the base to the terminal points of IC unit.

ISOLATION In monolithic IC all elements, transistors, diodes, resistors etc. are formed within a common conducting substrate. Often the substrate resistivity may not be high, so each element should isolate from the other. And the elements must be interconnected through metallization only & not through the conducting substrate, Hence isolation of elements one from the other is required.

Different Isolation techniques are : 1). Diode Isolation: 1). Circuit elements are formed with in an epilayer which

is grown on substrate of opposite type(n epilayer on p type substrate). Now isolation islands are formed by heavily doping the same type of impurities as the substrate. If the substrate is p-type P+ diffusion is done through the epilayer till it meets the substrate. 2). To achieve this type oxidation is done, all over epilayer. 3). Using photolithography, windows are opened. Now P+ diffusion is done to a depth equal to epilayer. 4). So ‘n’ type separate islands will be formed. So the ‘n’ type separate islands & ‘P+’ region will act as a diode. Each ‘n’ islands is isolated from the other. The transistors, diodes etc. are made on each ‘n’ island. They all interconnected by metallization as per the circuit. Thus elements are isolated one from the other within the substrate. The diodes are maintained at reverse bias by connecting the p-type substrate to most negative potential in the circuit via surface metallization. Advantage: Only diodes are to be fabricated so it is cheap.

Disadvatages: 1). Isolated diffusion (P+ diffusion for p-substrate) is deep as

thick as epilayer. So diffusion time is more.

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2). Lateral diffusion will also takes place while vertical diffusion is taking place. So widthwise, clearance must be given on the wafer. So this will result in inefficient chip area. 3). The capacitance of larger area isolation diodes will affect the circuit performance at high frequency.

2). Dielectic Isolation: In this case each island, in which an element is

deposited, is isolated from other by a dielectric (Sio2) layer. Thus Isolation is provided. This is carried out with the following steps: 1). The starting material is ‘n’ type silicon wafer not n or p epilayer. It can also be p-type silicon wafer.

2). Oxidation: Oxide layer is grown all over.

3). Photolithography: Using a mask, windows are be opened where ever

islands are to be created.

4).Silicon etching: When ever windows are opened etching of silicon is done

to a depth of 10-15µ using buffered HF(Hydrogen Floride) solution.

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5). Reoxidation: Now, reoxidation is done so that the etched portion of

silicon is also coated with oxide layer. 6). Then a silicon layer is grown all over to a height of 100-200µ.

7). Now wafer is inverted & bulk of the original ‘n’ type region is etched &lapped away until only n-type island remain in the polycrystalline substrate.

Advantages: 1). No frequency limitation & perfect isolation parasitic

capacitance as in the case of diode isolation is less because oxide thickness is more. 2). Permitivity of Sio2 is 1/3 of that of Silicon.

Disadvantages: 1). Number of process steps are more.

2). Lapping operation is difficult. 3). Silicon on Saphire (SOS) Isolation: Device fabrication use of crystalline sapphire Al2o3 layer on insulating substrate. Sapphire is perfect insulator. This choice can effectively result in elimination of the area of device node junction capacitance. So isolation can be provided. 1). The deposition of silicon epitaxial layer into a crystalline material whose lattice parameters similar to that of desired surface orientation (ex. 100 silicon on (1 1 0 2) sapphire (Al2o3). 2). The deposition of polycrystalline onto a non-crystalline (amorphous) substrate, with subsequent recrystallization on the deposited film. Silicon is etched from islands, so that isolation is achieved. Advantage: The process is simple, isolation is perfect, No frequency limitation or capacitance problem.

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Disadvantages: 1). Potential problem with this technology options are aluminum auto doping, thermal expansion coefficient mismatch & film defect density( i.e. a strong function of distance from the silicon-insulator interface). 2). Sapphire is costly, so it is used for high frequency ICs only.

Cross Overs: In the electronic circuit i.e. to be incorporated in IC, there will be interconnections or crossovers. For interconnections one element cross over, two conducting patterns should be separated from one another. An example, consider the Multivibrator circuit, two transistors are connected as shown:

So the metallization pattern conducting C1 to B2 & C2 to B1 shouldn’t touch each other. So there must be a crossover. How to realize this? The method to be adopted should be compatible with IC technology. One method that employed is buried crossover. It is shown in figure:

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Two elements A & B are to be connected by conducting pattern. There is another conducting pattern over crossing this. But it shouldn’t start the previous conducting patterns. This can be realized shown n+ region in the buried conducting pattern. The elements A & B (they can be n-type emitters of the transistor) are connected through n+ region. Heavy diffusion of n+ is done along with the emitter diffusion. So A & B are interconnected through n+ region. Sio2 separates the other conducting pattern of aluminum from n+ conducting pattern. The crossover is achieved. Another method is to have a diffused resistor in between the two conducting patterns to separate them, to get crossovers. A diffused resistor is lightly doped semiconductor material with high resistivity. It will act on the separate region to prevent the two conducting patterns getting shorted. Fabrication resistors: 1). Diffused resistor. 2). MOS resistor. Generally bipolar technology is most suitable for passive components ‘ R’& ‘C’. The MOS technology is suitable for only ‘C’. 1). Diffused resistor: Toerances : ±20%

ρs for base diffusion -- 100-200 Ω/Square.

ρs for emitter diffusion 1-10 Ω/Square.

ρs for collector diffusion - 1K Ω/Square. Parallel diffusion of two resistors ±5%. Structure:

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Integrated resistors can be made by diffused resistors. For a large value of resistance more area of the chip is selected. The p-type diffusion is most commonly used. Diffusion layers are very thin therefore to define we, a resistor, normally, a quantity called sheet resistance is defined.

At low frequency - reactance high signal pass from 1 to 2 R = ρL/A = (ρ/t)(L/W)= Rs (L/W) where RS is sheet resistance. Where L is length of diffusion & W is width of diffusion. Network equivalent: A parasitic or unwanted p-n-p transistor is formed with p substrate as collector, n isolation island as base and p type resistor as emitter. The emitter of this must be reverse biased to keep the transistor off. Normally to fulfill this condition all resistors are fabricated in one Isolation Island and it is mainted at most positive voltage. So that base of this parasitic pnp transistor of positive and it remains cut off. Diffused resistors are generally grown at one of the stages of manufacture of transistor in a single technological cycle. Resistors with low resistivity ρ are made during diffusion of an emitter region. Resistors with medium value of ρ at stage of diffusion of a base region. High value resistors ate grown in collector region.

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The resistivity of a collector layer is about 1Ώcm, base layer is 0.1Ώ cm and emitter has still lower ρ. Diffused resistors must have small possible dimensions. The figures shown have a shape of narrow strips. These strips terminate contact pads.

Number of squares Problem: Design a 5.025 KΏ resistor to be made with a silicide material having sheet resistivity of 75Ώ/ layout chip requires a resistance to be connected between pads of 100mils apart measured between inside edges. Minimum recommended width 2 mils. Width =2 mils length = 100mils & resistivity ρs = 75Ώ/ For given resistance value = 67X2 = 134 mils. Number of squares required = 5.025X103/ 75Ώ = 67 squares . Assume it is 70 squares.

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MOS resistor:

Structure:

Limited value of resistors is possible. In this the channel width & diffusion depths are fixed. Integrated Capacitance: The capacitors formed in integrated circuits are in pnp junctions displaying a barrier (transition) capacitance or diffusion capacitance, and also MOS structures. The capacitive elements based on reverse –biased pn junction enjoy more extensive use. The basic parameters of an Integrated capacitance C0, permissible voltage Vmax, temperature coefficient of capacitance (TCC), and parameters of parasitic elements namely, capacitance and resistance in series with useful capacitance. A reverse bias p-n junction has a depletion layer with acts as a dielectric between two conductive surfaces. The structure of Diffused capacitance is shown in figure Capacitance in parallel with diode and in series with bulk resistor.

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C is the wanted junction capacitance whose value is quite small of the order of 0.40pf/mil2. The transition capacitance of a capacitor formed by a pn junction depends on junction area and width of a barrier layer and therefore on the concentration (doping) level impurity gradient. Besides, the transition capacitance is a function of applied voltage. In most cases, capacitor doesn’t require additional operations for their manufacture since the same junctions as those formed in a transistor structure act as capacitors. This limits the range of values of the per-unit area capacitance because the impurity concentrations and diffusion gradient are dependent on the properties of the collector, base and emitter regions of transistor located with capacitors on common substrate. In other words, the design engineer has to deal with three per –unit area capacitance for three junctions, namely emitter base (EB), base-collector (BC) and collector-substrate (CS) junctions. Figure shows the emitter-base junction capacitors shows the highest per unit area capacitance, but have lowest breakdown voltage. A limitation of this type of capacitor is high resistance of the series combinations due to a thin base layer. Figure is equivalent circuit of an emitter-base junction capacitor. To overcome the effect of a parasitic pnp transistor, the lead 4 is connected to a maximum negative voltage and the lead 3 to maximum positive voltage. The capacitor has a parasitic capacitance on the substrate. The collector –base junction has a low per-unit area capacitance, but a high break down voltage. Figure2 illustrates the structure of a capacitor using this type

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of junction formed in a transistor. What presents a problem regarding this structure is isolation of the capacitor from the elements lying on the same substrate and having pn junctions.

pn junction’s capacitances have a number of disadvantages. As the reverse voltage increases, the capacitance decreases. The capacitors operate only at polarity of applied voltage. The integrated Capacitors have a small per-unit area capacitance not above 4000pf/mm2 or 0.4pf/mm2. They occupy larger than transistors. MOS capacitors: C = εA/d where d is thickness of oxide layer. Structure:

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Reliability tests of MOS circuits 1). What are significant failure nodes? 2). What are the significant circuit design techniques. 3). What are the significant Screening techniques. 1). Significant failure nodes: In certain circuit is failed then modify the circuit design in such way that failure not occurred. a). For digital circuits the fan-out and I available = I/O. decrease the value of I/O is called IC parametric IC drift. For digital ICs the “catastrophic failures” it is complete breakdown (logical 1 level may be due short circuit drift). b). Mechanical failure: 1). Bonding: In IC packing the bonding is one main cause for main failure. 2). Less number of pins & called open circuit failure. 3). Excessive flow of current at particular point of substrate cause J value increases the conductivity is increase at the substrate of that point the temperature may increase due to such high current. 4). Break down due to thermal shock: The IC is used for long time the rise in temperature causes the IC damage (the current may increase). 5). Mechanical shock: The bonding may be break due to sudden mechanical shock occurred. 6). Resonance frequency: Due to natural resonance frequency in IC circuit the bonding may break the IC may not work properly due to break in bonding. 2). Ultrasonic cleaning: Before oxidation & after oxidation the wafer is cleaned number of times TCE (Trichlorine ethylene). The cleaning is done after the bonding the contact is break. After metallization over the wafer for connection through aluminum contains “Na” ions is left they are high mobility the shorting of conducting lines may occur. 3). The thickness of aluminum deposition (Silicides): The conductivity lines of so much thickness are fixed. The conductivity lines thickness may occur the below

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or above the specified lines & not uniform. The design material like “Na” ions may cause short circuit. 4). Metal Short circuit Interface: The thermal properties of silicon & aluminum are differing; the cleaning of aluminum is not proper the conductivity increases that causes the breaking of some level a). Short circuit failures: Minimize the spacing between two adjoining conductivity lines. Due to the migration of the “Na” or foreign material cause short circuit. b). Over lap of metal interconnects: The source for One MOSFET & adjoining MOSFET. The cumulative line at one MOSFET to the other MOSFET cause short circuit between two MOSFETS. c). While in the fabrication of so many chemicals are used the improper cleaning may cause short circuit between two lines. d). Due to mishandling: Staic Charge. 2). Design aspects: 1). To overcome the above failures. The current density at any point may be less than 106 A/Cm2. So the increase in conductivity line width or bonding pad size. 2). Bonding pad size must be large. At large mechanical shocks it will withstand. 3). Reduce the number of bonding pads. 4). Minimum spacing between adjoining conductivity lines. 3). Protective circuits: Fabrication aspects: 1). Take care of conductivity particles. The Na ions are not left over after metalization. The aluminum traces are not left over after etching. 2). Faulty oxides. 3). Metal etching process: When two pads are near by after metal etching over the between two pads the cleaning between two pads which you not required any conductivity so it is removed properly. 4). Chemical contaminants: 4). Screening techniques: For IC short circuit or open circuit is easily detected. 1). MIL-STD 833: It is used for IC is to be passed for Thermal shocking, vibration. Mechanical screening tests: 1). 100,000 g force is applied. 2). Optical screening: Before encapsulation is done there are pinholes the oxidation is done properly (Thickness is not uniform) & etching is done properly.

3). Thermal screening: Where IC is subjected to different temperatures. The

operation is burn-in: 1). Thermal shock. 2). Thermal cycling. These are as per MIL standards.

4). X-ray screening techniques: IC is examined before encapsulation, so

that the bonding pad is connected properly or not.

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In lithography for micromachining, the photosensitive material used is typically a

photoresist (also called resist, other photosensitive polymers are also used). When resist is

exposed to a radiation source of a specific a wavelength, the chemical resistance of the

resist to developer solution changes. If the resist is placed in a developer solution after

selective exposure to a light source, it will etch away one of the two regions (exposed or

unexposed). If the exposed material is etched away by the developer and the unexposed

region is resilient, the material is considered to be a positive resist (shown in figure 2a). If

the exposed material is resilient to the developer and the unexposed region is etched away,

it is considered to be a negative resist (shown in figure 2b).

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Figure 2: a) Pattern definition in positive resist, b) Pattern definition in negative resist

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UNIT-2

Basic Electrical properties of MOS transistors

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(b)Enhancement mode device:

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NMOS inverter

vout

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NMOS inverter transfer characterstic

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UNIT-3

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GND

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CMOS design style:

CMOS representations are extension of NMOS approach.

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CMOS LAMDA BASED DESIGN RULES

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TRANSISTOR AND STICK DIAGRAM REPRESENTATION :

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CURRENT DENSITY J:

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UNIT-4

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UNIT-5

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4-bit ripple carry adder

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The excitation table for 3-bit binary counter is:

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State diagram of the counter is shown below:

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UNIT-6

PLA’s:

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Q(t+1)=JQ

1+K

1Q

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FPGA design

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UNIT-7

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CIRCUIT SYNTHESIS AND DESIGNFLOW:

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SIMULATION:

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UNIT-8

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12. Unit wise Question Bank (Subjective & Objective)

12.1 Unit-1

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UNIT-1

1. Describe the two commonly used methods for obtaining integrated capacitor.


process.

3. What is Moore’s law? Explain its relevance with respect to evolution of IC

Technology.

4. What is the size of silicon wafer used for manufacturing state-of-the art VLSI

ICs?

5. What is the minimum feature size of current commercial VLSI devices?

6. Explain the following:

(a) Thermal oxidation technique

(b) Kinetics of thermal oxidation.

7. With neat sketches explain how NPN transistor is fabricated in bipolar process.

8. With neat sketches explain how Diodes and Resistors are fabricated in nMOS

Process.

9. With neat sketches explain CMOS fabrication using n-well process.

10. With neat sketches explain the fabrication of CMOS inverter using p-well process.

11. Explain in detail about NMOS enhancement mode of operation.

12. Explain in detail the operation of NMOS depletion mode transistor.

13. Explain the process of ion-implantation.

UNIT-2

1. Explain various regions of CMOS inverter transfer characteristics.

2. For a CMOS inverter, calculate the shift in the transfer characteristic curve

When βn/βp ratio is varied from 1/1 to 10/1.

3. Explain nMOS inverter and latch up in CMOS circuits?

4. Draw the nMOS transistor circuit model and explain various components of

The model.

5. Compare the relative merits of three different forms of pull up for an inverter

Circuits. What is the best choice for realization in

(a) NMOS technology

(b) CMOS technology

6. Explain the operation of BiCMOS inverter? Clearly specify its characteristics.

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7. Explain how the BiCMOS inverter performance can be improved.

8. Define threshold voltage of a MOS device and explain its significance.

9. Explain the effect of threshold voltage on MOSFET current Equations.

10 With neat sketches explain the formation of the inversion layer in n-channel

Enhancement MOSFET.

11. A PMOS Transistor is operated in the triode region with the following para

meters. VGS = −4.5V; Vtp = −1V ; VDS = −2.2V ; W/L = 95; μnCox =95 μA/V 2

Find its drain current and drain source resistance.

12. Clearly explain the sub-threshold conduction of the MOSFET.

13. Show that switching speed of an enhancement MOSFET various inversely as

The square of channel length.

14. Derive an equation for IDS of an n-channel Enhancement MOSFET operating

in Saturation region.

15. An nMOS transistor is operating in saturation region with the following parameters.

VGS = 5V; Vtn = 1.2V ; W/L = 110; μnCox = 110 μA/V 2.

Find Transconductance of the device.

UNIT-3

1. What is a stick diagram? Draw the stick diagram and layout for a CMOS

Inverter.

2. What are the effects of scaling on Vt?

3. What are design rules? Why is metal- metal spacing larger than poly –poly spacing.

4. Draw the stick diagram and mask layout for a CMOS two input NOR gate and

Stick diagram of two input NAND gate.

5. Draw the stick diagram and a translated mask layout for nMOS inverter circuit.

6. Explain the following

(a) Double metal MOS process rules.

(b) Design rules for P- well CMOS process

7. Design a stick diagram for two input n-MOS NAND and NOR gates.

8. Design a stick diagram for the NMOS logic shown below Y = (A + B + C)’ .

9. Design a stick diagram for n-MOS Ex-NOR gate.

10. Design a stick diagram for the PMOS logic shown below Y = ((A + B).C)’.

11. Design a layout diagram for the PMOS logic shown below Y = (AB)’ + (CD)’.

12. Design a layout diagram for nMOS inverter

13. Explain about the following

(a) Lambda - based design rules

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(b) Double metal process rules.

UNIT-4

1. Calculate the rise time and fall time of the CMOS inverter (W/L)n= 6 and (W/L)p=8,

K′n =150μ A/V 2, Vtn =0.7V, K′p= 62 μ A/V 2, Vtp=-0.85V, VDD =3.3V. Total out-put

capacitance =150 fF.

2. Explain the concept of sheet resistance and apply it to compute the ON resis

tance (VDD to GND) of an NMOS inverter having pull up to pull down ratio

Of 4:1, If n channel resistance is Rsn = 104 per square.

3. Calculate the gate capacitance value of 5μm technology minimum size transistor

With gate to channel capacitance value is 4 × 10 -4

pF/μm2.


on the performance of a VLSI circuit.

5. Define and explain the following:

i. Sheet resistance concept applied to MOS transistors and inverters.

ii. Standard unit of capacitance.

6. Explain the requirement and functioning of a delay unit.

7. Two nMOS inverters are cascaded to drive a capacitive load CL=14Cg as shown in

Figure. Calculate the pair delay Vin to Vout in terms of τ for the given data.

Inverter -A


Inverter -B


8. Calculate on resistance of the circuit shown in Figure 1 from VDD to GND. If n-

Channel sheet resistance Rsn = 10 4 per square and p-channel sheet resistance

Rsp = 2.5 × 104 per square.

9. Calculate the gate capacitance value of 2μm technology minimum size transistor

with gate to channel capacitance value is 8 × 10−4pF/μm2.

10. Explain clearly about different parasitic capacitances of an nMOS transistor.

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UNIT-5

1. Explain the CMOS system design based on the data path operators with a

suitable example.

2. Draw and explain the basic Memory- chip architecture.

3. Explain the CMOS system design based on the data path operators with a

suitable example.

4. Draw and explain the basic Memory- chip architecture.

5. Compare the different types of CMOS subsystem Multipliers.

6. Design a schematic for an 8-word × 2-bit NAND ROM that serves a lookup

table to implement a full adder.

7. Draw the schematic for tiny XOR gate and explain its operation.

8. Draw the circuit diagram for 4-by-4 barrel shifter using complementary trans-

mission gates and explain its shifting operation.

9. Explain about the following gate array based ASICS

(a) Channel gate arrays

(b) Channel less gate arrays

(c) Structured gate arrays

UNIT-6

1. Explain the function of 4:1 Mux in PAL CMOS device with the help of I/O

structure.

2. Explain how the pass transistors are used to connect wire segments for the

purpose of FPGA programming.

3. Explain the methods of programming of PAL CMOS device.

4. Draw and explain the architecture of an FPGA.

5. What are the characteristics of 22V10 PAL CMOS device and draw its I/O

structure.

6. Explain any one chip architecture that used the antifuse and give its advantages.

7. Draw the typical standard-cell structure showing low-power cell and explain it.

8. Sketch a diagram for two input XOR using PLA and explain its operation

with the help of truth table.

9. Using PLA Implement JK Flip flop circuit

10.With neat sketches explain the architecture of PAL

UNIT-7

1. Write a VHDL Program for a divide-by-3 counter with suitable state diagram.

2. Compare all available design verification tools.

3. What are the different types of operators used in VHDL? Give some examples

using this.

4. Compare the Circuit-level, Logic-level, switch-level and Timing simulations.

5. What are the different data types available in VHDL and how they are indicated?

6. Write a VHDL program for a 4-bit Counter with Asynchronous reset.

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7. What are the advantages of Hardware Description Languages and give some

examples?

8. Explain the different types of simulators used to predict and verify the performance of

given circuit.

9. What are the inputs that are provided to the synthesis tool? And explain completely

about synthesis process in the ASIC design.

10. Explain the following processes in the ASIC design flow.

(a) Post - layout timing simulation.

(b) Post synthesis simulation.

11. With respect to synthesis process explain the following terms.

A) Flattening

B) Factoring

C) Mapping

UNIT-8

1. Draw the basic structure of parallel scan and explain how it reduces the long

scan chains.

2. Draw the state diagram of TAP Controller and explain how it provides the

control signals for test data and instruction register.

3. Draw the basic structure of parallel scan and explain how it reduces the long

scan chains.

4. Draw the state diagram of TAP Controller and explain how it provides the

control signals for test data and instruction register.

5. Compare functionality test and manufacturing test.

6. What type of testing techniques are suitable for the following:

i. Memories

ii. Random logic

iii. Data path.

7. How IDDQ testing is used to test the bridge faults?

8. Explain how an improved layout can be reduced faults in CMOS circuits.

9. Explain how a pseudo random sequence generator may be used to test a 16-bitdata path.

How would the outputs be collected and checked.

10. Explain about the following packaging design considerations.

(a) VLSI design rules.

(b) Thermal design consideration.

UNIT-1

OBJECTIVE QUESTIONS

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1 MOS Means

(a) Metal oxide silicon technology

(b) Metal oxide semiconductor technology

(c) Any of (a) and (b)

(d) None

2 n MOS devices are formed in a ___________ substrate of moderate doping level.

(a) P - type (b) n - type

(c) Either a and b (d) None

3 The source and drain in a n MOS device are formed by diffusing _________ impurities.

(a) n - type

(b) p - type

(c) Either a (or) b

(d) None

4 The connections to the source and drain are made by a deposited_________ layer

(a) P diffusion

(b) n diffusion

(c) Epitanial

(d) Metal

5 A gate is deposited on a layer of insulation over the region between source and drain in

a enhacement mode device

(a) Oxide (b) Polysilicon

(c) Metal (d) None.

6 If the gate is connected to a suitable positive voltage then a is formed between source

and drain (c)

(a) Non conducting layer (b) epitaxial Layer

(c) Conducting Layer (d) None

7 The source and drain are connected by a conducting channel but the channel may now

be cleared by applying a suitable voltage to the gate

(a) Negative (b) Positive

(c) Zero (d) None.

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8 In a Pmos device the substrate is of ________ type material

(a) n - type

(c) Either a or b

9 The source and drain material are type in a pMOS device

(a) p type (b) n type

(c) Either a or b (d) none.

10 The fabrication of CMOS is done by

(a) n - well process (b) p - well process

(c) Both a and b (d) None

11 The Limited deive capability of MOS transistors can be overcome by ______________

technology

(a) CMOS

(b) TTL

(c) Bi - CMOS

(d) None

12 The Bi CMOS npn transistor consists of

(a) P+base region

(b) n+ collector area

(c) Buried subcollector

(d) All the above

13 Process simulation can be done for the following process in IC fabrication

(a) Lithography

(b) implantation

(c) Etching

(d) All the above

14 Oxidation in IC fabrication refers to the chemical process of reaction of O_with ______

(a) Si with O 2

(b) Si with N 2

(c) Si with H 2

(d) None

(b) p-type

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15 The following is a type of oxidation

(a) Thermal oxidation

(b)High pressure oxidation

(c) Plasma oxidation

(d) All the above

16 Thermal oxiadation is done in

(a) Resistance heated oxidation furnace

(b) Ion implantation furnace

(c) Either a or b

(d) None.

17 The oxidizing species are transported from the bark of the gas phase to gas oxide

intergace with flex (a) F

(b) F 2

(c) F 3

(d) None.

18 The flux F is given by F = h G (CG - Cs) where h G is

(a) Gas phase Maes transfer coefficient

(b) Liquid phase Maes transfer coefficient

(c) Solid phase Maes transfer coefficient

(d) None.

19 The rate of oxidation depends on

(a) Supply of oxidant to interface

(b) The reaction rate constant RS and Ci

(c) Both a and b

(d) None.

20 The high - pressure oxidation process is applied to the oxide isolation of ___________

LSI with fully ion implanted shallow junctions and multi level metallizor.

(a) High speed bipolar

(b) Low speed bipolar

(c) High speed CMOS

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(d) Low speed CMOS

UNIT-2

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UNIT-3

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UNIT-4

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UNIT-5

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UNIT-6

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UNIT-7

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13.UNIVERSITY QUESTION PAPERS:

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III B.Tech II Semester Regular Examinations, Apr/May 2009

VLSI DESIGN

Code No: R05320402 Set No. 1

1. With neat sketches explain the Ion -lithography process. [16]

2. (a) Explain different forms of pull ups used as load, in CMOS and in enhancement

& depletion modes of NMOS.

(b) Determine the pull up to pull down ratio of an nMOS inverter driven by another

nMOS transistor. [8+8]

3. Design a stick diagram and layout for two input CMOS NAND gate indicating all the

regions & layers [16]

4. Describe the following briefly

(a)Cascaded inverters as drivers.

(b) Super buffers.

(c) BiCMOS drivers. [8+4+4]

5. Explain briefly the CMOS system design based on the data path operators, memory

elements, control structures and I/O cells with suitable examples. [16]

6. (a) Draw and explain the FPGA chip architecture.

(b) Draw and explain the AND/NOR representation of PLA. [8+8]

7. (a) Write a VHDL program for 7-sengment display decoder.

(b) What are the basic sources of errors in CMOS circuits and how these are

tested? Give name of such a simulator. [8+8]

8. (a) Explain the gate level and function level of testing.

(b) A sequential circuit with in? inputs and ‘m’ storage devices. To test this

circuit how many test vectors are required.

(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6]


1. Write in detail about integrated passive components. [16]

2. (a) Explain the operation of BiCMOS inverter? Clearly specify its characteristics.

(b) Explain how the BiCMOS inverter performance can be improved. [8+8]

3. (a) what is a stick diagram? Draw the stick diagram and layout for a CMOS

inverter.

(b) What are the effects of scaling on Vt?

(c) What are design rules? Why is metal- metal spacing larger than poly -poly

spacing. [8+4+4]

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4. (a) Determine an equation for the propagation delay from input to output of the

pass transistor chain shown in figure 4a with the help of its equivalent circuit.

Figure 4a

(b) What are super Buffers? [12+4]

5. (a) Explain how a Booth recoded multiplier reduces the number of adders.

(b) Draw circuit diagram of a one transistor with transistor capacitor dynamic

RAM and also draw its layout. [8+8]

6. (a) Draw the typical architecture of PAL and explain the operation of it.

(b) What is CPLD? Draw its basic structure and give its applications. [8+8]

7. (a) What is meant by enumeration type of data and give some example for it?

(b) What are the different Libraries used in VHDL? Write the syntax to load it.

(c) Explain how the delay of a statement is related to simulation and synthesis.

[6+6+4]

8. (a) What is ATPG? Explain a method of generation of test vector.

(b) Explain the terms controllability, observability and fault coverage. [8+8]


1. Explain the MOS Transistor operation with the help of neat sketches in the following

modes

(a) Enhancement mode

(b) Depletion mode. [8+8]

2. (a) Draw an nMOS transistor model indicating all the components.

(b) Explain latch up problem in CMOS circuits. [8+8]

3. (a) What is Moore’s law? Explain its relevance with respect to evolution of tech

nology.

(b) What are different VLSI technologies available compare their speed/power

performance.

(c) Why is VLSI design process presented in NMOS only?

(d) Discuss the micro electronics evolution. [6+4+2+4]

4. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic.

(b) In gate logic, compare the geometry aspects between two -input NMOS NAND and

CMOS NAND gates. [8+8]

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5. (a) Design a magnitude comparator based on the data path operators.

(b) Draw the Schematic and mask layout of array adder used in Booth Multiplier

and explain the principle of multiplication in Booth Multiplier. [6+10]

6. (a) What are the characteristics of 22V10 PAL CMOS device and draw its I/O

structure.

(b) Explain any one chip architecture that used the antifuse and give its advantages. [8+8]

7. (a) What are the advantages of Hardware Description Languages and Software

Languages?

(b) What are different design verification tools and explain them in brief? [8+8]

8. (a) Draw the basic structure of parallel scan and explain how it reduces the long scan

chains.

(b) Draw the state diagram of TAP Controller and explain how it provides the

control signals for test data and instruction register. [8+8]


1. (a) With neat sketches explain the NMOS fabrication procedure.

(b) Draw the cross sectional view of CMOS P - Well inverter. [8+8]

2. (a) Derive an equation for Transconductance of an n channel enhancement MOSFET

operating in active region.

(b) A PMOS transistor is operated in triode region with the following parameters.

VGS=- 4.5V, Vtp= -1V; VDS=-2.2 V, (W/L) =95, μnCox =95μA/V 2. Find its

drain current and drain source resistance. [8+8]

3. (a) Discuss design rule for wires (orbit 2μm CMOS).

(b) Discuss the transistor related design rule (orbit 2μm CMOS). [8+8]

4. Two NMOS inverters are cascaded to drive a capacity load CL= 14Cg as shown in

figure 4.

Calculate the pair delay Vin to Vout in terms of τ for the given data

inverter-A. [16]

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Lpu=12λ, Wpu=4λ, Lpd=1λ, Wpd=8λ

Inverter-B

Lpu=4λ, Wpu=4λ, Lpd=2λ, Wpd=8λ

Figure 4

5. (a) Design a magnitude comparator based on the data path operators.

(b) Draw the Schematic and mask layout of array adder used in Booth Multiplier

and explain the principle of multiplication in Booth Multiplier. [6+10]

6. Write briefly about:

(a) Channelled gate arrays

(b) Channelless gate arrays with neat sketches. [8+8]

7. (a) How to represent a tristate in VHDL and explain it with suitable program.

(b) What is rat’s-nest wiring diagram? Explain its significance in system design.

[8+8]

8. (a) Draw the basic structure of parallel scan and explain how it reduces the long scan

chains.

(b) Draw the state diagram of TAP Controller and explain how it provides the

control signals for test data and instruction register. [8+8]

III B.Tech Supplimentary Examinations, Aug/Sep 2008

VLSI DESIGN


1. With neat sketches explain BICMOS fabrication process in an N well. [16]

2. (a) With neat sketches, explain the transfer characteristic of a CMOS inverter.

(b) Derive an equation for Ids of an n-channel enhancement MOSFET operating

in saturation region. [8+8]

3. Design a stick diagram and layout for the NMOS logic shown below

Y = ((A + B)C)1 [16]

4. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic.

(b) In gate logic, compare the geometry aspects between two -input NMOS NAND and

CMOS NAND gates. [8+8]

5. (a) Draw the top level schematic and a floor plan for 16 × 16 Booth recoded

multiplier and explain its operation.

(b) Explain the tradeoffs between open, closed, and twisted bit lines in a dynamic

RAM array. [8+8]

6. (a) Draw and explain the Antifuse Structure for programming the PAL device.

(b) Explain how the I/O pad is programmed in FPGA. [8+8]

7. (a) Write a architecture for a 4- bit Counter in both behavioral and structural

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styles.

(b) Explain with example how mixed mode simulator are more for CMOS circuits

testing. [8+8]

8. (a) What are the reasons of malfunctioning of chip? What are the different levels of

testing?

(b) Explain how a parallel scan is used for data path test.

(c) What is mean by level sensitive of logic system? [6+6+4]


1. Write in detail about integrated passive components. [16]

2. (a) Explain various regions of CMOS inverter transfer characteristics.

(b) For a CMOS inverter, calculate the shift in the transfer characteristic curve

when βn/βp ratio is varied from 1/1 to 10/1. [8+8]

3. (a) Write the scaling factors for different types of device parameters.

(b) Discuss the limits due to sub threshold currents. [8+8]


on the performance of a VLSI circuit. [16]

5. (a) Draw the schematic for tiny XOR gate and explain its operation.

(b) Draw the circuit diagram for 4-by-4 barrel shifter using complementary trans-

mission gates and explain its shifting operation. [8+8]

6. (a) Draw and explain the Antifuse Structure for programming the PAL device.

(b) Explain how the I/O pad is programmed in FPGA. [8+8]

7. (a) Compare the Hardware and Software Languages.

(b) Draw the basic design flow through typical CMOS VLSI tools and give some

names of corresponding tools. [8+8]

8. (a) What type of defects are tested in manufacturing testing methods?

(b) What is the Design for Autonomous Test and what is the basic device used in

this?

(c) What type of tests are used to check the noise margin for CMOS gates?[4+6+6]


1. With neat sketches necessary, explain the oxidation process in the IC fabrication

process. [16]

2. (a) Draw an nMOS transistor model indicating all the components.

(b) Explain latch up problem in CMOS circuits. [8+8]

3. (a) Discuss in detial the NMOS design style.

(b) Discuss CMOS design style. Compare with NMOS design style. [8+8]

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on the performance of a VLSI circuit. [16]

5. (a) Explain how a Booth recoded multiplier reduces the number of adders.

(b) Draw circuit diagram of a one transistor with transistor capacitor dynamic

RAM and also draw its layout. [8+8]

6. (a) Draw the typical standard-cell structure showing regular-power cell and ex-

plain it.

(b) Draw and explain the pseudo-nMOS PLA schematic for full adder and what

are the advantages and disadvantages of it. [8+8]

7. (a) Explain how VHDL is developed and where it was used initially.

(b) What are the different design capture tools? Explain them briefly. [8+8]

8. (a) Explain how function of system can be tested.

(b) Explain any one of the method of testing bridge faults.

(c) What type of faults can be reduced by improving layout design? [6+5+5]



process. [16]

2. (a) Derive an equation for rds of an n channel enhancement MOSFET in linear

region.

(b) Plot the transfer characteristic of an nMOS inverter as a function of Vds.[8+8]

3. (a) Discuss in detial the NMOS design style.

(b) Discuss CMOS design style. Compare with NMOS design style. [8+8]

4. (a) Explain the requirement and operation of pass transistors and transmission

gates.

(b) Compare pseudo-n MOS logic and clocked CMOS logic. [8+8]

5. (a) How can the components of CMOS system design be categorized into the

groups.

(b) Why is the static 6 transistor cell used for average CMOS system design?

(c) Compare the performance of CMOS Off chip and On chip memory designs.

[4+6+6]

6. (a) Draw a self timed dynamic PLA and what are the advantages of it compared to

footed dynamic PLA.

(b) Explain the tradeoffs between using a transmission gate or a tristate buffer to

implement an FPGA routing block. [8+8]

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7. (a) What are the different types of operators used in VHDL? Give some examples

using this.

(b) Compare the Circuit-level, Logic-level, switch-level and Timing simulations.

[8+8]

8. (a) Explain the gate level and function level of testing.

(b) A sequential circuit with ?n? inputs and ‘m’ storage devices. To test this

circuit how many test vectors are required.

(c) What is sequential fault grading? Explain how it is analyzed. [6+4+6]

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