demo manual dca - analog.com · plots are taken with 10-pole lc filters made by tte (los angeles,...
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1dc1763afb
DEMO MANUAL DC1763A
Description
LTC2195, LTC2194, LTC2193, LTC2192, LTC2191, LTC2190, LTC2271
16-Bit, 20Msps to 125Msps Dual ADCs
Demonstration circuit 1763A supports a family of 16-Bit 20Msps to 125Msps ADCs. Each assembly features one of the following devices: LTC®2195, LTC2194, LTC2193, LTC2192, LTC2191, LTC2190, LTC2271 high speed, dual ADCs.
The versions of the 1763A demo board are listed in Table 1. Depending on the required resolution and sample rate, L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks
and PScope is a trademark of Linear Technology Corporation. All other trademarks are the property of their respective owners.
the DC1763A is supplied with the appropriate ADC. The circuitry on the analog inputs is optimized for analog input frequencies from 5MHz to 140MHz. Refer to the data sheet for proper input networks for different input frequencies.
Design files for this circuit board are available at http://www.linear.com/demo/DC1763A
Table 1. DC1763A VariantsDC1763A VARIANTS ADC PART NUMBER RESOLUTION MAXIMUM SAMPLE RATE INPUT FREQUENCY
1763A-A LTC2195 16-Bit 125Msps 5MHz to 140MHz
1763A-B LTC2194 16-Bit 105Msps 5MHz to 140MHz
1763A-C LTC2193 16-Bit 80Msps 5MHz to 140MHz
1763A-D LTC2192 16-Bit 65Msps 5MHz to 140MHz
1763A-E LTC2191 16-Bit 40Msps 5MHz to 140MHz
1763A-F LTC2190 16-Bit 25Msps 5MHz to 140MHz
1763A-G LTC2271 16-Bit 20Msps 5MHz to 140MHz
perForMAnce sUMMArY (TA = 25°C)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Voltage – DC1763A Depending on Sampling Rate and the A/D Converter Provided, this Supply Must Provide up to 500mA.
3 3.6 6 V
Analog Input Range Depending on SENSE Pin Voltage 1 2 VP-P
Logic Input Voltages Minimum Logic High Maximum Logic Low
1.3 0.6
V V
Logic Output Voltages (Differential) Nominal Logic Levels (100Ω Load, 3.5mA Mode) Common Mode Minimum Logic Levels (100Ω Load, 3.5mA Mode) Common Mode
350 1.25 247 1.25
mV V
mV V
Sampling Frequency (Convert Clock Frequency) See Table 1
Encode Clock Level Single-Ended Encode Mode (ENC– Tied to GND) Differential Encode Mode (ENC– Not Tied to GND)
0 0.2
3.6 3.6
V V
Resolution See Table 1
Input Frequency Range See Table 1
SFDR See Applicable Data Sheet
SNR See Applicable Data Sheet
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DEMO MANUAL DC1763A
TO PROVIDEDUSB CABLE
TO PROVIDEDPOWER SUPPLY
ANALOG INPUTS
CHANNEL 1
PARALLEL/SERIAL SINGLE-ENDEDENCODE CLOCK(USE PROVIDED DC1075,DIVIDE BY 4-CLOCK BOARD)
dc1763a F01
CHANNEL 2
3V TO 6V
qUick stArt proceDUre
Figure 1. Demo Board Setup
Demonstration circuit 1763A is easy to set up to evaluate the performance of the LTC2195 A/D converter family. Refer to Figure 1 for proper measurement equipment setup and follow the procedure below:
Setup
If a DC1371 PStache Data Acquisition and Collection System was supplied with the DC1763A demonstration circuit, follow the DC1371 Quick Start Guide to install the required software and for connecting the DC1371 to the DC1763A and to a PC.
DC1763A Demonstration Circuit Board Jumpers
The DC1763 demonstration circuit board should have the following jumper settings as default positions: (as per Figure 1)
JP13: PAR/SER : Selects parallel or serial programming mode. (Default: serial)
Optional Jumpers:
JP5: ILVDS: Selects either 1.75mA or 3.5mA of output current for the LVDS drivers. (Default: 3.5mA)
JP15: SHDN: Enables and disables the LTC2195. (De-fault: SHDN)
JP2: WP: Enable/Disables write protect for the EEPROM. (Default: EN)
JP14/JP8: LANE/TERM: Two bits that select between one, two and four lanes.
JP14 – LANE JP8 TERM NUMBER OF LANES
2 DIS 2
2 EN 4
1 DIS 1
1 EN Not Used
(Default: JP8: EN, JP14: 1)
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DEMO MANUAL DC1763A
qUick stArt proceDUreNotes:
1. The DC1371 does not support 1- or 4-lane operation.
2. Optional jumper should be left open to ensure proper serial configuration.
3. In the first revision of this demo board the jumpers were mislabeled. For boards labeled with a Rev 1 use the following jumper positions:
a. JP8: Term: Selects either 1.75mA or 3.5mA of output current for the LVDS drivers. (Default: 3.5mA)
b. JP14/JP5: ILVDS/LANE: Two bits that select between one, two and four lanes.
JP14 – ILVDS JP5 LANE NUMBER OF LANES
3.5mA 2 2
3.5mA 1 1
1.75mA 2 4
1.75mA 1 Not Used
Applying Power and Signals to the DC1763A Demonstration Circuit
If a DC1371 is used to acquire data from the DC1763A, the DC1371 must FIRST be connected to a powered USB port and have 5V applied BEFORE applying 3.0V to 6V across the pins marked V+ and GND on the DC1763A. DC1763A requires 3.6V for proper operation.
Regulators on the board produce the voltages required for the ADC. The DC1763A demonstration circuit requires up to 500mA depending on the sampling rate and the A/D converter supplied.
The DC1763A should not be removed, or connected to the DC1371 while power is applied.
Analog Input Network
For optimal distortion and noise performance the RC network on the analog inputs may need to be optimized for different analog input frequencies. For input frequen-cies above 140MHz, refer to the LTC2195 data sheet for a proper input network. Other input networks may be more appropriate for input frequencies less that 5MHz.
In almost all cases, filters will be required on both analog input and encode clock to provide data sheet SNR.
The filters should be located close to the inputs to avoid reflections from impedance discontinuities at the driven end of a long transmission line. Most filters do not present 50Ω outside the passband. In some cases, 3dB to 10dB pads may be required to obtain low distortion.
If your generator cannot deliver full-scale signals without distortion, you may benefit from a medium power amplifier based on a gallium arsenide gain block prior to the final filter. This is particularly true at higher frequencies where IC based operational amplifiers may be unable to deliver the combination of low noise figure and High IP3 point required. A high order filter can be used prior to this final amplifier, and a relatively lower Q filter used between the amplifier and the demo circuit.
Apply the analog input signal of interest to the SMA con-nectors on the DC1763A demonstration circuit board marked J3 AIN1 and J4 AIN2. These inputs correspond with channels one and two of the ADC respectively. These inputs are capacitively coupled to balun transformers ETC1-1-13 (lead free part number MABA007159-000000).
Encode Clock
NOTE: Apply an encode clock to the SMA connector on the DC1763A demonstration circuit board marked J12 CLK+. As a default the DC1763A is populated to have a single-ended input.
For the best noise performance, the encode clock must be driven with a very low jitter, square wave source. The amplitude should be large, up to 3VP-P or 13dBm. When using a sinusoidal signal generator a squaring circuit can be used. Linear Technology also provides demo board DC1075 that divides a high frequency sine wave by four, producing a low jitter square wave for best results with the LTC2195. Using band pass filters on the clock and the analog input will improve the noise performance by reducing the wideband noise power of the signals. In the case of the DC1763A a band pass filter used for the clock should be used prior to the DC1075. Data sheet FFT plots are taken with 10-pole LC filters made by TTE (Los Angeles, CA) to suppress signal generator harmonics, non-harmonically related spurs and broadband noise. Low phase noise Agilent 8644B generators are used for both the clock input and the analog input.
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DEMO MANUAL DC1763A
qUick stArt proceDUreDigital Outputs
The data outputs, data clock, and frame clock signals are available on J1 of the DC1763A. This connector follows the VITA-57/FMC standard, but all signals should be verified when using an FMC carrier card other than the DC1371.
Software
The DC1371 is controlled by the PScope™ System Soft-ware provided or downloaded from the Linear Technology website at http://www.linear.com/software/.
To start the data collection software if PScope.exe, is in-stalled (by default) in \Program Files\LTC\PScope\, double click the PScope icon or bring up the run window under the start menu and browse to the PScope directory and select PScope.
If the DC1763A demonstration circuit is properly connected to the DC1371, PScope should automatically detect the DC1763A, and configure itself accordingly. If everything is hooked up properly, powered and a suitable convert clock is present, clicking the Collect button should result in time and frequency plots displayed in the PScope window. Ad-ditional information and help for PScope is available in the DC1371 Quick Start Guide and in the online help available within the PScope program itself.
Serial Programming
PScope has the ability to program the DC1763A board serially through the DC1371. There are several options available in the LTC2195 family that are only available through serially programming. PScope allows all of these features to be tested.
These options are available by first clicking on the Set Demo Bd Options icon on the PScope toolbar (Figure 2).
This will bring up the menu shown in Figure 3.
Figure 3. Demobd Configuration Options
Figure 2. PScope Toolbar
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DEMO MANUAL DC1763A
qUick stArt proceDUreThis menu allows any of the options available for the LTC2195 family to be programmed serially. The LTC2195 family has the following options:
Randomizer: Enables data output randomizer
• Off(Default):Disablesdataoutputrandomizer
• On:Enablesdataoutputrandomizer
Two’s Complement: Enables two’s complement mode
• Off(Default):Selectsoffsetbinarymode
• On:Selectstwo’scomplementmode
Sleep Mode: Selects between normal operation, sleep mode:
• Off(Default):EntireADCispowered,andactive
• On:TheentireADCispowereddown.
Channel 1 Nap: Selects between normal operation and putting channel 1 in nap mode.
• Off(Default):Channeloneisactive
• On:Channeloneisinnapmode
Channel 2 Nap: Selects between normal operation and putting channel 2 in nap mode.
• Off(Default):Channeltwoisactive
• On:Channeltwoisinnapmode
Output Current: Selects the LVDS output drive current
• 1.75mA(Default):LVDSoutputdrivercurrent
• 2.1mA:LVDSoutputdrivercurrent
• 2.5mA:LVDSoutputdrivercurrent
• 3.0mA:LVDSoutputdrivercurrent
• 3.5mA:LVDSoutputdrivercurrent
• 4.0mA:LVDSoutputdrivercurrent
• 4.5mA:LVDSoutputdrivercurrent
Internal Termination: Enables LVDS internal termination
• Off(Default):Disablesinternaltermination
• On:Enablesinternaltermination
Outputs: Enables digital outputs
• Enabled(Default):Enablesdigitaloutputs
• Disabled:Disablesdigitaloutputs
Test Pattern: Selects digital output test patterns. The desired test pattern can be entered into the text boxes provided.
• Off(Default):ADCinputdataisdisplayed
• On:Testpatternisdisplayed.
Once the desired settings are selected hit OK and PScope will automatically update the register of the device on the DC1763A demo board.
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DEMO MANUAL DC1763A
pArts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
General BOM
1 1 CN1 CAP, ARRAY, 0508 2.2µF 20% 4V X5R AVX, W2L14D225MAT1A
2 11 C5, C7, C8, C9, C15, C16, C18, C28, C36, C48, C52
CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A
3 1 C4 CAP., X5R, 1µF, 10V, 10% 0402 AVX, 0402ZD105KAT2A
4 1 C6 CAP., TANT., 100µF, 16V, 10% 6032 AVX, TPSC107K016R0200
5 3 C10, C53, C54 CAP., X7R, 1µF,10V, 10% 0603 AVX, 0603ZC105KAT2A
6 1 C17 CAP., X5R, 2.2µF, 10V, 20% 0603 AVX, 0603ZD225MAT2A
7 2 C29, C37 CAP., X5R, 2.2µF, 6.3V, 20% 0402 AVX, 04026D225MAT2A
8 7 C30, C38, C43-C47 CAP., X7R, 0.01µF, 16V, 10% 0402 AVX, 0402YC103KAT2A
9 4 C31, C32, C39, C40 CAP., COG, 8.2pF, 50V, 5% 0402 AVX, 04025A8R2JAT2A
10 1 C49 CAP., X7R, 0.01µF, 25V, 10% 0402 AVX, 04023C103KAT2A
11 1 C51 CAP., X5R, 4.7µF, 6.3V 20% 0603 AVX, 06036D475MAT2A
12 1 J1 BGA CONNECTOR, 40X10 SAMTEC, SEAM-40-02.0-S-10-2-A
13 6 JP2, JP5, JP8, JP13, JP14, JP15 HEADER, 3-PIN 0.079 SINGLE ROW SAMTEC, TMM-103-02-L-S
14 2 J3, J4 CON., SMA 50Ω, EDGE-LAUNCH EF JOHNSON, 142-0701-851
15 2 J11, J12 CON.,SMA JACK, STRAIGHT, THRU-HOLE AMPHENOL CONNEX, 132134
16 2 L4, L5 INDUCTOR, 56nH 0603 MURATA, LQP18MN56NG02D
17 1 L7 FERRITE BEAD, 0603 MURATA, BLM18BB470SN1D
18 2 L9, L11 FERRITE BEAD, 1206 MURATA, BLM31PG330SN1L
19 2 R1, R63 RES., CHIP, 0Ω 0402 YAGEO, RC0402FR-070RL
20 0 R2, R57-R59, R61, R62, R64, R65 OPT, RES, CHIP, 0402
21 12 R4, R5, R10, R36, R102-R109 RES., CHIP, 10k, 1/16W, 5% 0402 YAGEO, RC0402JR-0710KL
22 2 R8, R92 RES., CHIP, 100Ω, 1/16W, 1% 0402 YAGEO, RC0402FR-07100RL
23 6 R9, R11, R14, R72, R73, R74 RES., CHIP, 1k, 1/16W, 5% 0402 YAGEO, RC0402JR-071KL
24 1 R12 RES., CHIP, 31.6k, 1/16W, 1% 0402 YAGEO, RC0402FR-0731K6L
25 4 R26, R29, R39, R46 RES., CHIP, 64.9Ω, 1/16W, 1% 0402 VISHAY, CRCW040264R9FKED
26 9 R30, R47, R56, R60, R95-R99 RES., CHIP, 100Ω, 1/16W, 5% 0402 YAGEO, RC0402JR-07100RL
27 8 R31, R32, R33, R34, R48-R51 RES., CHIP, 10.0Ω, 1/16W, 1% 0402 YAGEO, RC0402FR-0710RL
28 2 R35, R52 RES., CHIP, 86.6Ω, 1/16W, 1%, 0402 YAGEO, RC0402FR-0786R6L
29 4 R37, R38, R53, R54 RES., CHIP, 86.6Ω, 1/16W, 1% 0603 YAGEO, RC0603FR-0786R6L
30 2 R40, R41 RES., CHIP, 49.9Ω, 1/16W, 1% 0402 YAGEO, RC0402FR-0749R9L
31 2 R42, R43 RES., CHIP, 5.1Ω,, 1/16W, 1% 0402 YAGEO, RC0402FR-075R1L
32 8 R110-R117 RES., CHIP, 33k, 1/16W, 1% 0402 YAGEO, RC0402FR-0733KL
33 3 TP1, TP6, TP7 TESTPOINT, TURRET, 0.094, PBF MILL- MAX, 2501-2-00-80-00-00-07-0
34 3 T5, T9, T11 TRANSFORMER, RF~SMT~1:1BALUN MACOM, MABA-007159-000000
35 2 T8, T10 TRANSFORMER, FLUX-COUPLED BALUN MACOM, MABAES0060
36 1 U2 IC, LT1763CS8-1.8 SO8 LINEAR TECH., LT1763CS8-1.8#PBF
37 1 U3 I.C. EEPROM 32KBIT 400kHz 8TSSOP MICROCHIP, 24LC32A-I/ST
38 6 XJ2, XJ5, XJ8, XJ13, XJ14, XJ15 SHUNT, 0.079" CENTER SAMTEC, 2SN-BK-G
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DEMO MANUAL DC1763A
pArts listITEM QTY REFERENCE PART DESCRIPTION MANUFACTURER/PART NUMBER
DC1763A-A1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2195CUKG
DC1763A-B1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2194CUKG
DC1763A-C1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2193CUKG
DC1763A-D1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2192CUKG
DC1763A-E1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2191CUKG
DC1763A-F1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP., X5R, 0.1µF, 10V, 10% 0402 AVX, 0402ZD104KAT2A3 4 C25, C26, C33, C34 CAP., X7R, 0.01µF, 50V, 10% 0603 AVX, 06035C103KAT2A4 2 C27, C35 CAP, COG, 4.7pF, 50V, 5% 0402 AVX, 04025A4R7JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2190CUKG
DC1763A-G1 1 GENERAL BOM DC1763A2 2 C2, C3 CAP, 0402 1µF 20% 10V X5R TDK C1005X5R1A105M3 4 C25, C26, C33, C34 CAP, 0402 0.1µF 10% 10V X5R TDK C1005X5R1A104K4 2 C27, C35 CAP, 0402 10pF 5% 50V NPO AVX 04025A100JAT2A5 1 U1 DUAL A/D CONVERTER LINEAR TECH., LTC2271CUKG
8dc1763afb
DEMO MANUAL DC1763A
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SIZE
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:
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O.
REV.
SHEE
TOF
TITL
E:
APPR
OVA
LS
PCB
DES.
APP
ENG.
TE
CH
NO
LOG
YFa
x: (4
08)4
34-0
507
Milp
itas,
CA
9503
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one:
(408
)432
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0
1630
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arth
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vd.
LTC
Conf
iden
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63A
C29
2.2u
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292.
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R46
64.9
R46
64.9
C16
0.1u
FC
160.
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C39
8.2p
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398.
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86.6
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86.6
C28
0.1u
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280.
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R37
86.6
R37
86.6
C17
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172.
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86.6
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R65
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408.
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86.6
R35
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LT17
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1.8
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1.8
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GND3
BY
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5
GND6
GND7
IN8
R33
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1
72
63
54
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100
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100
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R59
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360.
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64.9
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64.9
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RE
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PA
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10
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2+11
AIN
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GN
D13
VC
M2
14
Vdd15
Vdd16
ENC+17
ENC-18
CS19
SCK20
SDI21
GND22
OUT2D-23
OUT2D+24
OUT2C-25
OUT2C+26
OU
T2B
-27
OU
T2B
+28
OU
T2A
-29
OU
T2A
+30
FR-
31FR
+32
OG
ND
33O
Vdd
34D
CO
-35
DC
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D-
37O
UT1
D+
38O
UT1
C-
39O
UT1
C+
40
OUT1B-41
OUT1B+42
OUT1A-43
OUT1A+44
GND45
SDO46
GND47
Vref48
GND49
SENSE50
Vdd51
Vdd52
EP53
R47
100
R47
100
C7
0.1u
FC
70.
1uF
C35
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7pf
C35
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7pf
R92
100
R92
100
C30
0.01
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300.
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C37
2.2u
FC
372.
2uF
C26
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C26
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C38
0.01
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380.
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L7
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AD
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58O
PT
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62O
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610
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L9
BE
AD
R51
10R51
10
R30
100
R30
100
R8
100
R8
100
9dc1763afb
DEMO MANUAL DC1763A
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
scheMAtic DiAgrAM5 5
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SIZE
DATE
:
IC N
O.
REV.
SHEE
TOF
TITL
E:
APPR
OVA
LS
PCB
DES.
APP
ENG.
TE
CH
NO
LOG
YFa
x: (4
08)4
34-0
507
Milp
itas,
CA
9503
5Ph
one:
(408
)432
-190
0
1630
McC
arth
y Bl
vd.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S M
ADE
A BE
ST E
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T TO
DES
IGN
ACI
RCUI
T TH
AT M
EETS
CUS
TOM
ER-S
UPPL
IED
SPEC
IFIC
ATIO
NS;
HOW
EVER
, IT
REM
AINS
THE
CUS
TOM
ER'S
RES
PONS
IBIL
ITY
TOVE
RIFY
PRO
PER
AND
RELI
ABLE
OPE
RATI
ON IN
THE
ACT
UAL
APPL
ICAT
ION.
COM
PONE
NT S
UBST
ITUT
ION
AND
PRIN
TED
CIRC
UIT
BOAR
D LA
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MAY
SIG
NIFI
CANT
LY A
FFEC
T CI
RCUI
TPE
RFOR
MAN
CE O
R RE
LIAB
ILIT
Y. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G F
OR A
SSIS
TANC
E.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MAT
IC
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
ww
w.li
near
.com 1
22
16-B
IT D
UAL,
HIG
H SP
EED,
SER
IAL
LVDS
ADC
M.H
.
CLAR
ENCE
M.
N/A
LTC2
19XC
UKG
FAM
ILY
DEM
O CI
RCUI
T 17
63A
SIZE
DATE
:
IC N
O.
REV.
SHEE
TOF
TITL
E:
APPR
OVA
LS
PCB
DES.
APP
ENG.
TE
CH
NO
LOG
YFa
x: (4
08)4
34-0
507
Milp
itas,
CA
9503
5Ph
one:
(408
)432
-190
0
1630
McC
arth
y Bl
vd.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S M
ADE
A BE
ST E
FFOR
T TO
DES
IGN
ACI
RCUI
T TH
AT M
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TOM
ER-S
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IFIC
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NS;
HOW
EVER
, IT
REM
AINS
THE
CUS
TOM
ER'S
RES
PONS
IBIL
ITY
TOVE
RIFY
PRO
PER
AND
RELI
ABLE
OPE
RATI
ON IN
THE
ACT
UAL
APPL
ICAT
ION.
COM
PONE
NT S
UBST
ITUT
ION
AND
PRIN
TED
CIRC
UIT
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D LA
YOUT
MAY
SIG
NIFI
CANT
LY A
FFEC
T CI
RCUI
TPE
RFOR
MAN
CE O
R RE
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ILIT
Y. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G F
OR A
SSIS
TANC
E.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MAT
IC
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
ww
w.li
near
.com 1
22
16-B
IT D
UAL,
HIG
H SP
EED,
SER
IAL
LVDS
ADC
M.H
.
CLAR
ENCE
M.
N/A
LTC2
19XC
UKG
FAM
ILY
DEM
O CI
RCUI
T 17
63A
SIZE
DATE
:
IC N
O.
REV.
SHEE
TOF
TITL
E:
APPR
OVA
LS
PCB
DES.
APP
ENG.
TE
CH
NO
LOG
YFa
x: (4
08)4
34-0
507
Milp
itas,
CA
9503
5Ph
one:
(408
)432
-190
0
1630
McC
arth
y Bl
vd.
LTC
Conf
iden
tial-F
or C
usto
mer
Use
Onl
y
CUST
OMER
NOT
ICE
LINE
AR T
ECHN
OLOG
Y HA
S M
ADE
A BE
ST E
FFOR
T TO
DES
IGN
ACI
RCUI
T TH
AT M
EETS
CUS
TOM
ER-S
UPPL
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SPEC
IFIC
ATIO
NS;
HOW
EVER
, IT
REM
AINS
THE
CUS
TOM
ER'S
RES
PONS
IBIL
ITY
TOVE
RIFY
PRO
PER
AND
RELI
ABLE
OPE
RATI
ON IN
THE
ACT
UAL
APPL
ICAT
ION.
COM
PONE
NT S
UBST
ITUT
ION
AND
PRIN
TED
CIRC
UIT
BOAR
D LA
YOUT
MAY
SIG
NIFI
CANT
LY A
FFEC
T CI
RCUI
TPE
RFOR
MAN
CE O
R RE
LIAB
ILIT
Y. C
ONTA
CT L
INEA
RTE
CHNO
LOGY
APP
LICA
TION
S EN
GINE
ERIN
G F
OR A
SSIS
TANC
E.
THIS
CIR
CUIT
IS P
ROPR
IETA
RY T
O LI
NEAR
TEC
HNOL
OGY
AND
SCHE
MAT
IC
SUPP
LIED
FOR
USE
WIT
H LI
NEAR
TEC
HNOL
OGY
PART
S.SC
ALE
= NO
NE
ww
w.li
near
.com 1
22
16-B
IT D
UAL,
HIG
H SP
EED,
SER
IAL
LVDS
ADC
M.H
.
CLAR
ENCE
M.
N/A
LTC2
19XC
UKG
FAM
ILY
DEM
O CI
RCUI
T 17
63A
J1J
SE
AM
-10X
40P
IN
J1J
SE
AM
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40P
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DJ1
CLK
1_C
2M_P
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CLK
1_C
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J3
GN
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GN
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HA
03_P
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HA
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GN
DJ8
HA
07_P
J9
HA
07_N
J10
GN
DJ1
1
HA
11_P
J12
HA
11_N
J13
GN
DJ1
4
HA
14_P
J15
HA
14_N
J16
GN
DJ1
7
HA
18_P
J18
HA
18_N
J19
GN
DJ2
0
HA
22_P
J21
HA
22_N
J22
GN
DJ2
3
HB
01_P
J24
HB
01_N
J25
GN
DJ2
6
PB
07_P
J27
HB
07_N
J28
GN
DJ2
9
HB
11_P
J30
HB
11_N
J31
GN
DJ3
2
HB
15_P
J33
HB
15_N
J34
GN
DJ3
5
HB
18_P
J36
HB
18_N
J37
GN
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8
VIO
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2CJ3
9
GN
DJ4
0
R73
1KR73
1K
R10
810
KR
108
10K
R72
1KR72
1K
J1E
SE
AM
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40P
IN
J1E
SE
AM
-10X
40P
INGN
DE
1
HA
01_P
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HA
01_N
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GN
DE
4
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DE
5
HA
05_P
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HA
05_N
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GN
DE
8
HA
09_P
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09_N
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11
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13_P
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HA
13_N
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14
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16_P
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16_N
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17
HA
20_P
E18
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20
HB
03_P
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HB
03_N
E22
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DE
23
HB
05_P
E24
HB
05_N
E25
GN
DE
26
HB
09_P
E27
HB
09_N
E28
GN
DE
29
HB
13_P
E30
HB
13_N
E31
GN
DE
32
HB
21_P
E33
HB
21_N
E34
GN
DE
35
HB
20_P
E36
HB
20_N
E37
GN
DE
38
VA
DJ
E39
GN
DE
40
R5
10K
R5
10K
R10
210
KR
102
10K
R10
710
KR
107
10K
JP15
JP15
1
2
3
R74
1KR74
1K
J1A
SE
AM
-10X
40P
IN
J1A
SE
AM
-10X
40P
INGN
DA
1
DP
1_M
2C_P
A2
DP
1_M
2C_N
A3
GN
DA
4
GN
DA
5
DP
2_M
2C_P
A6
DP
2_M
2C_N
A7
GN
DA
8
GN
DA
9
DP
3_M
2C_P
A10
DP
3_M
2C_N
A11
GN
DA
12
GN
DA
13
DP
4_M
2C_P
A14
DP
4_M
2C_N
A15
GN
DA
16
GN
DA
17
DP
5_M
2C_P
A18
DP
5_M
2C_N
A19
GN
DA
20
GN
DA
21
DP
1_C
2M_P
A22
DP
1_C
2M_N
A23
GN
DA
24
GN
DA
25
DP
2_C
2M_P
A26
DP
2_C
2M_N
A27
GN
DA
28
GN
DA
29
DP
3_C
2M_P
A30
DP
3_C
2M_N
A31
GN
DA
32
GN
DA
33
DP
4_C
2M_P
A34
DP
4_C
2M_N
A35
GN
DA
36
GN
DA
37
DP
5_C
2M_P
A38
DP
5_C
2M_N
A39
GN
DA
40
R98
100
R98
100
R10
310
KR
103
10K
R11
533
KR
115
33K
R10
10K
R10
10K
R97
100
R97
100
J1K
SE
AM
-10X
40P
IN
J1K
SE
AM
-10X
40P
IN
VR
EF_
B_M
2CK
1
GN
DK
2
GN
DK
3
CLK
1_M
2C_P
K4
CLK
1_M
2C_N
K5
GN
DK
6
HA
02_P
K7
HA
02_N
K8
GN
DK
9
HA
06_P
K10
HA
06_N
K11
GN
DK
12
HA
10_P
K13
HA
10_N
K14
GN
DK
15
HA
17_P
_CC
K16
HA
17_N
_CC
K17
GN
DK
18
HA
21_P
K19
HA
21_N
K20
GN
DK
21
HA
23_P
K22
HA
23_N
K23
GN
DK
24
HB
00_P
_CC
K25
HB
00_N
_CC
K26
GN
DK
27
HB
06_P
_CC
K28
HB
06_N
_CC
K29
GN
DK
30
HB
10_P
K31
HB
10_N
K32
GN
DK
33
HB
14_P
K34
HB
14_N
K35
GN
DK
36
HB
17_P
_CC
K37
HB
17_N
_CC
K38
GN
DK
39
VIO
_B_M
2CK
40
JP14
JP14
1
2
3
R10
910
KR
109
10K
R99
100
R99
100
J1F
SE
AM
-10X
40P
IN
J1F
SE
AM
-10X
40P
IN
PG
_M2C
F1
GN
DF2
GN
DF3
HA
00_P
_CC
F4
HA
00_N
_CC
F5
GN
DF6
HA
04_P
F7
HA
04_N
F8
GN
DF9
HA
08_P
F10
HA
08_N
F11
GN
DF1
2
HA
12_P
F13
HA
12_N
F14
GN
DF1
5
HA
15_P
F16
HA
15_N
F17
GN
DF1
8
HA
19_P
F19
HA
19_N
F20
GN
DF2
1
HB
02_P
F22
HB
02_N
F23
GN
DF2
4
HB
04_P
F25
HB
04_N
F26
GN
DF2
7
HB
08_P
F28
HB
08_N
F29
GN
DF3
0
HB
12_P
F31
HB
12_N
F32
GN
DF3
3
HB
16_P
F34
HB
16_N
F35
GN
DF3
6
HB
19_P
F37
HB
19_N
F38
GN
DF3
9
VA
DJ
F40
R11
633
KR
116
33K
J1B
SE
AM
-10X
40P
IN
J1B
SE
AM
-10X
40P
IN
RE
S1
B1
GN
DB
2
GN
DB
3
DP
9_M
2C_P
B4
DP
9_M
2C_N
B5
GN
DB
6
GN
DB
7
DP
8_M
2C_P
B8
DP
8_M
2C_N
B9
GN
DB
10
GN
DB
11
DP
7_M
2C_P
B12
DP
7_M
2C_N
B13
GN
DB
14
GN
DB
15
DP
6_M
2C_P
B16
DP
6_M
2C_N
B17
GN
DB
18
GN
DB
19
GB
TCLK
1_M
2C_P
B20
GB
TCLK
1_M
2C_N
B21
GN
DB
22
GN
DB
23
DP
9_C
2M_P
B24
DP
9_C
2M_N
B25
GN
DB
26
GN
DB
27
DP
8_C
2M_P
B28
DP
8_C
2M_N
B29
GN
DB
30
GN
DB
31
DP
7_C
2M_P
B32
DP
7_C
2M_N
B33
GN
DB
34
GN
DB
35
DP
6_C
2M_P
B36
DP
6_C
2M_N
B37
GN
DB
38
GN
DB
39
RE
S0
B40
R11
1KR11
1K
R10
610
KR
106
10K
R11
433
KR
114
33K
R96
100
R96
100
R12
31.6
KR
1231
.6K
R1 0R1 0
R95
100
R95
100
J1G
SE
AM
-10X
40P
IN
J1G
SE
AM
-10X
40P
INGN
DG
1
CLK
0_C
2M_P
G2
CLK
0_C
2M_N
G3
GN
DG
4
GN
DG
5
LA00
_P_C
CG
6
LA00
_N_C
CG
7
GN
DG
8
LA03
_PG
9
LA03
_NG
10
GN
DG
11
LA08
_PG
12
LA08
_NG
13
GN
DG
14
LA12
_PG
15
LA12
_NG
16
GN
DG
17
LA16
_PG
18
LA16
_NG
19
GN
DG
20
LA20
_PG
21
LA20
_NG
22
GN
DG
23
LA22
_PG
24
LA22
_NG
25
GN
DG
26
LA25
_PG
27
LA25
_NG
28
GN
DG
29
LA29
_PG
30
LA29
_NG
31
GN
DG
32
LA31
_PG
33
LA31
_NG
34
GN
DG
35
LA33
_PG
36
LA33
_NG
37
GN
DG
38
VA
DJ
G39
GN
DG
40
R9
1KR9
1K
JP13
JP13
1
2
3
R11
733
KR
117
33K
J1C
SE
AM
-10X
40P
IN
J1C
SE
AM
-10X
40P
INGN
DC
1
DP
0_C
2M_P
C2
DP
0_C
2M_N
C3
GN
DC
4
GN
DC
5
DP
0_M
2C_P
C6
DP
0_M
2C_N
C7
GN
DC
8
GN
DC
9
LA06
_PC
10
LA06
_NC
11
GN
DC
12
GN
DC
13
LA10
_PC
14
LA10
_NC
15
GN
DC
16
GN
DC
17
LA14
_PC
18
LA14
_NC
19
GN
DC
20
GN
DC
21
LA18
_P_C
CC
22
LA18
_N_C
CC
23
GN
DC
24
GN
DC
25
LA27
_PC
26
LA27
_NC
27
GN
DC
28
GN
DC
29
SC
LC
30
SD
AC
31
GN
DC
32
GN
DC
33
GA
0C
34
12P
0VC
35
GN
DC
36
12P
0VC
37
GN
DC
38
3P3V
C39
GN
DC
40
R4
10K
R4
10K
JP5
JP5
1
2
3
R10
510
KR
105
10K
R11
033
KR
110
33K
JP8
JP8
1
2
3
R2
OP
TR
2O
PT
J1H
SE
AM
-10X
40P
IN
J1H
SE
AM
-10X
40P
IN
VR
EF_
A_M
2CH
1
PR
SN
T_M
2C_N
H2
GN
DH
3
CLK
0_M
2C_P
H4
CLK
0_M
2C_N
H5
GN
DH
6
LA02
_PH
7
LA02
_NH
8
GN
DH
9
LA04
_PH
10
LA04
_NH
11
GN
DH
12
LA07
_PH
13
LA07
_NH
14
GN
DH
15
LA11
_PH
16
LA11
_NH
17
GN
DH
18
LA15
_PH
19
LA15
_NH
20
GN
DH
21
LA19
_PH
22
LA19
_NH
23
GN
DH
24
LA21
_PH
25
LA21
_NH
26
GN
DH
27
LA24
_PH
28
LA24
_NH
29
GN
DH
30
LA28
_PH
31
LA28
_NH
32
GN
DH
33
LA30
_PH
34
LA30
_NH
35
GN
DH
36
LA32
_PH
37
LA32
_NH
38
GN
DH
39
VA
DJ
H40
JP2
JP2
1
2
3
J1D
SE
AM
-10X
40P
IN
J1D
SE
AM
-10X
40P
IN
PG
_C2M
D1
GN
DD
2
GN
DD
3
GB
TCLK
0_M
2C_P
D4
GB
TCLK
0_M
2C_N
D5
GN
DD
6
GN
DD
7
LA01
_P_C
CD
8
LA01
_N_C
CD
9
GN
DD
10
LA05
_PD
11
LA05
_ND
12
GN
DD
13
LA09
_PD
14
LA09
_ND
15
GN
DD
16
LA13
_PD
17
LA13
_ND
18
GN
DD
19
LA17
_P_C
CD
20
LA17
_N_C
CD
21
GN
DD
22
LA23
_PD
23
LA23
_ND
24
GN
DD
25
LA26
_PD
26
LA26
_ND
27
GN
DD
28
TCK
D29
TDI
D30
TDO
D31
3P3V
AU
XD
32
TMS
D33
TRS
T_N
D34
GA
1D
35
3P3V
D36
GN
DD
37
3P3V
D38
GN
DD
39
3P3V
D40
R11
133
KR
111
33K
R36
10K
R36
10K
R11
333
KR
113
33K
R10
410
KR
104
10K
U3
24LC
32A
-I /S
TU
324
LC32
A-I
/ST
A0
1A
12
A2
3
VSS4
SD
A5
SC
L6
WP
7
VCC8
C18
0.1u
FC
180.
1uF
R11
233
KR
112
33K
10dc1763afb
DEMO MANUAL DC1763A
Linear Technology Corporation1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com LINEAR TECHNOLOGY CORPORATION 2011
LT 0815 REV B • PRINTED IN USA08
DEMONSTRATION BOARD IMPORTANT NOTICE
Linear Technology Corporation (LTC) provides the enclosed product(s) under the following AS IS conditions:
This demonstration board (DEMO BOARD) kit being sold or provided by Linear Technology is intended for use for ENGINEERING DEVELOPMENT OR EVALUATION PURPOSES ONLY and is not provided by LTC for commercial use. As such, the DEMO BOARD herein may not be complete in terms of required design-, marketing-, and/or manufacturing-related protective considerations, including but not limited to product safety measures typically found in finished commercial goods. As a prototype, this product does not fall within the scope of the European Union directive on electromagnetic compatibility and therefore may or may not meet the technical requirements of the directive, or other regulations.
If this evaluation kit does not meet the specifications recited in the DEMO BOARD manual the kit may be returned within 30 days from the date of delivery for a full refund. THE FOREGOING WARRANTY IS THE EXCLUSIVE WARRANTY MADE BY THE SELLER TO BUYER AND IS IN LIEU OF ALL OTHER WARRANTIES, EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. EXCEPT TO THE EXTENT OF THIS INDEMNITY, NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT, SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES.
The user assumes all responsibility and liability for proper and safe handling of the goods. Further, the user releases LTC from all claims arising from the handling or use of the goods. Due to the open construction of the product, it is the user’s responsibility to take any and all appropriate precautions with regard to electrostatic discharge. Also be aware that the products herein may not be regulatory compliant or agency certified (FCC, UL, CE, etc.).
No License is granted under any patent right or other intellectual property whatsoever. LTC assumes no liability for applications assistance, customer product design, software performance, or infringement of patents or any other intellectual property rights of any kind.
LTC currently services a variety of customers for products around the world, and therefore this transaction is not exclusive.
Please read the DEMO BOARD manual prior to handling the product. Persons handling this product must have electronics training and observe good laboratory practice standards. Common sense is encouraged.
This notice contains important safety information about temperatures and voltages. For further safety concerns, please contact a LTC applica-tion engineer.
Mailing Address:
Linear Technology
1630 McCarthy Blvd.
Milpitas, CA 95035
Copyright © 2004, Linear Technology Corporation