delayed branch
DESCRIPTION
Delayed Branch. All problems solved? NO, what will happen if...... b loop add $4 $6 $1 .. . loop sub. Add. B loop. Zero ext. =. =. Branch logic. 0. A. ALU. 4. B. +. =. =. 31. +. Sgn/Ze extend. sub. Add. B loop. Zero ext. =. =. Branch logic. 0. A. ALU. 4. - PowerPoint PPT PresentationTRANSCRIPT
MicroComputer Engineering DelayedBranch slide1
Delayed Branch
All problems solved?
NO, what will happen if......
b loop
add $4 $6 $1
..
.
loop sub
MicroComputer Engineering DelayedBranch slide2
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
B loopAdd
MicroComputer Engineering DelayedBranch slide3
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
B loopAdd sub
MicroComputer Engineering DelayedBranch slide4
Delayed Branch
- Throughput might decrease, (nop).
- Assembler/Compiler dependent.
+ Keep critical path short
MicroComputer Engineering DelayedBranch slide5
All problems solved now?
NO, what will happen if......
..
bal loop
add $4 $6 $1
xor ....
loop: sub ...
..
j $ra
MicroComputer Engineering DelayedBranch slide6
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
> ADDR 0x00400000 bal loop
bal loop
ADDR 0x00400004
MicroComputer Engineering DelayedBranch slide7
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400000 bal loop
> ADDR 0x00400004 add
ADDR 0x00400004
bal loopadd
MicroComputer Engineering DelayedBranch slide8
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400004
ADDR 0x00400004
bal loopadd
ADDR 0x00400000 bal loop
ADDR 0x00400004 add >loop: sub
sub
MicroComputer Engineering DelayedBranch slide9
Branch
logic
Sgn/Ze
extend
Zero ext.
sub
.. .. j $ra
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400004
jr $ra
MicroComputer Engineering DelayedBranch slide10
Branch
logic
Sgn/Ze
extend
Zero ext.
Oooh not again!!!
ALU
A
B
31
0
4+
+
= =
= =
0x00400004 add
MicroComputer Engineering DelayedBranch slide11
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
4
4+
+
= =
= =
ADDR 0x00400004
ADDR 0x00400008
Continue at 0x00400008bal loopadd sub
MicroComputer Engineering DelayedBranch slide12
Branch
logic
Sgn/Ze
extend
Zero ext.
sub
.. .. j $ra
ALU
A
B
31
0
4+
+
= =
= =
ADDR 0x00400008
jr $ra
MicroComputer Engineering DelayedBranch slide13
All Hazards Fixed but:
One “delayed branch” slot
MicroComputer Engineering DelayedBranch slide14
What about “delayed Branch”
Can we avoid it? How?
MicroComputer Engineering DelayedBranch slide15
IM
Reg DM Reg
Delayed Branch
Direct Branch
BranchLogic
IM
Reg DM Reg
BranchLogic
MicroComputer Engineering DelayedBranch slide16
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
Delayed Branch
MicroComputer Engineering DelayedBranch slide17
Branch
logic
Sgn/Ze
extend
Zero ext.
ALU
A
B
31
0
4+
+
= =
= =
Branch
logic
Direct Branch
MicroComputer Engineering DelayedBranch slide18
What about the instruction set?
beq $t0 $t0 label? jr $ra? NO, DE is not in path! b label? OK, but the new branch logic needs an ALU
to compute the address
MicroComputer Engineering DelayedBranch slide19
Different branch logic?
Can both branch types coexist? Yes, no problem, but: Old type still uses “delay slot”