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Delay Test

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Topics to be DiscussedDelay test definitionCircuit delays and event propagationPath-delay tests

Non-robust testRobust testFive-valued logic and test generation

Path-delay fault (PDF) and other fault modelsTest application methods

Combinational, enhanced-scan and normal-scanVariable-clock and rated-clock methods

At-speed testTiming design and delay testSummary

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Delay Test Definition

A circuit that passes delay test must produce correct outputs when inputs are applied and outputs observed with specified timing.For a combinational or synchronous sequential circuit, delay test verifies the limits of delay in combinational logic.Delay test problem for asynchronous circuits is complex and not well understood.

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Digital Circuit Timing

Inpu

tsO

utpu

ts

time

Transientregion

Clock period

Comb.logic

OutputObservation

instant

InputSignal

changes

SynchronizedWith clock

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Observations

For correct operation, the delay of the combinational circuit must not exceed the clock period.

Typical outputs of logic circuits can contain transients as shown in the previous slide.

In order to examine the timing operation of a circuit we should examine signal transitions.

The last example consists of two vectors: 010 → 100.Delay tests consists of vector pairs.

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All input transitions occur at the same time in the figure.

Idealized situation though it closely resembles the real situation.The transient region at the output contains multiple transitions that are separated in time.The position of each output transition depends upon the delay of some input to output combinational path.

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The right edge of the output transition region (red shaded area) is determined by the last transition.

Delay of the longest combinational path activated by the current input vector-pair.Considering all possible input vector-pairs, the longest delay of the combinational path of the circuit is called the critical path.The delay of critical paths determines the smallest clock period at which the circuit can function correctly.

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For a manufactured circuit to function correctly, the output transition region for any input vector-pair must not expand beyond the clock period.

Otherwise, the circuit is said to have a delay fault.A delay fault means that the delay of one or more paths (not necessarily the critical path) exceeds the clock period.

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Circuit DelaysSwitching or inertial delay is the interval between input change and output change of a gate:

Depends on input capacitance, device (transistor) characteristics and output capacitance of gate.Also depends on input rise or fall times and states of other inputs (second-order effects).Approximation: fixed rise and fall delays (or min-max delay range, or single fixed delay) for gate output.

Propagation or interconnect delay is the time a transition takes to travel between gates:

Depends on transmission line effects (distributed R, L, Cparameters, length and loading) of routing paths.Approximation: modeled as lumped delays for gate inputs.

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Each path can potentially produce one signal transition at the output.The location of an output transition in time is determined by the delay of the path.

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Example: Transition propagation through paths

2 4 61

1 3

5

3

10

0

0

2

2

Path P1

P2

P3

Single lumped inertial delay modeled for each gatePI transitions assumed to occur without time skew

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Example: contd.

The critical path has a delay of 6 time units in the fault-free circuit.

Path P3 is one of the two critical paths.Suppose we choose the clock period T to be 7.Any path will be faulty if its delay exceeds 7 time units.

Consider two cases:Singly faulty pathsMultiple faulty paths

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Example: contd.

Single faulty pathWe examine the output at 7 units of time.As long as the delay of path P3 is ≤ 6, the output will become high irrespective of the delay of path P1 or P2.

Delay faults of P1 or P2 will not be detected by this input vector pair (010 → 100).

If the delay of P3 exceeds 7 time units, the output will be observed incorrectly.

Delay fault of path P3 is detectable by the vector pair.

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Example: contd.

Multiple faulty pathsSuppose all three paths P1, P2, P3 have more than 7 units of delay.

Entire output waveform will get shifted right, and we will observe a failure.

Suppose P1 is not faulty, but P2 and P3 are faulty.Output will rise at 2 units and will remain high beyond 7 units.May fall depending on the relative delays of P2 and P3.Observing at 7 time units, however, will not show any failure.Fault of P2 interferes with the detection of fault at P3.Why this happens:

– Because the vector-pair is a non-robust test for delay fault of P3.

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Path-Delay Fault

Path delay faultThe delay defect in the circuit is assumed to cause the cumulative delay of a combinational circuit to exceed some specified duration.

For each combinational path in a circuit, there are two path-delay faults corresponding to rising and falling transitions, respectively.The total number of (single) path-delay faults is twice the number of physical paths in the circuit.In general, any combination of paths can be faulty.

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Path-Delay Test

Non-robust path-delay testA test that guarantees to detect a path-delay fault, when no other path-delay fault is present, is called a non-robust test for that fault.

A path-delay fault for which a non-robust test exists is called a singly-testable path-delay fault.

Applies a transition (vector pair) at the input of the path and measures the output value after a specified interval.

Signals lying on the path are called on-path signals.Signals that are not in the path but feed the gates on the path are called off-path signals.

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A non-robust test consists of a vector-pair V1, V2, such that:1. The change V1 → V2 initiates the appropriate transition

at the beginning of the path under test.2. All off-path input signals for the path under test assume

non-controlling values in the steady-state following the application of the second vector v2.– Called static sensitization of the path.

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Singly-Testable Paths(Non-Robust Test)

V1 V2 V1 V2

Static sensitization guarantees a test when the target path is the only faulty path. The test is, therefore, called non-robust.

A path with no such test is called a false path.

Targetpath

Off-path inputs

don’tcare

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Robust path-delay testA robust test guarantees the detection of a delay fault of the target path, irrespective of delay faults on other paths.A robust test consists of a vector-pair V1, V2, that produces an event at the output such that:1. It should be a real event, defined as a transition from the initial

value to the final value.2. It should be a controlling event.

– Permits no other events to appear prior to its own appearance.– Output will remain at initial value until the controlling event

occurs.

A robust test is also a non-robust test.

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A Five-valued Algebra

Due to Lin and Reddy [IEEE TCAD, 1987].Signal states:

S0, S1 : steady (without glitch) 0 and 1 for both V1 and V2.U0, U1 : final values as 0 and 1, respectively, with the initial values as X.X : don’t care, or undefined.

Notations:F0 : falling transition on on-path signals (same as U0).R1 : rising transition on on-path signals (same as U1).

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V1 V2 V1 V2V1 V2

V1 V2

V1 V2

V1 V2

U1

U1

U1/R1

S1

U0/F0

S1

U0

U0

U0/F0

U1/R1

U1/R1

U1/R1U0/F0

U0/F0

S0S0

Robust Test Conditions

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S0 U0 S1 U1 XX

S0 S0 S0 S0 S0 S0U0 S0 U0 U0 U0 U0S1 S0 U0 S1 U1 XXU1 S0 U0 U1 U1 XXXX S0 U0 XX XX XX

Input 1

Inpu

t 2

S0 U0 S1 U1 XX

S0 S0 U0 S1 U1 XXU0 U0 U0 S1 U1 XXS1 S1 S1 S1 S1 S1U1 U1 U1 S1 U1 U1XX XX XX S1 U1 XX

Input 1

Inpu

t 2

InputS0 U0 S1 U1 XX

S1 U1 S0 U0 XX

AND OR

NOT

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Example: Robust Test Generation

R1

S0U0

R1

XX S0

U0

F0

U0

Path P3

Test for P3 – falling transition through path P3: Steps A through E

F0

XX

A. Place F0 atpath origin

B. Propagate F0 through OR gate;also propagates as R1 throughNOT gate

C. F0 interpreted as U0;propagates throughAND gate

D. Change off-path inputto S0 to Propagate R1through OR gate

E. Set input of AND gate toS0 to justify S0 at output

Robust Test:S0, F0, U0

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Example: Non-Robust Test Generation

U1

U0

XX U1

U0

R1

R1

Path P2

Fault P2 – rising transition through path P2 has no robust test.

R1

XX

A. Place R1 atpath origin

B. Propagate R1 through OR gate;interpreted as U1 on off-path signal;propagates as U0 through NOT gate

D. R1 non-robustly propagatesthrough OR gate since off-path input is not S0

C. Set input of AND gate topropagate R1 to output

Non-robust test:U1, R1, U0

U1 Non-robust test requiresStatic sensitization:S0=U0, S1=U1

R1

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Since off-path input is not S0 (or S1), a robust test is not possible.For a non-robust test, we change S0 and S1 to U0 and U1, respectively.

Because non-robust test requires static sensitization.

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Example: Untestable path delay fault

The path delay fault ↓ P2 is untestable.Forward implication sets the off-path input of the output OR gate to U1.Since U1 is controlling value in V2, this path-delay fault has no test.

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Path Delay Faults that do not Need Testing

Large number of paths are possible in a circuit.A disadvantage.

There exists path delay faults that can never impact circuit performance unless some other paths also have delay faults.

These paths do not need to be tested if the other paths have been tested.

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An Example

P1

P2

a

b c

de

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If path P2 does not have a delay defect that slows down the propagation of ↓, then the value on ‘d’ is determined by ‘a’ and not by ‘c’.Thus, delay defects on path P1 can affect the delay of the circuit only if path P2 also has a delay fault.

Path P1 for ↓ does not have to be tested if path P2 for ↓ is tested.

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Number of Paths in a Circuit

Number of paths can be an exponential function in the number of gates.

The benchmark circuit c6288 is known to have 1.98X1020 paths.Parallel multiplier with 32 inputs, 32 outputs and 2406 gates.

Path counting algorithms work efficiently in spite of the exponential number of paths.

O(N2) algorithm exists.< Look at Example 12.6, page 427, Bushnell&Agrawal>

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Outline of the algorithmConstruct a direct acyclic graph (DAG).

Every PI, PPI, PO and PPO is a vertex in this graph.Two extra vertices, source and sink, are added.Directed edges represent signal flow paths.

Each vertex is assigned a label that equals the number of paths arriving from the source.

Label of source is initialized to 1.Use a levelized graph search algorithm.Label of a visited node is computed as the sum of the labels of its fanin vertices.

The label of sink gives the number of paths in the circuit.

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Complexity of the algorithmSince a vertex can potentially be visited as many times as its in-degree, the worst-case complexity is O(N2), for a DAG with N vertices.

Since maximum indegree of a node is O(N).

For practical circuits, the fanin has a fixed upper bound, and does not grow with N.

So, the complexity is usually O(N).

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Path-Delay Faults (PDF)Two PDFs for each physical path.

One for ↓ transition at the input.One for ↑ transition at the input.

Total number of paths is an exponential function of gates.

Not possible to test all the paths.Critical paths, identified by static timing analysis must be tested.

PDF tests are delay-independent. Robust tests are preferred, but some paths have only non-robust tests.

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Other Delay Fault ModelsSegment-delay fault

A segment of an I/O path is assumed to have large delay such that all paths containing the segment become faulty.

Transition fault A segment-delay fault with segment of unit length (single gate).

Two faults per gate; slow-to-rise and slow-to-fall.Tests are similar to stuck-at fault tests. For example, a line is initialized to 0 and then tested for s-a-0 fault to detect slow-to-rise transition fault.Models localized (spot) delay defects of large delay amounts.

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Delay Test Methodologies

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Slow Clock TestApplicable to combinational circuits or to those sequential circuits that are internally combinational with flip-flops only at PI and PO.

Test architecture shown in next slide.Input and output latches can be either part of the circuit or provided by the ATE.Input and output test clocks control the application of vectors and latching of combinational outputs, respectively.

A two-vector delay test assumes that all signals due to V1 will have reached steady state when V2 is applied.

Vectors are applied at slower than the rated clock.Output clock is skewed by an amount that equals the rated clock period.

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Inputtest clock

Outputtest clock

Combinationalcircuit

Inputlatches

Outputlatches

Inputtest clock

Outputtest clock

V1applied

V2applied Output

latched

Testclockperiod

Ratedclockperiod

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Enhanced Scan Test

Applicable to scan types of sequential circuits.Any arbitrary vector-pair can be applied.A normal scan circuit should be enhanced by inserting hold latches and an additional HOLD signal.Replace scan flip-flops by scan-hold flip-flop (SHFF).

How to apply the vector pairs?State portion of V1 is serially shifted in the scan register, bysetting TC=0 and applying clock CK.Scanned V1 bits are transferred to hold latches by setting HOLD=1, and also apply the PI bits of V1.As signals due to V1 stabilize, the state bits of V2 are scanned in.

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Simultaneous activation of HOLD (=1) and application of PI bits of V2 provides a V1 → V2 transition.Set the circuit in normal mode (TC=1) for exactly one rated-clock period, at the end of which the clock CK latches the combinational outputs in the flip-flops.

– This one cycle of the clock must have the rated-period.– Other clock cycles can have slower period.

Like normal scan, scanout of the response can be overlapped with the scanin of the next vector.

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Scan-Hold Flip-Flop

The control input HOLD keeps the output steady at previous state of flip-flop.Why needed?

Reduce power dissipation during scanIsolate asynchronous parts during scan test

SFF

D

SD

TC

CK

HOLD

Q

Q

To SD ofnext SHFF

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Combinational

circuit

HL

SFFHL

SFF

PI PO

SCANIN

SCAN-OUT

HOLDCK TC

CK TC

CK: system clockTC: test controlHOLD: hold signalSFF: scan flip-flopHL: hold latch

CK

HOLD

CKperiod

Nor

mal

mod

e

Nor

mal

mod

e

TC Scan mode

V1 PIapplied

V2 PIapplied

ScaninV1

states

ScaninV2 states

V1 settles

Resultlatched

Scanoutresult

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Normal-Scan Test

Combinational

circuit

SFF

SFF

PI PO

SCANIN

SCAN-OUT

CK TC

CK TC

CK: system clockTC: test controlSFF: scan flip-flop

RatedCK period

Nor

mal

mod

eTC(A) Scan mode

V1 PIsapplied

V2 PIsapplied

ScaninV1 states

Resultlatched

Resultscanout

V2 states generated, (A) by one-bit scan shift of V1, or

(B) by V1 applied in functional mode.

Scan mode

Normal modeTC(B) Scan modeScan mode

Slow CKperiod

t

Gen. V2states

Pathtested

Slow clock

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Variable-Clock Sequential Test

T 1

PI

PO

T n-2

PI

PO

T n-1

PI

PO

T n+1

PI

PO

T n+m

PI

PO

1

2

1 1

22

T n

PI

PO

Initialization sequence(slow clock)

Pathactivation

(ratedClock)

Fault effectpropagation

sequence(slow clock)

0

0

1

D

Off-pathflip-flop

Note: Slow-clock makes the circuit fault-free in the presence ofdelay faults.

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Variable-Clock Example

ISCAS’89 benchmark s35932 (non-scan).2,124 vectors obtained by simulator-selection from random vectors (Parodi, ITC-98).PDF coverage, 26,228/394,282 ~ 6.7%Longest tested PDF, 27 gates; longest path has 29 gates.Test time ~ 4,511,376 clocks.

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Rated-Clock Sequential Test

All vectors are applied with rated-clock.Paths are singly and multiply activated potentially in several time-frames.Test generation requires a 41-valued logic (Bose, et al., IEEE TVLSI, June 1998).Test generation is extremely complex for non-scan circuits (Bose and Agrawal, ATS-95).Fault simulators are effective but work with conservative assumptions (Bose, IEEE TVLSI, Dec. 1993; Parodi, et al., ITC-98).

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Comparing PDF Test Modes

All PDFs ofseq. circuit

Combinationallytestable PDFs

PDFstestableby variable-clock seq.test

PDFs testable byrated-clock seq. test

Ref.: Majumder, et al., VLSI Design - 98

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At-Speed TestAt-speed test means application of test vectors at the rated-clock speed.Two methods of at-speed test.External test:

Vectors may test one or more functional critical (longest delay)paths and a large percentage (~100%) of transition faults.High-speed testers are expensive.

Built-in self-test (BIST):Hardware-generated random vectors applied to combinational or sequential logic.Only clock is externally supplied.Non-functional paths that are longer than the functional critical path can be activated and cause a good circuit to fail.Some circuits have initialization problem.

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Timing Design & Delay Test

Timing simulation:Critical paths are identified by static (vector-less) timing analysis tools like Primetime (Synopsys).Timing or circuit-level simulation using designer-generated functional vectors verifies the design.

Layout optimization: Critical path data are used in placement and routing. Delay parameter extraction, timing simulation and layout are repeated for iterative improvement.

Testing: Some form of at-speed test is necessary. PDFs for critical paths and all transition faults are tested.

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SummaryPath-delay fault (PDF) models distributed delay defects.

Verifies the timing performance of a manufactured circuit.

Transition fault models spot delay defects and is testable by modified stuck-at fault tests.Variable-clock method can test delay faults but the test time can be long.Critical paths of non-scan sequential circuits can be effectively tested by rated-clock tests.Delay test methods (including BIST) for non-scan sequential circuits using slow ATE require investigation:

Suppression of non-functional path activation in BIST.Difficulty of rated-clock PDF test generation.Long sequences of variable-clock tests.