1

Degradation in gate dielectrics and the effects on Degradation in gate dielectrics and the effects on simple integrated circuit building blockssimple integrated circuit building blocks

((SICBBsSICBBs))

DoDDoD MURI MURI –– Program ReviewProgram Review

Richard Southwick III1, Bill Knowlton1,2 and Jake Baker11Department of Electrical and Computer Engineering

2Department of Materials Science and EngineeringBoise State University, Boise, ID

July 14, 2006

2

AcknowledgmentsAcknowledgments

University InvolvementSTUDENTS:◘ Betsy Cheek (G), ECE◘ Mike Ogas (UG,G) ECE◘ Nate Stutzke (UG), ECE◘ Windy Wilson (UG) ECE◘ Carrie Lawrence (UG,G), ECE◘ Dave Whelchel (UG) ECE◘ Patrick Nagler (UG) ECE◘ David Jenkins (UG) ECE◘ Mark Elgin (UG) ECE◘ Dave Estrada (UG) ECE◘ Terry Gorseth (UG) ECE◘ Josh Kiepert (UG) ECE◘ Patrick Price (UG) MSEFACULTY:◘ Amy Moll, ME Faculty

Industry Involvement◘ Santosh Kumar, Cypress

Semiconductor◘ Dr. Amr Haggag, Motorola/Freescale◘ Dr. Gennadi Bersuker, SEMATECH◘ Dr. Rino Choi, SEMATECH

Funding◘ 2001 DOD Multidisciplinary Research

Initiative (MURI)◘ NSF-Idaho EPSCoR Program ◘ Cypress Semiconductor◘ NSF Major Research Instrumentation

Grant◘ DARPA Grant◘ 2000 Governor’s Higher Education

Initiative - Idaho State Board of Education◘ 2003 Micron Campus Engineering

Research Program◘ NIH INBRE #P20RR16454

3

MURI Supported Journal & Conference PublicationsMURI Supported Journal & Conference Publications((*denotes student authors)*denotes student authors)

Southwick III*, Richard G. and William B. Knowlton, Stacked Dual Oxide MOS Energy Band Diagram Visual Representation Program, IEEE Transactions on Device and Materials Reliability, (2006) - accepted for publication.T. L. Gorseth*, D. Estrada*, J. Kiepert*, M. L. Ogas*, B. J. Cheek*, P.M. Price, R. J. Baker, G. Bersuker, W.B. Knowlton, Preliminary Study of NOR Digital Response to Single pMOSFET Dielectric Degradation, presented at the Workshop on Microelectronic Devices (Boise, Idaho; April 14, 2006)M. L. Ogas*, P. M. Price*, J. Kiepert*, R. J. Baker, G. Bersuker, and W. B. Knowlton, Degradation of Rise Time in NAND Gates Using 2.0 nm Gate Dielectrics, oral presentation and publication at the 2005 IEEE Integrated Reliability Workshop, (October 2005) p. 63-66.Ogas* M. L., R. G. Southwick III* B. J. Cheek* R. J. Baker, G. Bersuker, W. B. Knowlton, Survey of Oxide Degradation in Inverter Circuits Using 2.0nm MOS Devices, in proceedings of the 2004 IEEE International Integrated Reliability Workshop, (Oct. 2004), pp. 32-36.Cheek* Betsy J., Stutzke* Nate, Santosh Kumar, R. Jacob Baker, Amy J. Moll and William B. Knowlton, Investigation of Circuit-Level Oxide Degradation and its Effect on CMOS Inverter Operation Performance and MOSFET Characteristics, in proceedings of the 2004 IEEE International Reliability Physics Symposium (April, 25-29, 2004) pp. 110-116.Kumar, Santosh, William B. Knowlton, Sridhar Kasichainula and Cesar Payan, SRAM Subthreshold Current Recovery after unipolar AC stressing, in proceedings of the 2004 IEEE International Reliability Physics Symposium (April, 25-29, 2004) pp. 46-48.Stutzke*, N., B.J. Cheek*, S. Kumar, R.J. Baker, A.J. Moll and W.B. Knowlton, Effects of Circuit-Level Stress on Inverter Performance and MOSFET Characteristics, in proceedings 2003 IEEE International Integrated Reliability Workshop, (Oct, 20-23, 2003) pp. 71-79.Payan, C., S. Kumar, A. Thupil, S. Kasichainula and W.B. Knowlton, Leakage Current Recovery in SRAM after AC stressing, in proceedings 2003 IEEE International Integrated Reliability Workshop, (Oct, 20-23, 2003) pp. 67-70.Lawrence*, C.E., B.J. Cheek*, T.E. Lawrence*, Santosh Kumar, A. Haggag, R.J. Baker, and W.B. Knowlton, Gate Dielectric Degradation Effects on nMOS Devices Using a Noise Model Approach, in Proceedings of the 15th Biennial IEEE University/Government/Industry Microelectronics (UGIM) Symposium, June 30 - July 2, 2003, pp.263-266.Kumar, Santosh and William B. Knowlton, Alternate method of TDDB study for aluminum oxide using magneto-resistance. in IEEE International Integrated Reliability Workshop, (2002) pp. 180-183.Knowlton, W.B., T. Caldwell*, J.J. Gomez*, and S. Kumar. On the nature of ultrathin gate oxide degradation during pulse stressing of nMOSCAPs in accumulation. in IEEE International Integrated Reliability Workshop, (2001) pp. 87-88.

4

MURI Supported Conference Presentations, Posters and MURI Supported Conference Presentations, Posters and Extended Abstracts Extended Abstracts (to show inclusion of UG and Grad students as authors*)(to show inclusion of UG and Grad students as authors*)

Richard Southwick III*, Michael Ogas* and William B. Knowlton, Interactive dual oxide MOS energy band diagram program, poster presentation at the 2005 IEEE International Integrated Reliability Workshop, (October 2005).Richard G. Southwick III*, Vaughn Johnson*, Joe Lindsey*, Tim Lawrence*, Jim Jozwiak, Amy Moll, William B. Knowlton, Through Wafer Interconnects: Preliminary Investigation Of Plasma Induced Damage In pMOSFETs By BOSCH DRIE, poster presentation at 2004 IEEE International Integrated Reliability Workshop, (Oct. 2004).Ogas*, Michael, Richard Southwick III*, Betsy Cheek*, Carrie Lawrence*, BSU, Santosh Kumar, Amr Haggag, Jacob Baker, and William Knowlton, Multiple Waveform Pulse Voltage Stress Technique for Modeling Noise in Ultra Thin Oxides, poster presentation at Workshop on Microelectronics and Electron Devices, (Boise, Idaho, April 16, 2004).Ogas, Michael*, Dorian Kiri*, Ouahid Salhi*, Richard Southwick III*, Betsy Cheek*, William B. Knowlton, Investigation of Ultra Thin Gate Oxide Reliability in MOS Devices and Simple ICs, poster presentation at Workshop on Microelectronics and Electron Devices, (Boise, Idaho, April 16, 2004) and at 2004 IEEE International Integrated Reliability Workshop, (Oct. 2004).Ogas*, M. L., R. G. Southwick III, B. J. Cheek*, C. E. Lawrence*, S. Kumar, A. Haggag, R. J. Baker, W. B. Knowlton, Investigation of Multiple waveform pulse voltage stress (MWPVS) technique in ultrathin oxides, poster presentation at the 2003 IEEE International Integrated Reliability Workshop (Oct, 20-23, 2003).Stutzke*, Nate, Betsy J. Cheek*, and William B. Knowlton, Circuit-level stress and gate dielectric degradation in MOSFETs, oral presentation and poster at the 2003 Micron Foundation Summer Technical Conference, Boise, ID (August 8, 2003). [Awarded Best Poster Award]Southwick III, R.G. *, Betsy Cheek* and William B. Knowlton, Charge pumping techniques for MOS devices, oral presentation and poster at the 2003 Micron Foundation Summer Technical Conference, Boise, ID (August 8, 2003).Cheek, Betsy*, Carrie Lawrence*, Tim Lawrence*, Jose Gomez*, Theodora Caldwell*, Dorian Kiri*, Santosh Kumar, Jake Baker, Amy J. Moll and William B. Knowlton, Gate dielectric degradation effects on nMOS devices and simple IC building blocks (SICBBs), extended abstract accepted for poster session at IEEE/EDS Workshop on Microelectronics and Electron Devices, (October 25, 2002).Lawrence*, C., B. Cheek*, T. Caldwell*, T. Lawrence*, D. Kiri*, S. Kumar, J. Baker, A. J. Moll and W. B. Knowlton, Pulse voltage stressing of ultrathin gate oxides in NMOS devices, poster session at the IEEE International Integrated Reliability Workshop, (October 21-24, 2002).Cheek*, B., C. Lawrence, T. Lawrence*, T. Caldwell*, D. Kiri*, S. Kumar, J. Baker, A. J. Moll and W. B. Knowlton, Circuit level reliability of ultrathin gate oxides for SICBBs: Preliminary study concentrated on the effect of stress on the NMOSFET of an inverter, poster session at the IEEE International Integrated Reliability Workshop, (October 21-24, 2002).Knowlton, William B., Research efforts in materials science related areas at Boise State University, invited talk at Idaho State University-Idaho Accelerator Center Workshop on "Application of Novel X-ray sources to Biological and Materials Science" (September 5 & 6, 2002).

5

OutlineOutline

Statement of Work for Gate Oxide Reliability

Measurement Techniques Developed

Circuits Studied Relative to Gate Oxide Thickness

Alternative Gate Dielectrics

Future Work

6

Statement of WorkStatement of Work

Focus: Gate dielectric/oxide (SiO2) degradation by EM radiation in MOSFETs & Effects on ICs ◘ Determine degradation mechanisms in gate dielectric due to

EM radiation◘ Mimic EM radiation-induced degradation in gate oxides

using DC techniques◘ Determine how gate oxide degradation mechanisms affect

simple integrated circuit building blocksInvertersLogic gates: NAND & NOR

To do this: Developed 2 - test and measurement techniques◘◘ 1) Multi1) Multi--Waveform Pulse Voltage StressingWaveform Pulse Voltage Stressing◘◘ 2) Switch Matrix Technique2) Switch Matrix Technique

7

Techniques for Examining EM Radiation Effects Techniques for Examining EM Radiation Effects on Devices and Circuitson Devices and Circuits

MultiMulti--Waveform Pulse Voltage Stressing (MWPVS)Waveform Pulse Voltage Stressing (MWPVS)

Switch Matrix TechniqueSwitch Matrix Technique

8

Continued size reduction in ICs, leads to:◘ Very close interconnect

proximity

◘ EM radiation will Capacitive Couple to Interconnects

◘ Cause noise spiking

◘ Increase voltage:From: Vcarrier

To: Vcarrier + VEM = Vnoise

V

+ =Vcarrier V EM

t

MultiMulti--waveform Pulse Voltage Stressing (MWPVS)waveform Pulse Voltage Stressing (MWPVS)-- Mimics EM RadiationMimics EM Radiation--IC CouplingIC Coupling

9

Time

Vol

tage

Time

Vol

tage

RVS (ramped voltage stress)◘ DC – difficult to extract time dependency

CVS (constant voltage stress)◘ DC - NOT typical for digital circuit operation

PVS (pulse voltage stress)◘ Better mimics digital device behavior

MWPVSMWPVS◘ Represents circuit operation with noise source

such as EM radiation

Reliability Test MethodsReliability Test Methods

Agilent4156C

O’scope

Probe DeviceDevice

Agilent 81110APulse

Pattern Generator

Ch 1

Ch 2

Time

Vol

tage

10

MWPVS MWPVS -- Experimental ResultsExperimental Results

0.0 -0.5 -1.0 -1.5 -2.010-15

10-13

10-11

10-9

10-7

10-5

10-3

10-1

10-10

10-8

10-6

10-4

10-2

100

102

SILC

Softer SBD

SBD

LHBD

| IG |

(A)

VG (V)

tox = 3.2 nm

Aox = 2.1 x 10-4 cm2

Accumulation

Fresh

| JG | (A

/cm2)

MWPVS

CVS

Finding: Degradation mechanisms induced by either EM-like pulse voltage stressing or DC stress the same.

Pre- and post- MWPVS IGATE-VGATE results:◘ Degradation mechanisms observed

SILC (Stress Induced Leakage Current)SBD and Softer SBD (Soft Breakdown) LHBD (Limited Hard Breakdown)HBD (Hard Breakdown)

CVS

11

MWPVS MWPVS vsvs CVSCVS

Weibull plots indicate device lifetime decreases by orders of magnitudes when compared to preliminary CVS data

MWPVS Weibull Plots

Similar results for lower frequencies

12

Preliminary Noise Model for MWPVSPreliminary Noise Model for MWPVS

Initial data indicates that increasing the noise signal decreases device lifetime exponentially†

◘ d, constant proportional to DCBASE of carrier signal

◘ d’, constant proportional to DCSPIKEof noise signal

◘ c, voltage accelerator factor◘ dV, noise amplitude

Preliminary noise model for a spike voltage with a DCSPIKE of 20%

†Lawrence, C.E., et al, “Gate Dielectric Degradation Effects on nMOS Devices Using a Noise Model Approach”, in Proc. of the 15th Biennial IEEE UGIM Symposium, June 30 - July 2, 2003, pp.263-266.

( )

,

1 ' c V dVcV

bd noise

d e d et

+≈ ⋅ + ⋅

,

,

bd bd noisebd

bd noise

bd BASE bd

t tt

tt T DC P

−Δ =

= ⋅ ⋅

0 1 2 3 4 5 60

200400600800

1000120014001600

Δ t bd

/ t bd

, noi

se

| Noise Voltage | (V)

EM Radiation can cause significant reduction in lifetime (over 3 orders of magnitude)

13

Designed a MWPVS technique to simulate effects of EM radiation on MOSFETs

Reliability IssuesConstructive Interference occurs due Superposition of waveforms

o Electromagnetic radiation

o Capacitive Coupling

o Mixed Signals

Device lifetime shorter for EM-like radiation than PVS or CVS

ConclusionsConclusions

Data corresponds to the noise modelData corresponds to the noise model: Device lifetime : Device lifetime exponentially decreases with increase in noise voltageexponentially decreases with increase in noise voltage

14

Techniques for Examining EM Radiation Effects Techniques for Examining EM Radiation Effects on Devices and Circuitson Devices and Circuits

MultiMulti--Waveform Pulse Voltage Stressing (MWPVS)Waveform Pulse Voltage Stressing (MWPVS)

Switch Matrix Technique (SMT)Switch Matrix Technique (SMT)

15

Gate Oxide Reliability in Simple IC Building BlocksGate Oxide Reliability in Simple IC Building Blocks((SICBBsSICBBs))

11 J.H. Stathis, R. Rodriguez, B.P. Linder, J.H. Stathis, R. Rodriguez, B.P. Linder, ““Circuit Implications of Gate Oxide Circuit Implications of Gate Oxide Breakdown,Breakdown,”” Proceedings Proceedings WoDIMWoDIM, 2002., 2002.

Only one other group examining SICBB reliabilityThey can only perform VTC – a DC technique

• They did not examine time domain• Cannot determine oxide degradation mechanism• Why? Because they cannot examine individual MOSFETS

Inverter

16

Switch Matrix Technique (SMT)Switch Matrix Technique (SMT)

Reliability studies - focus mainly on MOSFETS and large-scale ICs.

Degradation effects in MOSFETs cannot be directly correlated to gate oxide degradation in ICs

ANSWER: We developed a method that can isolate MOSFET from IC to:◘ examine EM-radiation-like oxide degradation in individual MOSFETs◘ Induce EM-radiation-like oxide degradation in individual MOSFETs or circuit

METHOD: Switch Matrix Technique (SMT) enables reliability studies at the simple integrated circuit building block (SICBBSICBB) level.1

Using SMT, reliability studies have focused on the following SICBBsSICBBs:1,2

◘ Inverter (tox: 3.2 and 2 nm)◘ Transmission Gate (TG not shown)◘ NAND (tox: 2 nm)◘ NOR (tox: 2 nm)

1B. Cheek, et al., "Investigation of circuit-level oxide degradation and its effect on CMOS inverter operation and MOSFET characteristics," in 2004 Proc. IEEE IRPS, pp. 110-116.2M. L. Ogas, et al., "Degradation of risetime in NAND gates using 2nm gate dielectrics," in 2005 Proc. IEEE IIRW, pp. 63-66.

17

Switch Matrix Technique (SMT) Switch Matrix Technique (SMT) -- SystemSystem

Agilent 41501B SMU and Pulse Generator

Unit

Agilent 4156C Precision Semiconductor Parameter

Analyzer

Agilent E5250A Low Leakage Switch Matrix

HP 4284A LCR Meter

Agilent Infinium 54832D 1GHz Oscilloscope

Micromanipulator Probe Station:•8 Cascade MicrotechMicromanipulators•Faraday Cage

Metrics ICS Software

Micromanipulator Probe Station:•8 Cascade MicrotechMicromanipulators•Faraday Cage

High Resolution: High Resolution: femtoamperefemtoampere and microvoltand microvolt

18

Switch Matrix Technique (SMT) Switch Matrix Technique (SMT) -- Experimental Experimental SetupSetup

Station #1Station #1 Station #2Station #2

Switch Matrix TechniqueSwitch Matrix Technique

SICBB CircuitVDD

Output

Input A

Input B

N

P

N

P

19

Switch Matrix Technique (SMT) Switch Matrix Technique (SMT) --Addressing Load Capacitance Addressing Load Capacitance

Δtr is within standard deviation when comparing wire bonded NAND circuit and SMT NAND circuit.

0 250.0p 500.0p 750.0p 1.0n0

20

40

60

80

100150 nm CMOS Process

Δ t r P

erce

nt

Load Capacitance (F)

tr NOR

Wire Bonded SMT

Simulation of NOR circuit shows when Cload is decreased, Δtrpercent remains constant.

SMT is a viable technique

Experimental Simulation

0

0.2

0.4

0.6

0.8

1.0

Input A Input B Fresh LLDA

90%

10%

OutputV OU

T (V)

Time (a.u.)

IncreasedDegradation

tr

1R. J. Baker, "CMOS: Circuit design, layout, and simulation," 2 ed: IEEE Press Wiley-Interscience, 2005, pp 278, 154-158.

20

SMT Experimental ProcedureSMT Experimental Procedure

Transistor-levelStress applied

to the gate terminal of the device

Before stress measurementsCircuit: VTC, V-t, IIN-VIN

MOSFET: IG-VG, ID-VD, ID-VG

Device Or

Circuit?

After stress measurementsSICBB Circuit: VTC, V-t, IIN-VIN

MOSFET: IG-VG, ID-VD, ID-VG

Circuit-level+RVS applied to the input

node of the circuit

Data Analysis & Parameter ExtractionCircuit: IIN, VOH, VOL, VSP, VOut,MAX, VOut,MIN, tr, tf

MOSFET: IG, IOn, IOff, Vth, gm, S

21

SMT SMT –– SICBBsSICBBs StudiedStudied

- +VIN VOUT

VDD

SICBB: 3.2nm InverterCircuit Level Degradation

GND

SICBB: 2nm InverterDevice Level Degradation

SICBB: 2nm NAND GateDevice Level Degradation

SICBB: 2nm NOR GateDevice Level Degradation

- +VIN VOUT

VDD

GND

Input A

Input B

VDD

Output

OUT

Input A =

Input B = VDD

VDD VDD

22

0

0.3

0.6

0.9

1.2

1.5

1.8

tf increase

tr increase

Time (a.u.)

VO

UT (

V)

ΔVOut,MIN

ΔVOut,MAXdecrease

63%

increase ~ 24%

I II

3.2nm Inverter VTC and V3.2nm Inverter VTC and V--t Responset Response

0 0.3 0.6 0.9 1.2 1.5 1.80

0.3

0.6

0.9

1.2

1.5

1.8

decrease ~ 1%

ΔVOL

VIN (V)

ΔVSP ~ 11 %

increase ~ 24 % VO

UT (

V)

Fresh

ΔVOH Fresh+ LHBD (P,N )

HBD (P,N)

x LHBD (P,N )

Increasing Degradation

x HBD (P), LHBD (N)

Time-domain degradationmore significant!ΔVOH << ΔVOut,MAX

ΔVOL = ΔVOut,MIN

23

2nm pMOSFET Gate Oxide Degradation (I2nm pMOSFET Gate Oxide Degradation (IGG--VVGG)

Observed gate leakage current increase (2.0 nm)◘ Accumulation mode ~ 2 to 3 orders of magnitude◘ Inversion mode < 1 order of magnitude

CVS IGate vs VGate

24

2nm Inverter VTC and V2nm Inverter VTC and V--t Responset Response

1R. J. Baker, H. W. Li, and D. E. Boyce, "CMOS: Circuit design, layout, and simulation," IEEE Press, pp. 201-228, 1998.

Fresh E level degradation:◙ Δ VSP ~8% shift left1

◙ Output behavior transitions from 1 to 0

Fresh E level degradation Δ rise time1 ~36% to 62%

DC Operation AC Operation

Time (a.u.)

25

• Significant reduction in NAND circuit performance

OUTInput A =

Input B = VDD

VDD VDDDegraded PMOS Position

┼R. J. Baker, "CMOS: Circuit design, layout, and simulation," 2 ed: IEEE Press Wiley-Interscience, pp 317-318, 2005.

ΔVSP ≈ 9.0% left, ± 1.2%Δtr ≈ +64.2%, ± 17.5%

%10%90 tttr −=┼

0 0.2 0.4 0.6 0.8 1.0

0

0.2

0.4

0.6

0.8

1.0

Knowlton's GroupBoise State University

August 2, 2005W3C4R2 W4C4R7

NAND1BVDD

V OU

T (V)

VIN (V)

Inc.Degradation

Fresh

VSP

DC Operation AC Operation

Setting 1-3

2nm NAND Gate VTC and V2nm NAND Gate VTC and V--t Responset Response

26

2nm NOR Gate V2nm NOR Gate V--t Responset Response

• Approximately ½ Δtr,NAND• Significant reduction in NOR circuit performance

0

0.2

0.4

0.6

0.8

1.0

Input A Input B Fresh LLDA

IncreasedDegradation

V OU

T (V)

Time (a.u.)

tr

Output10%

90%

Δtr ≈ +31% ± 6%

VDD

OUTPUT

0V

AC Operation

27

NAND Gate NAND Gate -- Potential Circuit FailurePotential Circuit Failure

Want: tdelay < tsetup

If tdelay ↑ then output becomes:

Idealoutput

Degradedoutput

Resulting problem:• Does data get clocked?• Too much delay fail

Clk

DataIdeal output Degraded output

D

ClkVDD

Q

HighLow

28

SICBB SICBB -- ConclusionsConclusions

Switch Matrix Technique – viable technique◘ Determine degradation in individual devices◘ Ability to connect device degradation to circuit degradation

Gate Oxides: 2.0 nm more susceptible than 3.2 nm to EM-radiation-like degradation◘ SICBB failure may result at a fairly low level degradation

VTC measurements may show negligible inverter degradation ◘ Suggests Oxide degradation effects in SICBBs are not a reliability issue

Decrease in logic gate performance, particularly in time domain, directly related to:

Observed degradation in Δtr of the NOR gate is about half of that observed in NAND gates

CHr Rt Δ∝ΔCH

DRIVE RI 1

∝DRIVEIΔ

29

High k Dielectrics to Replace SiOHigh k Dielectrics to Replace SiO22

Motivation

M. Houssa et al., Materials Science and Engineering R, vol. 51, pp. 37-85, 2006.

Leading high k candidate: HfO2

Dielectric Constant: ~25

30

High k Dielectrics High k Dielectrics –– HfOHfO22

Many Issues with HfO2: ◘ Prompted by SiOx interfacial layer (IL)◘ Larger number of defects◘ Reliability Assessment of IL needed

R. G. Southwick III and W. B. Knowlton, "Stacked dual oxide MOS energy band diagram visual representation program (IRW Student Paper)," IEEE

Transactions on Device and Materials Reliability, accepted for publication, 2006.

31

HfOHfO22 –– Preliminary RVS Reliability TestingPreliminary RVS Reliability Testing

Time-zero dielectric breakdown studies

-2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5 -6.0 -6.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

tox,HfO2

3nm 5nm 7nm 10nm 12nm 15nm

ln[-

ln[1

-F]]

EHfO2 (MV/cm)

solid = thermal SiO2 dashed/open = chemical SiO2nMOSFETW/L=10μm/0.2μmtox,SiO2

= 1.1nm

HfO2

Thickness

-0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 -4.5 -5.0 -5.5

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

tox,HfO2

3nm 5nm 7nm 10nm 12nm 15nm

ln[-

ln[1

-F]]

VHfO2 (V)

HfO2

Thickness

nMOSFETW/L=10μm/0.2μmtox,SiO

2

= 1.1nm

solid = thermal SiO2 dashed/open = chemical SiO

2

-8 -10 -12 -14

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

-16 -18 -20 -22

ln[-

ln[1

-F]]

ESiO2 (MV/cm)

tox,HfO2

3nm 5nm 7nm 10nm 12nm 15nm

n = chemical SiO2nMOSFETW/L=10μm/0.2μmtox,SiO2

= 1.1nm

solid = thermal SiO2 dashed/ope

HfO2

Thickness

-8 -10 -12 -14 -16 -18 -20 -22

-2.0

-1.5

-1.0

-0.5

0.0

0.5

1.0

ln[-

ln[1

-F]]

ESiO2 (MV/cm)

tox,HfO2

3nm 5nm 7nm 10nm 12nm 15nm

nMOSFETW/L=10μm/0.2μmtox,SiO

2

= 1.1nm

solid = thermal SiO2 dashed/open = chemical SiO2

HfO2

Thickness

32

Future WorkFuture Work: : Will useWill useVariable Temperature Variable Temperature ProbestationProbestation

• Custom Design (3+ years in design & development)

• Temp. RangeTemp. Range:: 5.5 – 450 K;• System PressureSystem Pressure: ~10-6 Torr

Keithley 1 SystemKeithley 1 System

High Resolution: High Resolution: attoampereattoampere and microvoltand microvolt

Keithley 4200 SCSKeithley 4200 SCSKeithley 595 QSCVKeithley 595 QSCV

Agilent 81110A Agilent 81110A 22--channel PPG channel PPG

Keithley707A Keithley707A Switch matrixSwitch matrix

Agilent 4284A LCR meter

33

Future WorkFuture Work: : Will useWill useVariable Temperature Variable Temperature ProbestationProbestation

Cryogenic Temperature Studies◘ SiO2 gate oxides

Device reliabilityCircuit reliability

◘ High dielectric constant reliability

High temp measurements ◘ Thermal stability◘ Reliability: thermal &

voltage acceleration

-1.0 -0.5 0 0.5 1.010-16

10-14

10-12

10-10

VG (V)

| IG |(

A)

Temperature: 5.5 K 50 K 75 K 100 K 150 K 250 K 300 K 350 K

pMOSFET: 10 μm/125 nm tOX = 2.0 nm

Knowlton's GroupBoise State University[LTPS 4.19.06]

inc. temp.inc. temp.

inc. temp.inc. temp.

inc. temp.inc. temp.

0 -0.2 -0.4 -0.6 -0.8 -1.010-13

10-11

10-9

10-7

10-5

10-3

10-1

Temperature: 5.5 K 50 K 75 K 100 K 150 K 250 K 300 K 350 K

Knowlton's GroupBoise State University[LTPS 4.19.06] VD (V)

| ID |

(A)

pMOSFET: 10 μm/125 nm tOX = 2.0 nm VD = -1.0 V

inc.

temp.

inc.

temp.

34

Thank youThank you

Questions?