december, 2004 ecole polytechnique 1 deterministic bist by amiri amir mohammad professor dr....

December, 2004 Ecole Polytechnique 1

Deterministic BIST

ByAmiri Amir Mohammad

Professor Dr. Abdelhakim Khouas

Project Presentation for ELE6306 (Test des Circuits Electronics)

December, 2004 2Ecole Polytechnique

Deterministic BISTDeterministic BIST

Schemes To DiscussSchemes To Discuss I.I. DBIST Schemes Based On Reseeding of DBIST Schemes Based On Reseeding of

LFSRLFSR A. General DBIST SchemeA. General DBIST Scheme B. Implicit Encoding (B. Implicit Encoding (Re-ordering Of Patterns) Re-ordering Of Patterns) C. Implicit Encoding(C. Implicit Encoding(Reordering 2Of Test cubes+ next-Reordering 2Of Test cubes+ next-

bitbit)) II.II. DBIST Schemes Using Internal PatternsDBIST Schemes Using Internal Patterns

A. Bit-Flipping BIST (BFF)A. Bit-Flipping BIST (BFF) B. Improved BFF BIST (SMF)B. Improved BFF BIST (SMF)

III.III. OthersOthers SMF with Multiple ScanSMF with Multiple Scan DBIST with TPIDBIST with TPI


BIST OVERVIEWBIST OVERVIEW

PRPGPRPG Random patterns by LFSR with P(x)Random patterns by LFSR with P(x) Signature Analysis by MISRSignature Analysis by MISR

Large number of Patterns to achieve FCLarge number of Patterns to achieve FC Delay & performance issuesDelay & performance issues

DeterministicDeterministic Complex AlgorithmsComplex Algorithms

Increased Complexity for larger and complex Increased Complexity for larger and complex circuits circuits

Many patterns needed to achieve desired Many patterns needed to achieve desired FCFC

Delay and CostlyDelay and Costly


Deterministic BISTDeterministic BIST What?

Improved BIST scheme Why?

Increase FC in Scan-Based Design Improve test application time and performance

How? Random Patterns + Deterministic

Initially random patterns Generated by Internal LFSR Random resistant faults not detected

Followed by Deterministic Patterns Generated by ATPG Tend to detect hard-to-detect faults (random resistant)


I. DBIST (LFSR Reseeding)I. DBIST (LFSR Reseeding) A. General SchemeA. General Scheme

kk-bit -bit MP-LFSRMP-LFSR ProgrammableProgrammable

22kk distinct patterns distinct patterns xx primitive polynomials primitive polynomials

=> => xx different sequences different sequences of patterns depending on of patterns depending on initial valueinitial value ( (seedseed))

ATPG-generated ATPG-generated deterministic pattern deterministic pattern encoded into encoded into n-bitn-bit word word

qq-bit => Poly. Id (-bit => Poly. Id (22qq PolynomialsPolynomials))

((nn - - qq) bit => LFSR ) bit => LFSR seedseed mm-bit-bit Scan RegisterScan Register


BehaviorBehavior LFSR loaded with LFSR loaded with seedseed value value Poly IDPoly ID identifies FeedBack identifies FeedBack

configurationconfiguration LFSR output bits LFSR output bits seriallyserially shifted shifted

into the Scan Register in into the Scan Register in mm-clocks-clocks Generated pattern Generated pattern consistentconsistent with with

encoded deterministic patternencoded deterministic pattern OriginalOriginal Test Cube - - Test Cube - - 0 0 0 0 - - - - - - 1 1

- - 00 Generated Generated pattern 1 1 pattern 1 1 0 0 0 0

101 101 1 1 0 0 00

I. DBIST (LFSR Reseeding)I. DBIST (LFSR Reseeding)


Encoding Of Test Cubes Size of seed depends on number of carebits in Test

Cube C carebit => specified bit either 1 or 0, not ‘x’ A set of test cubes T = { C1, C2,…, Ci }

S(Ci) = { indice of carebits in test cube Ci } s(Ci) = Number of carebits in test cube Ci smax(T) = maximum number of specified bits in set T Example: T={ C1 , C2 , C3 }

C1 = x1xx0x11xx , C2 = xxx10xx1xx, C3 = 0x1xxxx0xx S(C1) = {2 , 3 , 5 , 8} s(C1)=4 s(C2)=3 s(C3) = 3

smax(T) = 4

ai consistent with ci * ci = ai = (a(0). Mi )1 = (a(0).Mi-k+1 )k

Companion matrix M



Encoding Of Test Cubes (continued..) To encode C into a seed a

Solving s(C) system of non-linear equations in terms of seed variables(a0, …, ak-1) & polynomial coefficients (p0,…,pk-1 ), obtained from *

Two way to solve: 1. Fixing seed variables, and finding the corresponding

P(x) System of non-linear equations (complex to solve)

2. Fixing P(x), and finding seed variables Simpler to solve Less computation time in general If no solution with P1(x), choose next polynomial average # of polynomials analyzed slightly greater

than one



Example: Given P (x) = x4 + x3 + 1 p0=1 p1=0 p2=0 p3=1 C = “x 1xx 0xx 11x” => S(C) = {1,2,5,8} and s(C) = 4. For each index i in S(C), calculate a(0). Mi

i k (M i-k+1 )k ci a(0)k

1 1 M1 1 1 a0

2 2 M1 2 1 a1

5 3 M33 0 a2

8 4 M54 1 a3

(M i-k+1 )k Calculated for each i and k

Subscript k indicates kth position in the set of seed variables a(0)



Only 4-bit encoding for 10 bit test cube (4 + q)-bit stored in Memory



General Scheme Efficient Encoding Probabilistic Analysis show Very high

probability of successfull encoding with s + 4 bits ( 16 polynomial LFSR )

Area Overhead N Patterns => N x (s + q) bits of storage Control Logic For configuration

Optimization possible in terms of storage area



Modified Reseeding Scheme

Re-ordering of Test Cubes

Reduced Storage Size No storage for poly

id Periodic Operation

Mod-p counter p is the period of the

sequence of polynomials (p feedback polynomials)

Addition of Random Patterns to complete periods

High Computational Effort

B. Implicit Encoding B. Implicit Encoding Scheme (1)Scheme (1)



B. Implicit Encoding Scheme (1) (Continued..) Periodic Operation Example:

T = {C1, C2, C3, C4} & set of Polynomials P(C) where P (Ci) contains all the polynomials that can generate Ci P (C1) = {p1, p4}, P (C2) = P (C3) = {p1, p2, p3, p4} P (C4) = {p2,

p3} p1 and p2 can generate all the patterns

(C1, C2) by p1 ; (C3, C4) by p2

Therefore: ( C1, C2, C3, C4 ) Implies Sequence of Polynomials (p1, p1, p2, p2)

Re-ordering : (p1, p2, p1, p2) => ( C1, C3, C2, C4 ) minimum period 2

adding random patterns to make perfect ordering not necessary (i.e counter can be stopped in last period at any time) Can insert more polynomial from P(Ci ) at the expense of AREA



B. Implicit Encoding Scheme (1) (Continued..) Issue:

achieve a re-ordering of the polynomials such that all the test cubes are covered, and so by having a sequence of polynomials with minimum period

Therefore: Need An Algorithm to reduce the list of test cubes generated by each polynomial and hence reduce period

TestCube Compaction To improve time of test application and the efficiency of

encoding Techniques

Simplification : Removal of Ci from T if Ci is a subsets of Cj Merging : consistent test cubes combined such that

s(mrg(C1C2…Ci)) ≤ s(T) is met. Concatenation : Ci&Cj&…&Cz if s(concat(..)) ≤ s(T)



B. Implicit Encoding Scheme (1) B. Implicit Encoding Scheme (1) ((Continued..Continued..)) TestCube CompactionTestCube Compaction (Example): (Example): SimplificationSimplification And And MergingMerging



B. Implicit Encoding Scheme (1) B. Implicit Encoding Scheme (1) (Continued..)(Continued..) TestCube CompactionTestCube Compaction ( (Example..Example..):): ConcatenationConcatenation

Only Only 3 encoding3 encoding needed as opposed to needed as opposed to 44. . Therefore, Therefore, Reduced EncodingReduced Encoding and and

consequently consequently improved time of test improved time of test applicationapplication can be obtained can be obtained



ModifiedModified Reseeding Reseeding SchemeScheme

Re-orderingRe-ordering of Test of Test CubesCubes

Reduced StorageReduced Storage Size Size SeedSeed grouping grouping StorageStorage required for required for

Next-bitNext-bit q-bit counterq-bit counter Each state of Counter Each state of Counter

correponds to a correponds to a feedback feedback configurationconfiguration

No BalancingNo Balancing needed needed in the number of in the number of seedsseeds

(s(smaxmax + 1) x N + 1) x N storage storage

for for N patternsN patterns

B. Implicit Encoding B. Implicit Encoding Scheme (2)Scheme (2)



A. Bit Flipping BIST (BFF) (A. Bit Flipping BIST (BFF) (Continued..Continued..))

Pattern mappingPattern mapping Useless Useless

randomrandom patterns patterns converted converted intointo deterministicdeterministic

BFFBFF block is block is combinationalcombinational and and responsible to responsible to flipflip an an outputoutput bit of LFSR at bit of LFSR at particular particular states of LFSRstates of LFSR

II. DBIST Scheme Using Internal II. DBIST Scheme Using Internal PatternsPatterns


EfficientEfficient Mapping Mapping PPrr and and PPdd with with minimumminimum humming distancehumming distance MinimumMinimum costcost (least number of (least number of mintermsminterms) )

RandomRandom Pattern Pattern PrPr PrPr = f ( = f ( LFSRLFSR states states )) On-setOn-set((PrPr): Modifiable bits): Modifiable bits Off-setOff-set((PrPr): fixed bits (consistent with ): fixed bits (consistent with PdPd ) ) Fix-setFix-set: : On-, Off-, Fix-setsOn-, Off-, Fix-sets containcontain LFSRLFSR states states {s{s00, s, s11, …, s , …, s k-1k-1}}

A. Bit Flipping BIST (BFF) A. Bit Flipping BIST (BFF) ((Continued..Continued..))



BFF function Constructed iteratively starting

with BFF0 ending with BFFR in R iterations

At each iteration r ( 0 ≤ r ≤ R )

New Pd embeded in BFF More Hard-to-detect faults

coverd New set of Hard-to-detect

faults F identified Final BFFR covers all faults Fix0 set of LFSR states,

whose random patterns detect some faults




ExampleExample: : 3-bit3-bit LFSR, LFSR, 5-bit5-bit Scan Register, Scan Register, FF = { = {ff11, f, f22, , ff33, f, f44, f, f55}, }, primitiveprimitive P (x)P (x) generating generating ss00-s-s66 as below. as below.

s0s0 010100

s1s1 000011

s2s2 101000

s3s3 111100

s4s4 111111

s5s5 010111

s6s6 101011

s7 = s0s7 = s0

……010100

……

## PatterPatternn

LFSR statesLFSR states

11 0100101001 s0, s1, s2, s3, s0, s1, s2, s3, s4s4

22 1111010010 s5, s6s5, s6, s0, s1, , s0, s1, s2s2

33 0011111100 s3s3, s4, s5,, s4, s5, s6s6, , s0s0

44 1001110011 s1, s2, s3, s4, s1, s2, s3, s4, s5s5

55 1010010100 s6, s0, s1, s2, s6, s0, s1, s2, s3s3

Assume P1 = 11xxx and P2 = 0xx1x Covering f1, f2, f3

Fix1={s5, s6}Fix2={s3, s6}and Fix0 = Union(Fix1, Fix2}

= {s3 , s5 , s6 }

BFFBFF00 = Ø and Fix0 = {s3 , s5 , s6 }

A determinstic pattern Pd = 11 x 01 covering f4, f5

Hence, need to map Pd onto a Pr in the list




Example (cont..):

on-set and off-set for all Pr w.r.t (Pd = 11 x 01)

Candidates for mapping Pd : P1, P2, P4. Why not P3, P5 ?

P1 chosen, because minimum cost (humming distance + least # of minterms )

New BFF = Union {BFF0, on-set (Pd, P1)} = { s0 }

New FIX = FIX1 = Union {FIX0, on-set (Pd , P1), off-set (Pd , P1)} = {s0, s1, s3, s4, s5, s6}




MinimizingMinimizing BFFBFF by considering by considering s0 s0 ((on-set elementson-set elements) ) only only

NewNew LFSR patterns LFSR patterns =>=> PPdd = = 11 x 01

P1 = 11xxx P2 = 0xx1x

Randomly modified




ExtensionExtension of of BFFBFF ImprovesImproves Area Area

OverheadOverhead AutocorrelationAutocorrelation

between between randomrandom patternspatterns

1111- 1111- 00111-1111-10011-1111-11001-1-11111100

SMFSMF = = ff ( ( LFSRLFSR states, states, Bit-counterBit-counter bits, bits, Pattern-counterPattern-counter bits) bits)

SameSame procedure as procedure as BFF to get SMF BFF to get SMF function, function, exceptexcept state state variablesvariables are are differentdifferent

B. Improved BFF (SMF)B. Improved BFF (SMF)



ExampleExample: : Given Given 2-bit2-bit LFSR with LFSR with P(x)P(x) with states as with states as below, test length below, test length 66, , 5-bit5-bit Scan Register, and need to Scan Register, and need to generate generate PPd1d1 = “00010 = “00010 , , PPd2d2 = “00011 = “00011

Looking at the tableLooking at the table Minimum of Minimum of 2 bits2 bits need to be modified for a need to be modified for a

chosen chosen PrPr

B. Improved BFF (SMF) B. Improved BFF (SMF) (continued..)(continued..)



ExampleExample (continued.. )(continued.. ) PPd1d1, , PPd2d2 are similar are similar PPd1d1 maps onto maps onto PP11 (minimum cost)(minimum cost)

On1 ( Pd1 , P1 ) = { 000 000 01, 010 000 01}

Off1 ( Pd1 , P1 ) = { 001 000 10, 011 000 01, 100 000 10}

logic minimization similar to logic minimization similar to BFFBFF

SMFSMF11 = {xx= {xx00 xxx x xxx x11}} coveringcovering all terms of all terms of On1 ( Pd1 , P1 ) but but nonenone of of Off1

( Pd1 , P1 ) Fix1 = Union { On1 ( Pd1 , P1 ) , Off1 ( Pd1 , P1 ) }

To map To map PPd2d2, , repeated repeated P1 ( (PP44) is the ) is the candidatecandidate




SMF1::

With the new table, only 1-bit modification possible for mapping Pd2 On2( Pd2 , P4) = {100 011 10} Off 2(Pd2 , P4) = {000 011 01, 001 01110, 010 011 11, 011 011

01} and FIX2 = Union { Fix1, Off 2(Pd2 , P4) , On2( Pd2 , P4) } SMF2= {xx0 xxx x1, xx0 xx1 xx} = b0. (p0 + t0)




Pd1 and Pd2 mapped efficiently with only two minterms

Original

Pattern

SMF1 SMF2

10110 can1

00010 00010

11011 01010 01110

01101 01000 01000

10110 00010 can2

00011

11011 01010 01010

01101 01000 11000

SMF2:




High FC compared to PRPG for

Less Area than the 32-bit register used for PRPG for the same FC

Less Area than BOTH (BFF and General)

Efficiency of the SMF over PRPG

B. Improved BFF (SMF) (continued..)B. Improved BFF (SMF) (continued..)


CircuitCircuit RandoRandom FCm FC

SMF SMF FCFC

Area (% Area (% of of

LFSR-LFSR-32)32)

s838s838 66.92%66.92% 95.92%95.92% 41.6%41.6%

s9234s9234 90.63%90.63% 91.51%91.51% 66.4%66.4%

s13207s13207 93.83%93.83% 96.38%96.38% 43.8%43.8%

s15850s15850 94.58%94.58% 97.25%97.25% 43.8%43.8%

s38417s38417 93.41%93.41% 93.62%93.62% 46.9%46.9%

s38584s38584 98.71%98.71% 98.93%98.93% 43.8%43.8%

s2670s2670 88.26%88.26% 89.19%89.19% 76.0%76.0%

s7552s7552 96.29%96.29% 97.05%97.05% 78.2%78.2%

CircuitCircuit S-path S-path length(length(

n)n)

ReseedReseeding ing

[mm2][mm2]

BFF BFF [mm2][mm2]

Area Area [mm2][mm2]

s420s420 3434 0.3440.344 0.0630.063 0.0570.057

s641s641 5454 0.3440.344 0.0630.063 0.0520.052

s713s713 5454 0.3440.344 0.0630.063 0.0510.051

s838s838 6666 0.5330.533 0.1000.100 0.0900.090

s953s953 4545 0.3080.308 0.0630.063 0.0500.050

s1196s1196 3232 0.3350.335 0.0670.067 0.0570.057

s1238s1238 3232 0.3320.332 0.0630.063 0.0570.057

s5378s5378 214214 0.4230.423 0.0810.081 0.0780.078

s9234s9234 247247 0.9440.944 0.5440.544 0.4480.448

s3207s3207 700700 0.7300.730 0.1930.193 0.1580.158

s15850s15850 611611 0.9180.918 0.3310.331 0.3270.327

s38417s38417 16641664 1.8961.896 1.7331.733 1.4921.492

s38584s38584 14641464 0.7700.770 0.5770.577 0.2940.294

s2670s2670 157157 0.7340.734 0.2790.279 0.2200.220

s7552s7552 206206 0.9870.987 0.5170.517 0.3840.384


ImprovementImprovement over over single-scan SMFsingle-scan SMF

Breaking one large Breaking one large scan register into scan register into severalseveral scan registers scan registers Reduced time of test

application (less FFs) Similar Synthesis process as

single scan SMF , except at logic minimization step

Patterns feed several scan paths

Pd can map onto any path

SMF with Multiple Scan

III. OthersIII. Others SchemesSchemes


DBIST with TPIDBIST with TPI BFFBFF combinedcombined with with TPITPI ( (Test point Test point

insertioninsertion)) ImprovesImproves

Random testabilityRandom testability Controllability and ObservabilityControllability and Observability

100% FC achieved with less area100% FC achieved with less area

DBIST SchemesDBIST Schemes

III. OthersIII. Others SchemesSchemes


Reseeding of LFSRReseeding of LFSR General DBIST SchemeGeneral DBIST Scheme

High High FCFC Efficient Encoding ( Less computational effort for encoding of Efficient Encoding ( Less computational effort for encoding of

seeds)seeds) Storage Area Overhead (seed + poly id )Storage Area Overhead (seed + poly id )

Implicit Encoding (1)Implicit Encoding (1) High High FCFC Less Storage Area ; Less Storage Area ; mod-pmod-p counter needed counter needed More Computational effort needed for encoding of seedsMore Computational effort needed for encoding of seeds Re-ordering needed + added Random Patterns for balancingRe-ordering needed + added Random Patterns for balancing

Implicit Encoding (2)Implicit Encoding (2) High High FCFC next-bit + p-bit counter (for p polynomials of LFSR)next-bit + p-bit counter (for p polynomials of LFSR) No balancing problem, hence no random patterns need to be No balancing problem, hence no random patterns need to be

addedadded

VI. ConclusionVI. Conclusion DBIST SchemesDBIST Schemes


VI. ConclusionVI. Conclusion

Internal Pattern GenerationInternal Pattern Generation BFFBFF

High High FCFC Pattern MappingPattern Mapping Less Area Overhead (No Storage required)Less Area Overhead (No Storage required) Synthesis processSynthesis process

SMF SMF (single scan design)(single scan design) High High FCFC Pattern MappingPattern Mapping Furthre improve BFF for area overhead ( reduced-Furthre improve BFF for area overhead ( reduced-

size LFSR )size LFSR ) Synthesis ProcessSynthesis Process

SMFSMF with Multiple Scan Register with Multiple Scan Register improved time of test Application improved time of test Application

DBIST SchemesDBIST Schemes

december, 2004 ecole polytechnique 1 deterministic bist by amiri amir mohammad professor dr....

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