de lab11 (1)

LIST OF CONTENT

S.NO. CONTENT PAGE NO.

1. INTRODUCTION

2. SYLLABUS

3. MANUALS OF ALL EXPERIMENTS

INTRODUCTION

Here are some guidelines to help you perform the experiments and to submit the reports:

1. Read all instructions carefully and carry them all out.

2. Ask a demonstrator if you are unsure of anything.

3. Record actual results (comment on them if they are unexpected!)

4. Write up full and suitable conclusions for each experiment.

5. If you have any doubt about the safety of any procedure, contact the demonstrator before hand.

6. THINK about what you are doing!

THE BREADBOARD

The breadboard consists of two terminal strips and two bus strips (often broken in the centre). Each bus strip has two rows of contacts. Each of the two rows of contacts are a node. That is, each contact along a row on a bus strip is connected together (inside the breadboard). Bus strips are used primarily for power supply connections, but are also used for any node requiring a large number of connections. Each terminal strip has 60 rows and 5 columns of contacts on each side of the centre gap. Each row of 5 contacts is a node.

You will build your circuits on the terminal strips by inserting the leads of circuit components into the contact receptacles and making connections with 22-26 gauge wire. There are wire cutter/strippers and a spool of wire in the lab. It is a good practice to wire +5V and 0V power supply connections to separate bus strips.

The 5V supply MUST NOT BE EXCELLED since this will damage the IC’s (Integrated Circuits) used during the experiments. Incorrect connection of power to the ICs could result in them exploding or becoming very hot – with the possible serious injury occuring to the people working on the experiment! Ensure that the power supply polarity and all components and connections are correct before switching on power.

Building the Circuit

Throughout these experiments we will use TTL chips to build circuits. The steps for wiring a circuit should be completed in the order described below:

1. Turn the power (Trainer Kit) off before you build anything!

2. Make sure the power is off before you build anything!

3. Connect the +5V and ground (GND) leads of the power supply to the power and ground bus strips on your breadboard.

4. Plug the chips you will be using into the breadboard. Point all the chips in the same direction with 1 at the upper-left corner. (Pin 1 is often identified by a dot or a notch next to it on the chip package).

5. Connect +5V and GND pins of each chip to the power and ground bus strips on the breadboard.

6. Select a connection on your schematic and place a piece of hook-up wire between corresponding pins of the chips on your breadboard. It is better to make the short connections before the longer ones. Mark each connection on your schematic as you go, so as not to try to make the same connection again at a later stage.

7. Get one of your roup members to check the connections, before you turn the power on.

8. If an error is made and is not spotted before you turn the power on, Turn the power off immediately before you begin the rewire the circuit.

9. At the end of the laboratory session, collect your hook-up wires, chips and all equipment and return them to the demonstrator.

10. Tidy the area that you were working in and leave it in the same condition as it was before you started.

Common Causes of Problems

1. Not connecting the ground and/or power pins for all chips.

2. Not turning on the power supply before checking the operation of the circuit.

3. Leaving out wires.

4. Plugging wires into the wrong holes.

5. Modifying the circuit with the power on.

In all experiments, you will be expected to obtain all instruments, leads, components at the start of the experiment and return them to their proper place after you have finished the experiment. Please inform the demonstrator or technician if you locate faulty equipment. If you damage a chip, inform a demonstrator, don’t put it back in the box of chips for somebody else to use.

Sometimes the chip manufacturer may denote the first pin by a small indented circle above the first pin of the chip. Place your chips in the same direction, to save confusion at a later stage. Remember that you must connect power to the chips to get them to work

SYLLABUS

1. Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the data sheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL ICs.

2. Implementation of the given Boolean function using logic gates in both SOP and POS forms.

3. To verify the operation of a digital comparator.4. Implementation of 4-bit parallel adder using 7483 IC. 5. Implementation of 4x1 multiplexer and 1x4 demultiplexer using

logic gates.6. To design a 16:1 multiplexer using two 8:1 multiplexers.7. Implementation and verification of Decoder and Encoder using

logic gates.8. Verification of state tables of RS, JK, T and D flip-flops using

NAND & NOR gates.9. Design, and verify the 2-bit asynchronous counter.10. Mini Project.

EXPERIMENT NO.1

OBJECTIVE:

Introduction to digital electronics lab- nomenclature of digital ICs, specifications, study of the datasheet, concept of Vcc and ground, verification of the truth tables of logic gates using TTL ICs.

APPARATUS REQUIRED:

S.No. Name of Apparatus

Specifications Qty.

1 7400 TTL NAND Gate 01

2 7408 TTL AND Gate 01

3 7432 TTL OR gate 01

4 7402 TTL NOR Gate 01

5 7404 TTL NOT Gate 01

6 7486 TTL X-OR Gate 01

7 Digital Trainer kit

With Bread board & 5V dc Supply

01

8 Patch Cords As required

THEORY:

IC Family Summary :- Various families of logic ICs exist on the market however the families. Mainly used in digital electronics lab are the TTL and the high speed CMOS families.

Nomenclature of digital IC’s:-

MM74XXXNNRP

MM - Manufacturer

74/54 - Temperature range

XXX - Technology type

NNN - Logic Function

R - Revision

RP - Package Type

Manufacturer --- MM

SN - Texas Instrument, Motorola

DM - National Semiconductor

Temperature Range – 74 or 54

74 - Standard (commercial) 0 to 70ºC

54 - Military -55 to 125ºC

Technology Type XXX

LS – Low power schottky

ALS – Advanced low power schottky

Fv -- Fast TTL

HC -- high speed CMOS

C -- Low speed CMOS

Vcc :- It is supply voltage which operate any instrument without damaged. Vcc terminal is always Red.

Ground :- It is zero potential point, GND terminal is always black.

PROCEDURE:

1. OR Gate

Place the 2 Input OR gate IC 7432 in the bread board.

Connect pin no.14 to Vcc(+5V) and pin no. 7 to ground.

Make the connection for gate 1 connect among pin 1,2 and 3.

Verify the truth table for various combinations of inputs.

2. AND Gate

Place the 2 Input AND gate IC 7408 on the bread board.

Repeat step 2 to 4 as given for OR gate.


3. NOT Gate

Place NOT gate IC 7404 on the bread board.

Connect pin no.14 to Vcc(+5V) and pin no. 7 to ground.

Make the connection for gate 1 connect among pin 1and 2.


4. NAND Gate

Place the 2 Input NAND gate IC 7400 on the bread board.



5. NOR Gate

Place the 2 Input NOR gate IC 7402 on the bread board.


Connect the output to pin no. 3.


6. X-OR Gate

Place the 2 Input X-OR gate IC 7486 on the bread board.


Verify the truth table for various combinations of inputs

Logic Diagram and Truth Tables for various logic gates:

GATE DESCRIPTION TRUTH TABLE

AND GATE The AND gate is a logic gate that gives an output of ‘1’only when all of its inputs are ‘1’. Thus its is ‘0’ whenever atleast one of its input is ‘0’. Mathematically x = A.B

A B X = A . B

0 0 0

0 1 0

1 0 0

1 1 1

OR GATE The OR gate is a logic gate that gives an output of ‘0’only when all of its inputs are ‘0’. Thus its is ‘1’ whenever atleast one of its input is ‘1’. Mathematically x = A+B

A B X = A + B

0 0 0

0 1 1

1 0 1

1 1 1

NOT GATE The OR gate is a logic gate that gives an output that is opposite the state of its input.

A

0 1

1 0

NAND GATE The NAND gate is and AND gate with a NOT gate at its end. Thus for

A B

0 0 1

the same combinations of the inputs, the output of the NAND gate will be opposite that of an AND gate.

0 1 1

1 0 1

1 1 0

NOR GATE The NOR gate is and OR gate with a NOT gate at its end. Thus for the same combinations of the inputs, the output of the NOR gate will be opposite that of an OR gate.

A B

0 0 1

0 1 0

1 0 0

1 1 0

EX-OR GATE The Exclusive OR gate is a logic gate that gives an output of ‘1’ when only one of the input is ‘1’.

A B B

0 0 0

0 1 1

1 0 1

1 1 0

RESULT:

Introduction to digital electronics lab- nomenclature of digital ICs, specifications study of data sheet, concept of Vcc and ground, Verification of truth tables of logic gates using TTL ICs.

PRECAUTIONS:

1. All the ICs should be checked before use the apparatus.

2. All LEDs should be checked.

3. All connections should be tight.

4. Always connect GND first and then connect Vcc.

5. Use suitable type Patch cords.

6. The circuit should be off before change the connections.

After completed experiments switch off the supply of the apparatus.

EXPERIMENTAL QUIZ:

1. What is universal gates?

2. Which gate is generally used to recognize words that have odd number of one’s?

3. How can you inhibit an AND gate?

4. Using only NAND gates, realize the NOR logic function.

EXPERIMENT NO.2

OBJECTIVE:

Implementation of the given Boolean function using logic gates in both SOP and POS forms.

APPARATUS REQUIRED:

S.NO. Name of Apparatus Specifications Quantity

1 SOP & POS kit Using 7404, 7408,7432 01

2 Patch cords As required

THEORY:

Logical functions are generally expressed in terms of logical variables. Values taken on by the logical functions and logical variables are in the binary form. An arbitrary logic function can be expressed in the following forms:

i) Sum of Products (SOP)

ii) Product of Sums (POS)

Sum of Products (SOP):

The logic sum of two or more logical product terms is called a Sum of Products Expression. It is basically an OR operation of AND operated variable such as:

In this approach we simplified the given Boolean expression using basic Boolean laws and theorem. In this approach we assign ‘1’ value to the normal variable and ‘0’ to its complements. Also considered the values to find the expression from any arithmetic or logic calculation.

Product of Sums (POS)

Product of Sums(POS):

A product of Sums expression is a logical product of two or logical sum terms. It is basically an AND operation of OR operated variables such as:

In POS form we simplified the given Boolean expression using basic Boolean laws and theorem. In this approach we assign ‘0’ values to normal variable and ‘1’ to its complements. Also considered the values to find any arithmetic or logic calculation.

PROCEDURE:-

1. Connect the circuit as per circuit diagram.

2. Give the inputs to A & B through switches.

3. Switch ON the experimental board.

4. Observe the output Y on the kit through LEDs.

5. For different combination of inputs observe the output and match them with respective truth table and verify the equations SOP & POS.

TRUTH TABLE FOR SOP

INPUT OUTPUT

A B

0 0 0

0 1 1

1 0 1

1 1 0

TRUTH TABLE FOR POS

INPUT OUTPUT

A B

0 0 1

0 1 0

1 0 0

1 1 1

RESULT:

Study of Boolean function and both equations SOP & POS are verified.

PRECAUTIONS:

1. All ICs should be checked before starting the experiment.

2. All the connection should be tight.

3. Always connect ground first and then connect Vcc.

4. Suitable type wire should be used for different types of circuit.

5. The kit should be off before change the connections.

6. After completed the experiments switch off the supply of the apparatus.

EXPERIMENTAL QUIZ:

1. How do you convert an SOP form to a POS form and vice-versa?

2. Differentiate between minterms and maxterms.

3. What are literals?

EXPERIMENT NO. 3

STUDY OF DIGITAL COMPARATOR

MOTIVATION: In digital circuits, the logic comparison of two quantities is frequently required. The basic function of the combinational circuit-comparator is to compare and determine the relationship of two binary quantities. Magnitude comparators are often used as a part of address decoding circuitry used in computer to select a specific input or output device.

OBJECTIVE: To verify the operation of a digital comparator.

THEORY: A comparator compares the magnitude of two numbers and indicates which one is bigger of the two, or if the two numbers are equal. IC 7485 is a 4-bit comparator which indicates whether A=B, A>B or A<B. In addition, it has three cascading inputs; A<B, A=B, A>B. These inputs allow several comparators to be cascaded for comparison of any number of bits greater than four. The logic symbol and pin diagram of a 4-bit comparator is shown below:-

A0

A1 A <B

A2 A>B

A3 A=B

B0 IC

B1 7485

B2

B3

B1

B2

B3

LOGIC SYMBOL 7485 - PIN DIAGRAM

1 15

14

13

11

12

9

10

2

3

4

G N D

16

7

6

5

B3 A3

B2

A2

B1

A1

B0

A0

A<Bin

A=Bin

A>Bin

8

Vc

c

A<Bout

A=Bout

A>Bout

The general procedure used in a comparator is to check for an inequality in a bit position, starting with MSB. When such an inequality is found, the relationship of the two numbers is established and any other inequalities in lower-order bit positions must be ignored. Thus to determine the inequality of binary numbers A and B, first examine the highest order bit in number. The following conditions are possible:-

If A1 = 1, B1 = 0, number A is greater than number B.

If A1 = 0, B1= 1, number A is less than number B.

If A1 = B1, then examine the lower bit position.

EQUIPMENT REQUIRED: IC 7485, digital trainer kit, connecting wires.

PROCEDURE:

1. Prepare the truth table of comparator .2. Connect pin 16 of IC 7485 to Vcc and pin 8 to ground.3. Connect the terminals A0, A1 and B0, B1 to binary inputs.4. Connect A<Bout, A=Bout and A>Bout at the output.5. Verify the truth table of the comparator for different combinations of A and B.

A1 A0 B1 B0 A<B A=B A>B

0 0 0 0 0 1 0

0 0 0 1 1 0 0

0 0 1 0 1 0 0

0 0 1 1 1 0 0

0 1 0 0 0 0 1

0 1 0 1 0 1 0

0 1 1 0 1 0 0

0 1 1 1 1 0 0

1 0 0 0 0 0 1

1 0 0 1 0 0 1

1 0 1 0 0 1 0

1 0 1 1 1 0 0

1 1 0 0 0 0 1

1 1 0 1 0 0 1

1 1 1 0 0 0 1

1 1 1 1 0 1 0

For K-Maps we are considering A1 as C, A0 as D, B1 as A and B0 as B.

K-Map for A<B K-Map for A=B

K-Map for A>B

RESULT: Operation of Digital Comparator is verified.

POST-EXPERIMENTAL QUIZ:

1. What is the utility of a comparator? 2. Which gate serves as a basic comparator?3. Construct the truth table of a three-bit comparator.4. Draw the combinational circuit of a 3-bit comparator using gates.5. Write down the Boolean expression for A=B, A>B and A<B for the above circuit.

EXPERIMENT NO.4

OBJECTIVE:

Implementation of 4-bit parallel adder using 7483 IC.

APPARATUS REQUIRED :

1. Digital Trainer Kit.2. IC 74833. Connecting Wires

THEORY:

Adder: An adder is a logic circuit which adds two or three bits at a time and give sum and carry as the result.

Parallel Adder :A n-bit parallel adder can be constructed using number of full adders circuit connected in parallel the carry output of each is connected to the carry input of the next higher-order adder.Since all the bits of the augends and addend are fed into the adder circuits simultaneously and the additions in each position are known as parallel adder.

A3 A2 A1 A0 → Augends bitsB3 B2 B1 B0 → Addend bitsS3 S2 S1 S0 → Sum bits

LOGIC DIAGRAM OF BCD ADDER & SUBTRACTOR

Where A0, A1, A2, A3 & B0, B1, B2, B3 are BCD inputs

S0, S1, S2, S3 are Sum outputs.

PIN DIAGRAM OF 7483 IC

PROCEDURE:

1. Connect ground and Vcc to 7483 IC from trainer kit through patch cords.

2. Connect inputs A0,A1,A2,A3 and B0,B1,B2,B3 to logic input switches.

3. Connect carry in from pin no.13 to ground so that carry input(CY1) will be logic ‘0’ state.

4. Connect S0,S1,S2,S3 and carry out(CY0) from pin nos. 9,6,2,15 and 14 to the output display.

5. Verify truth tables for different combinations of inputs.

TRUTH TABLE:

The Truth table operation of the 4-bit Parallel Adder is shown below:

INPUTS OUTPUT

A0 A1 A2 A3 B0 B1 B2 B3 CY1 S0 S1 S2 S3 CY0

0 0 0 1 0 1 0 1 1 1 1 0 0 1

1 0 0 0 1 1 1 0 0 0 0 0 0 1

RESULT: For various combinations of selected input lines, observed the LED output and verified the truth table.

PRECAUTIONS:








1. Draw the block diagram of a full adder as a combination of two half adders.2. Derive the Boolean expressions for the outputs S and Co of a full adder from the truth

table.3. Make the truth table and logic diagram of a half adder.4. Implement a half adder using only NAND gates.5. Implement a full adder using only NOR logic.

EXPERIMENT NO. 5(a)

Implementation of 4x1 multiplexer using logic gates.

MOTIVATION: Multiplexer are complex integrated circuits that find application in combinational system design. These devices significantly reduce IC package count, thereby reducing the system count and improving the system reliability. Thus it is necessary for the designer to become familiar with the functions of these devices.

OBJECTIVE: Implementation of 4x1 multiplexer using logic gates.

EQUIPMENT REQUIRED: Digital trainer kit, AND-7411, OR-7432, NOT-7404 Gate IC, Connecting wires.

THEORY:

Multiplexer: A multiplexer (MUX) is a device that accepts data from one of many input sources for transmission over a common shared line. To achieve this MUX has several data lines and a single output along with data-select inputs, which permit digital data on any of the inputs to be switched to the output line. The logic symbol for a 1 to 4 data selector/multiplexer is shown in Figure:

Data S0

Select S1

D0 Y

D1

Data D2

Inputs D3

The selection lines decide the number of inputs lines of particular multiplexer. If the number of n inputs lines is equal to 2m, then m select lines are required to select one of the n input line.

0

1

0

1

2

3

MUX

Note that if a binary zero appears on the data-select lines then data on input line D0 will appear on the output. Thus, data output Y is equal to D0 if and only if S1=0 and S0=0.

Similarly, the data output is equal to D1, D2 and D3 for , and

respectively. Thus the total multiplexer logic expression, formed from

ORing terms is

The implementation of this equation is as shown in figure:

TRUTH TABLE :

Data Select Input Input Selected

S1 S0

0 0 D0

0 1 D1

1 0 D2

1 1 D3

PROCEDURE:

1. Connections are made as per circuit diagram.

2. Verify the truth table.

3. Also connect Vcc and Ground then performed experiment.

RESULT: Study of 4×1 multiplexer and verified its truth table .

PRECAUTIONS:








1. What is a multiplexer?2. What are the advantages of using multiplexers over gates in order to realize

any function?3. Draw the circuit of full adder using multiplexer.

EXPERIMENT NO. 5(b)

Implementation of 1x4 Demultiplexer using logic gates.

MOTIVATION: To study the working of transmission of multiple user’s data on single line.

OBJECTIVE: Implementation of 1x4 demultiplexer using logic gates.

EQUIPMENT REQUIRED: Digital trainer kit, NAND-7410, NOT-7404 Gate IC, Connecting wires.

THEORY: A Demultiplexer performs the reverse operation; it takes a single input and distributes it over several outputs. So ,a Demultiplexer can be thought of as a “distributor” ,since it transmits the same data to different destinations. Thus Demultiplexer is a 1-to-N(or 2n) device.

Fig. below shows the logic circuitry for a 1-line to 4-line Demultiplexer circuit . The input data line goes to all of the NAND gates.The two select lines S0 and S1 enable only one gate at a time, and the data appearing on the input will pass through the selected gate the associated output line.

The truth table for a 1:4 Demultiplexer is shown below

PROCEDURE:

1. Connect All ICS on the bread board of digital trainer kit.2. Give supply to pin 16 and connect pin 8 to ground.3. Select lines S0, S1 are connected to binary inputs 0/1.4. Connect the data input (1) to any of the multiplexer inputs.5. For various combinations of select input lines, observe the LED output and verify the truth table.

RESULT: Study of 1:4 demultiplexer and verified its truth table.


1) Design the circuit of 1:8 demultiplexer.

EXPERIMENT NO.6

MULTIPLEXER TREE

MOTIVATION: In order to meet the requirement of larger number of inputs, there should be a provision for expansion of the multiplexers. Hence it is essential to get familiar with the design of multiplexer trees or stacks.

OBJECTIVE: To design a 16:1 multiplexer using two 8:1 multiplexers

EQUIPMENT REQUIRED: IC 74151A (2), IC 7432, IC 7404, digital trainer kit, multimeter, wires.

THEORY: A single 8:1 multiplexer IC can handle a maximum of 8 inputs. When the number of inputs is more than 8, a multiplexer tree can be used, also called a multiplexer stack. Fig. 1 shows an arrangement for 16:1 multiplexer using two 8:1 MUX and one 2:1 MUX.

4

1

S1

2:1 MUX

9

D

BS1

Logic 0

C

S2

Data Inputs

14

12

8

Data Inputs

10

13

11

0

15

Y2

Y1

S

Y

S0

3

7

A (MSB)

Logic 0

8:1 MUX

S0

2

6

S2

5

8:1 MUX

Logic 0

Fig.1

If one out of N inputs is to be selected, the number of select inputs required is m where 2 m = N. In

MUX1, one out of 8 inputs is to be selected and the number of select lines is 3. So is the case in MUX2. In MUX3, one out of two inputs is to be selected and the number of select lines is 1. MUX1 selects one out of its 8 inputs (I0 to I7) depending on the address BCD. If BCD is 000, the output of MUX1 will be I0. Similarly MUX2 selects one out of its 8 inputs (I8 to I15) depending on the address BCD. For example, if BCD = 000, output of M2 will be I8. MUX3 selects one out of its two inputs depending on the address A. If A = 0, output of MUX1 will be the final output. If A = 1, output of MUX2 will be the final output. So if ABCD = 0100, the final output will be I4. Another method is shown in fig.2 using two 8:1 MUX and one OR gate.

13

Y212

C

A (MSB)

8:1 MUX

D

14

S1 S0

15

6

S2

5

7

0

2

3

10

Data Inputs

4

B

11

S1

Y1

Data Inputs

7 4 0 4

1 2

8

Y

S2 S0

1

9

1

23

8:1 MUX

Fig.2

If ABCD = 0101, final output will be I5.

If ABCD = 1101, final output will be I13.

PROCEDURE:

1. Connect the circuit as shown in fig.2.2. Switch on the supply +5V.3. Give binary inputs A,B,C,D.4. Observe the output.5. Verify the truth table shown below.

TRUTH TABLE:

INPUTS

A B C D

OUTPUT

Y

0 0 0 0 I0

0 0 0 1 I1

0 0 1 0 I2

0 0 1 1 I3

0 1 0 0 I4

0 1 0 1 I5

0 1 1 0 I6

0 1 1 1 I7

1 0 0 0 I8

1 0 0 1 I9

1 0 1 0 I10

1 0 1 1 I11

1 1 0 0 I12

1 1 0 1 I13

1 1 1 0 I14

1 1 1 1 I15

RESULT: : Study of 16:1 multiplexer using 8:1 multiplexers and verified its truth table.


1. What is a multiplexer tree?2. The Boolean expression for a 4 variable logic function is:

Y= Σ m (0, 2, 6, 8, 9, 11, 13, 15) Implement using a 16:1 MUX.3. Design an XOR gate using one 2:1 MUX.

EXPERIMENT 7

IMPLEMENTATION OF DECODER & ENCODER USING LOGIC GATES

MOTIVATION : Decoder is an important part of Digital Circuit and is used not only in computer systems but also in communication systems. Decoder is used at the receiver to convert the received encoded data back to the original message.

OBJECTIVE : Implementation and verification of decoder and encoder using logic gates.

EQUIPMENT REQUIRED: Digital trainer kit, 7432 IC, 7404 IC, 7411 IC and Connecting wires.

Encoder is used at the starting stage to encode the message into a unique code. Encoder encodes different types of messages into various forms. In Digital Circuits it encodes a decimal value into a binary word. The encoded binary word has number of bits associated with it. The number of bits depends upon the decimal value which is being encoded. For example in case of decimal values ranging from 0 to 7 the number of bits required to encode these values is 3.

TRUTH TABLE OF 4:2 ENCODER

PROCEDURE:

1. Connect the supply from the trainer kit through patch chords, also connect circuit as per circuit diagram.

2. Give the input connections to I0,I1,I2 and I3.3. Observe the output Y0, Y1 on the trainer kit through LED’s.4. For the different combinations of inputs observe the output and match the truth table.

RESULT: Truth tables of Encoder and decoder are verified.

POST-EXPERIMENTAL QUIZ :

1. How decoder is different from demultiplexer?2. Define various types of Encoders.3. How many 2x4 decoders are required to make one 4x16 decoder.4. Convert 2x4 decoder into 1:4 Demultiplexer.

INPUT OUTPUT

I3 I2 I1 I0 Y1 Y0

0 0 0 1 0 0

0 0 1 0 0 1

0 1 0 0 1 0

1 0 0 0 1 1

EXPERIMENT NO.-8

VERIFICATION OF STATE TABLES OF FLIP FLOPS

USING NAND & NOR GATES.

MOTIVATION: The basic building block of a sequential circuit is a flip-flop. Practically, flip flop is the most widely used memory element. Flip-flops are combined together to form counters, shift registers and various memory devices. So, it is necessary to become familiar with their operation.

OBJECTIVE: Verification of state tables of

1) R-S flip-flop2) J-K flip-flop3) T flip-flop4) D flip-flopUsing NAND and NOR gates.

EQUIPMENT REQUIRED: IC 7400 (NAND Gate), IC 7402 (NOR Gate), IC 7408 (AND Gate)

THEORY: : In case of sequential circuits the effect of all previous inputs on the outputs is represented by a state of the circuit. Thus, the output of the circuit at any time depends upon its current state and the input. These also determine the next state of the circuit. The relationship that exists among the inputs, outputs, present states and next states can be specified by either the state table or the state diagram.

State Table

The state table representation of a sequential circuit consists of three sections labeled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state.

FLIP-FLOP: The basic one bit digital memory circuit is known as flip-flop.It can store either 0 or 1. Flip-flops are classifieds according to the number of inputs.

R-S FLIP-FLOP : The circuit is similar to SR latch except enable signal is replaced by clock pulse.

LOGIC DIAGRAM :

CLOCK S R Qn Qn+1 State↑

↑

0

0

0

0

0

1

0

1

Qn

(No Change)↑

↑

0

0

1

0

0

1

0

0

Reset

↑

↑

1

1

0

0

0

1

1

1

Set

↑

↑

1

1

1

1

0

1

X

X

Prohibited State

D FLIP-FLOP: The modified clocked SR flip-flop is known as D-flip-flop.From the truth table of SR flip-flop we see that the output of the SR flip-flop is in unpredictable state when the inputs

are same. In many practical applications, these input conditions are not required. These input conditions can be avoided by making then complement of each other.

J-K FLIP-FLOP: In a RS flip-flop the input R=S=1 leads to an indeterminate output. The RS flip-flop circuit may be rejoined if both inputs are 1 than also the output are complement of each other.

CLOCK J K Qn Qn+1 State↑

↑

0

0

0

0

0

1

0

1

Qn

(No Change)↑

↑

0

0

1

1

0

1

0

0

Reset

↑

↑

1

1

0

0

0

1

1

1

Set

↑

↑

1

1

1

1

0

1

X

X

Qn (toggle)

T FLIP-FLOP: T flip-flop is known as toggle flip-flop. The T flip-flop is modification of the J-K flip-flop. Both the JK inputs of the JK flip-flop are held at logic 1 and the clock signal continuous to change the outputs will simply change state with each rising edge of the clock signal.

TRUTH TABLE:

CLOCK T Qn Qn+1 STATE↑

↑

0

0

0

1

0

1

NC

↑

↑

1

1

0

1

1

0

Toggle

PROCEDURE:

1. Connections are made as per circuit diagram.2. Verify truth-tables for various combinations of input.

RESULT: Study and verified truth-tables of various flip-flops.

PRECAUTIONS:

1. All the IC’s should be checked before use the apparatus.2. All LED’s should be checked.3. All connections should be tight.4. Always connect GROUND first and then Vcc.5. The circuit should be off before change the connections.6. After completing the experiment switch off the supply to apparatus.


1. What is the advantage of JK flip flop over SR flip flop?2. What is the race around condition in flip-flops?3. Convert a JK flip flop into SR flip flop.

EXPERIMENT NO.-9

MOTIVATION: To verify Two bit asynchronous counter using J-K flip flops

OBJECTIVE: Design, and verify the 2-bit asynchronous counter.

THEORY: Counters are the sequential circuits used to count the clock pulses. Counters are

broadly classified as Synchronous and Asynchronous counters. Asynchronous counters are also

known as Ripple counters In case of synchronous counters a single clock is used for all the flip

flops whereas the clock used for asynchronous counter depends on the previous output of flip

flop. Due to this reason the asynchronous counters are slower than synchronous counterpart. The

stages of flip flops depend on the number of states. Ripple counters are deigned by using J-K and

T flip flops. The n bit asynchronous counter uses n flip flops and counts 2n clock pulses.

Q0 Q11 1

CLK

2

4

1

1 6

3

1 5

1 4

PRE

J

C L K

K

CLR

Q

Q

2

4

1

1 6

3

1 5

1 4

PRE

J

C L K

K

CLR

Q

Q

TIMING DIAGRAM OF 2 BIT ASYNCRONOUS COUNTER

EQUIPMENT REQUIRED Dgital trainer kit, J-K-7476 IC, Connecting wires.

PROCEDURE:

1. Connect All ICS on the bread board of digital trainer kit.2. Give supply by connecting the corresponding pins to Vcc and and ground of the flip

flop IC.3. The inputs of both the flip flops are connected to logic high.4. Give clock input from trainer kit to the first flip flop and clock input for the second flip

flop is the output of the first flip flop.5. After the active edge of each clock pulse the state of flip flops changes and thus clock

pulses are counted.

RESULT: 2-bit asynchronous counter is verified.

POST-EXPERIMENTAL QUIZ

Q1). Design a Negative edge triggered MOD-12 Asynchronous Down counter using J-K Flip flops?

de lab11 (1)

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