ddr evolution and memory market trends
DESCRIPTION
DDR Evolution and Memory Market Trends. Bill Gervasi Technology Analyst [email protected]. Topics to Cover. The SDRAM Roadmap DDR-I & DDR-II Comparison Why DDR-I 400 is Boutique Memory Modules Changes. DRAM Evolution. DDR667. Mainstream Memories. 4300MB/s. 5400MB/s. DDR533. - PowerPoint PPT PresentationTRANSCRIPT
DDR Evolution andDDR Evolution andMemory Market TrendsMemory Market Trends
Bill GervasiBill Gervasi
Technology AnalystTechnology Analyst
[email protected]@attbi.com
2
Topics to CoverTopics to Cover
The SDRAM RoadmapThe SDRAM Roadmap DDR-I & DDR-II ComparisonDDR-I & DDR-II Comparison Why DDR-I 400 is BoutiqueWhy DDR-I 400 is Boutique Memory Modules ChangesMemory Modules Changes
3
DRAM EvolutionDRAM Evolution
Simple,incrementalsteps
“DDR I”
“DDR II”
1100MB/s
PC133
DDR2662100MB/s
DDR3332700MB/s
DDR4003200MB/s
1600MB/s
DDR200
“SDR”
DDR5334300MB/s
DDR400?
3200MB/s
MainstreamMemories
DDR667
5400MB/s
Is DDR-I 400 a temporary
blip?
4
Key to System EvolutionKey to System Evolution
Never over-design!Never over-design!
Implement just enough new features to Implement just enough new features to achieve incremental improvementsachieve incremental improvements
Use low cost high volume infrastructureUse low cost high volume infrastructure ProcessesProcesses PackagesPackages Printed circuit boardsPrinted circuit boards
5
Posed To Me at Posed To Me at Platform & JEDEXPlatform & JEDEX
Why will DDR-I at 400 MHz data rate be a Why will DDR-I at 400 MHz data rate be a “boutique” solution?“boutique” solution?
Why will DDR-II at 400 MHz data rate be a Why will DDR-II at 400 MHz data rate be a “mainstream” solution?“mainstream” solution?
The answer is to look at what new is going The answer is to look at what new is going into DDR-IIinto DDR-II
6
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
7
The DDR II FamilyThe DDR II Family
DDR II similarities to DDR I:DDR II similarities to DDR I: Compatible RAS/CAS command set & protocolCompatible RAS/CAS command set & protocol
DDR II differences from DDR I:DDR II differences from DDR I: DDR I = 2.5V, DDR II = 1.8VDDR I = 2.5V, DDR II = 1.8V Prefetch 4Prefetch 4 Differential data strobesDifferential data strobes Improved command bus utilization:Improved command bus utilization:
Write latency as a function of read latencyWrite latency as a function of read latency Additive latency to help fill holesAdditive latency to help fill holes
New FBGA package & memory modulesNew FBGA package & memory modules Tighter package parasiticsTighter package parasitics
8
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
LowerVoltage
9
1.8V Signaling1.8V Signaling2.5V
DDR-II (SSTL_18)
1.60V
0.90V
1.43V
1.07V
1.25V
0V
0.90V1.03V
0.77V0.65V
1.15V
1.8V
VSS
VDDQ
VREF
VIHac
VIHdc
VILdc
VILacVREF
VSS
VDDQ
VIHac
VIHdc
VILdc
VILac
DDR-I(SSTL_2)
10
I/O Voltage Impact on TimingI/O Voltage Impact on Timing
Signal integrity is a serious Signal integrity is a serious challenge at high data rates!!! challenge at high data rates!!! (duh!)(duh!)
Assume 1mV/ps edge slew rateAssume 1mV/ps edge slew rate DDR-I = 700 mV (VDDR-I = 700 mV (VILILVVIHIH) = 700 ps) = 700 ps
DDR-II = 500 mV (VDDR-II = 500 mV (VILILVVIHIH) = 500 ps) = 500 ps
Helps meet the need for speedHelps meet the need for speed
11
1.8V Signaling =1.8V Signaling =Major Power SavingsMajor Power Savings
0123456789
Power Efficiency in MB/s per Watt
PC133 @ 3.3V
DDR533 @ 1.8V
DDR266 @ 2.5V
12
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
Prefetch 4
13
PrefetchPrefetch
Today’s SDRAM architectures assume an Today’s SDRAM architectures assume an inexpensive DRAM core timinginexpensive DRAM core timing
DDR I (DDR200, DDR266, and DDR333) DDR I (DDR200, DDR266, and DDR333) prefetches 2 data bits: increase prefetches 2 data bits: increase performance without increasing core performance without increasing core timing coststiming costs
DDR II (DDR400, DDR533, DDR667) DDR II (DDR400, DDR533, DDR667) prefetches 4 bits internally, but keeps DDR prefetches 4 bits internally, but keeps DDR double pumped I/Odouble pumped I/O
14
Prefetch 2 Versus 4Prefetch 2 Versus 4
CK
READ
Prefetch 2
Prefetch 4
Core access time
Costs $$$Essentially free
data
15
Prefetch Impact on CostPrefetch Impact on Cost
By doubling the prefetch depth, cycle time for column By doubling the prefetch depth, cycle time for column reads & writes relaxed, improving DRAM yieldsreads & writes relaxed, improving DRAM yields
DDR-I
DDR-II
Pre-fetch
2
2
2
4
4
4
266
333
400
400
533
667
7.5 ns
6 ns
5 ns
6 ns
7.5 ns
10 ns
DDR Family
Data Rate
Cycle Time
Starts to get REAL EXPENSIVE!
Comparable to DDR266 in cost
16
DDR-I 400 PrefetchDDR-I 400 Prefetch
DDR-I prefetch of 2 means expensive DDR-I prefetch of 2 means expensive core timingcore timing
Lower yieldsLower yields
Conclusion: DDR-I 400 will maintain Conclusion: DDR-I 400 will maintain a price premium for a long whilea price premium for a long while
17
Why Not Prefetch = 8?Why Not Prefetch = 8?
DIMM width = 64 bitsDIMM width = 64 bits PCs use 64b, servers use 128b (2 PCs use 64b, servers use 128b (2
DIMMs)DIMMs)64 byte prefetch okay for PC, but…64 byte prefetch okay for PC, but…128 byte prefetch for servers wastes 128 byte prefetch for servers wastes
bandwidthbandwidth
DDR-II must service all applications DDR-II must service all applications well to insure maximum volume well to insure maximum volume minimum costminimum cost
18
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
DifferentialStrobe
19
Differential Data StrobeDifferential Data Strobe
Just as DDR added differential clock to SDRJust as DDR added differential clock to SDR DDR II adds differential data strobe to DDR IDDR II adds differential data strobe to DDR I
Transition at the crosspoint of DQS and DQSTransition at the crosspoint of DQS and DQS
Route these signals as a differential pairRoute these signals as a differential pair Common mode noise rejectionCommon mode noise rejection Matched flight timesMatched flight times
20
Differential Data StrobeDifferential Data Strobe
DQShigh time
VREF
DQSlow time
DQS
DQShigh time
VREF
DQSlow time
DQS
Normal balanced signal
Mismatched Rise & Fall signal
Error!
21
Differential Data StrobeDifferential Data Strobe
DQShigh time
VREF
DQSlow time
DQS
DQShigh time
VREF
DQSlow time
DQS
Normal balanced signal
Mismatched Rise & Fall signal
DQS
DQS
Significantly reduced symmetry error
22
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
CommandBus
23
Additive LatencyAdditive Latency
Command slot availability is Command slot availability is disrupted by CAS latency even on disrupted by CAS latency even on seamless read burstsseamless read bursts Sometimes with odd CAS latencies, Sometimes with odd CAS latencies,
sometimes with evensometimes with even These collisions can be avoided by These collisions can be avoided by
shifting READs and WRITEs in the shifting READs and WRITEs in the command streamcommand stream
Additive latency shifts R & W Additive latency shifts R & W commands earlier – applies to bothcommands earlier – applies to both
24
Read LatencyRead Latency
In the past, data access from a READ In the past, data access from a READ command was simply CAS Latencycommand was simply CAS Latency
Combined with Additive Latency, Combined with Additive Latency, ability to order commands betterability to order commands better
25
Read & Additive LatenciesRead & Additive Latencies
CK
ACT RD
CK
ACT RD
CAS Latency
CAS Latency
RL = AL + CL
Additive Latencydata
data
26
Write LatencyWrite Latency
Complex controllers had collisions Complex controllers had collisions between command slots and data bus between command slots and data bus availabilityavailability
These are eliminated in DDR II by setting These are eliminated in DDR II by setting Write Latency = Read Latency – 1Write Latency = Read Latency – 1
Combined with Additive Latency, lots of Combined with Additive Latency, lots of flexibility in ordering commandsflexibility in ordering commands
27
Write & Additive LatenciesWrite & Additive Latencies
CK
ACT WR
CK
ACT WR
WL = RL – 1
CL – 1
WL = AL + CL – 1 = RL – 1
Additive Latency
Additive Latency = 0 data
data
28
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTermination
FBGAPackage
29
Managing PowerManaging Power
(and its relationship to (and its relationship to packaging)packaging)
30
Power = CVPower = CV22f%#f%#
Factors:Factors: Capacitance (C)Capacitance (C) Voltage (V)Voltage (V) Frequency (f)Frequency (f) Duty cycle (%)Duty cycle (%) Power statesPower states
(# circuits in use)(# circuits in use)
Keys to lowpower design:
Reduce C and VMatch f to demandMinimize duty cycleUtilize power states
31
Package Capacitance (pF)Package Capacitance (pF)
Reduced capacitance lowers power, Reduced capacitance lowers power, makes design easiermakes design easier
Input Capacitance
Input/Output Capacitance
Min Max Delta
2.0 3.0 0.25
4.0 5.0 0.50
Input Capacitance
Input/Output Capacitance
1.5 2.5 0.25
3.5 4.5 0.50
TSOP-II Package
FBGA PackageApproximate 10-25% reduction
32
From DDR-I to DDR-IIFrom DDR-I to DDR-II
LowerVoltage Prefetch 4
DifferentialStrobe
CommandBus
FBGAPackage
On-DieTerminationOn-Die
Termination
33
On-Die TerminationOn-Die Termination
Reduces system cost while improving signal Reduces system cost while improving signal integrityintegrity
Data
Controller
VTT =VDDQ 2
DRAM
Data
Controller
DRAM
VDDQ 2VDDQ 2
DDR-I
DDR-II
34
DDR-I 400 IssuesDDR-I 400 Issues
DDR-I 400 systems are hard to DDR-I 400 systems are hard to design robustlydesign robustly
No vendor interoperability No vendor interoperability guaranteesguarantees
DDR-II offers other performance DDR-II offers other performance benefits besides peak data ratebenefits besides peak data rate
DDR-I 400 runs hotDDR-I 400 runs hot Exists because DDR-II is lateExists because DDR-II is late
35
DDR-I 400 ConclusionDDR-I 400 Conclusion
The JEDEC roadmap represents the The JEDEC roadmap represents the industry focus for mainstream industry focus for mainstream productsproductsDDR-I tops out at 333 MHz data rateDDR-I tops out at 333 MHz data rateDDR-II starts at 400 MHz data rateDDR-II starts at 400 MHz data rate
This This DOES NOTDOES NOT mean that DDR-I at mean that DDR-I at 400 MHz data rate will not ship in 400 MHz data rate will not ship in volumevolume
It It DOESDOES mean that there will be price mean that there will be price premiums for this speed binpremiums for this speed bin
36
ModulesModules
37
ModulesModules
DDR-IDDR-I Unbuffered DIMMUnbuffered DIMM Registered DIMMRegistered DIMM SO-DIMMSO-DIMM Micro-DIMMMicro-DIMM
New:New: 32b-DIMM32b-DIMM
DDR-IIDDR-II Unbuffered DIMMUnbuffered DIMM Registered DIMMRegistered DIMM SO-DIMMSO-DIMM Micro-DIMMMicro-DIMM
New:New: Mini-DIMMMini-DIMM
38
Unbuffered & Registered DIMMsUnbuffered & Registered DIMMs
Same physical size: 133 mm (5.25”)Same physical size: 133 mm (5.25”) New socket; more pins, tighter pitchNew socket; more pins, tighter pitch ““Same plane referencing” pinoutSame plane referencing” pinout Target markets unchangedTarget markets unchanged
ServersServers WorkstationsWorkstations Full form factor desktop PCFull form factor desktop PC
39
SO-DIMMSO-DIMM
Same size as before: 67.6 x 31.75 mmSame size as before: 67.6 x 31.75 mm Same 200 pin socket as beforeSame 200 pin socket as before
Uses 1.8V key positionUses 1.8V key position
No longer supports x72 (ECC) or No longer supports x72 (ECC) or registeredregistered
Target markets change:Target markets change: DDR-I: Mobile, blade serverDDR-I: Mobile, blade server DDR-II: Does not support blade server, DDR-II: Does not support blade server,
small form factor PC possiblesmall form factor PC possible
40
Mini-DIMMMini-DIMM
New to DDR-II… no DDR-I equivalentNew to DDR-II… no DDR-I equivalent Supports x72 (ECC) and registeredSupports x72 (ECC) and registered Larger than SO-DIMM: 82 mmLarger than SO-DIMM: 82 mm New socket requiredNew socket required Target market: blade serverTarget market: blade server Intent is to support stackingIntent is to support stacking
If anyone figures out how to stack BGAIf anyone figures out how to stack BGA
41
Micro-DIMMMicro-DIMM
Same footprint: 45.5 x 30-ish mmSame footprint: 45.5 x 30-ish mm New connectorNew connector
High pin count mezzanine connectorHigh pin count mezzanine connector Two part: one on mobo, one on moduleTwo part: one on mobo, one on module 0.4 mm pitch0.4 mm pitch
42
32b-DIMM32b-DIMM
New to DDR-I… no DDR-II version yetNew to DDR-I… no DDR-II version yet X32 onlyX32 only Ultra low costUltra low cost New connectorNew connector Target market: peripherals, Target market: peripherals,
e.g. printerse.g. printers
43
What Can Change?What Can Change?
44
Small Form Factor PCSmall Form Factor PC
PC memory usage flattened outPC memory usage flattened out SO-DIMM or Mini-DIMM meet the SO-DIMM or Mini-DIMM meet the
needs of most PCsneeds of most PCs DIMM could yield to smaller module DIMM could yield to smaller module
for most desktop PCsfor most desktop PCs Saves ~10,000 mmSaves ~10,000 mm22 board space board space
45
46
North Bridge
Copper
Slots
FlexATX FootprintFlexATX Footprint
With DIMM:
17k mm2
With SO-DIMM:
7k mm2Area saved
~ 60%
47
MobileMobile
DDR-I SO-DIMM had 2X capacity of DDR-I SO-DIMM had 2X capacity of Micro-DIMM (assuming TSOP)Micro-DIMM (assuming TSOP)
DDR-II Micro-DIMM has same DDR-II Micro-DIMM has same capacity as SO-DIMMcapacity as SO-DIMM
Differences:Differences: SO-DIMM supports 1SO-DIMM supports 1stst generation die generation die Micro-DIMM connector change scaryMicro-DIMM connector change scary
However, possible that the Micro-However, possible that the Micro-DIMM displaces the SO-DIMM for all DIMM displaces the SO-DIMM for all mobile marketmobile market
48
Small Module CapacitySmall Module Capacity
49
SummarySummary
DDR-II offers many incremental DDR-II offers many incremental improvements over DDR-Iimprovements over DDR-I Lower voltage, higher prefetch, differential Lower voltage, higher prefetch, differential
strobes, more efficient command bus, higher strobes, more efficient command bus, higher quality package, on-die terminationquality package, on-die termination
DDR-I 400 likely to stay a profitable nicheDDR-I 400 likely to stay a profitable niche New module configurations may impact New module configurations may impact
markets – watch for growth of Micro-markets – watch for growth of Micro-DIMM, possible shrink of SO-DIMM in DIMM, possible shrink of SO-DIMM in DDR-II generationDDR-II generation
50
Thank YouThank You