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TRANSCRIPT
AT91RM9200 Development Kit..............................................................................................
User Guide
AT91RM9200 Development Kit User Guide i
6006A–ATARM–07/03
Table of Contents
Section 1Overview............................................................................................... 1-1
1.1 Scope........................................................................................................1-11.2 Deliverables ..............................................................................................1-11.3 The AT91RM9200 Development Board ....................................................1-1
Section 2Setting Up the AT91RM9200 Development Board ............................... 2-1
2.1 Electrostatic Warning ................................................................................2-12.2 Requirements............................................................................................2-12.3 Powering Up the Board.............................................................................2-12.4 Connecting the Board ...............................................................................2-22.5 Getting Started with the AT91RM9200 .....................................................2-3
Section 3Board Description ................................................................................. 3-1
3.1 AT91RM9200 Processor...........................................................................3-13.2 Memory .....................................................................................................3-23.3 Memory Card ............................................................................................3-23.4 Clock Circuitry and Analog Functions .......................................................3-23.5 Reset Circuitry...........................................................................................3-23.6 Power Supply Circuitry..............................................................................3-23.7 Remote Communication............................................................................3-33.8 User Interface ...........................................................................................3-33.9 Expansion Slots ........................................................................................3-33.10 Debug Interface ........................................................................................3-3
Section 4Configuration Straps ............................................................................. 4-1
4.1 Configuration Straps and Jumper Settings ...............................................4-1
Section 5Schematics ........................................................................................... 5-1
5.1 Schematics ...............................................................................................5-1
Table of Contents
ii AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
AT91RM9200 Development Kit User Guide 1-1
Rev. 6006A–ATARM–07/03
Section 1
Overview
1.1 Scope The AT91RM9200 Development Board enables real-time code development and evalu-ation. It supports the AT91RM9200 ARM9-based 32-bit RISC microcontroller.
This guide focuses on the AT91RM9200 Development Board as an evaluation and dem-onstration platform:
� Section 1 is this overview.
� Section 2 gives information on setting up the installation.
� Section 3 contains a description of the development board.
� Section 4 details the configuration straps.
� Section 5 shows board schematics.
1.2 Deliverables The development kit is delivered with:
� One AC adapter 100 - 240V ~ 1.0A, 50 - 60 Hz
� One modem RS232 cable
� One RJ45 Ethernet crossed cable
� One A/B-type USB cable
� Two power supply cables, one US format, one French format
� One CD-ROM containing summary and full datasheets, datasheets with electrical and mechanical characteristics, application notes and getting started documents for all development boards and AT91 microcontrollers. An AT91 software package with C and assembly listings is also provided. This allows the user to begin evaluating the AT91 ARM® Thumb® 32-bit microcontroller quickly.
1.3 The AT91RM9200 Development Board
The board consists of an AT91RM9200 together with the following:
� 2M bytes of parallel Flash memory
� Four banks of 2M x 32-bit SDRAM
� 128K bytes of EEPROM with two-wire interface access
Overview
1-2 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
� 8M bytes of serial DataFlash®
� Five communication ports (USB host and device, Ethernet, serial and IrDA)
� Graphic controller with output to a standard VGA monitor
� JTAG/ICE, ETM and debug interface
� Expansion connector
Figure 1-1. AT91RM9200 Development Board Block Diagram
Si3044Line Interface
Chipset
RS232Driver
IrDATrasnceiver
SDCardSocket
Smart CardSocket
Oscillator, PLLand Reset
PowerSupply
ADC
USB HostPort
USB DevicePort
DCInput
UserAnalogInputs
SmartMediaSlot
Compact FlashSlot
Flash
FingerChipSocket
Extension Slot
Graphic DisplayController
SDRAM DataFlash EEPROM
LCD PanelSlot
LCD PanelSlot
ClockController
VGA Connector
Buzzer
LED
EthernetPHY
EthernetPort
ICE Debug Port
Trace Port
RS232 Driver
Extension Slot
Extension Slot
Extension Slot
AT91RM9200
16
32
EBI SPI TWI TWI EMAC
JTAG
ETM
DBGU
PIOAPIOBPIOC
SSCSSCTWIUSARTMCI orSPI
USARTNRST
UHP
UDP
AT91RM9200 Development Kit User Guide 2-1
Rev. 6006A–ATARM–07/03
Section 2
Setting Up the AT91RM9200Development Board
2.1 Electrostatic Warning
The AT91RM9200 development board is shipped in protective anti-static packaging.The board must not be subjected to high electrostatic potentials. A grounding strap orsimilar protective device should be worn when handling the board. Avoid touching thecomponent pins or any other metallic element.
2.2 Requirements In order to connect the AT91RM9200 development board, the following elements arerequired:
� The AT91RM9200 development board itself
� Power supply cable capable of supplying 7V to 12V at 1A (not supplied)
2.3 Powering Up the Board
DC power is supplied to the board via the 2.1 mm socket (J1). The polarity of the powersupply is not critical. The minimum voltage required is 7V.
The board has a voltage regulator providing +3.3V. The regulator allows the input volt-age range to be from 7V to 12V.
Setting Up the AT91RM9200 Development Board
2-2 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
2.4 Connecting the Board
� Using the RS232 cable supplied in the AT91RM9200-DK kit, connect the board to your PC via the Serial Debug Port (J23).
� Start the HyperTerminal application:
� In the window Connection Description, enter a name for the connection, e.g., “RM9200K_DBGU”.
� Click on OK.
� In the window Connect To, click on the drop-down list arrow at Connect using:. Select the COM port used.
� Click on OK.
� Set the serial parameters of the COM port as follows:
– Bit rate: 115 kbps
– Data bit: 8
– Parity: NONE
– Stop bit: 1
– Flux control: NONE
� Click on OK.
Setting Up the AT91RM9200 Development Board
AT91RM9200 Development Kit User Guide 2-3
6006A–ATARM–07/03
� The AT91RM9200-DK and your PC are connected, as indicated in the lower left-hand corner of the console and by the title bar.
� Press the RESET button on the board.
� A message is sent from the board to the HyperTerminal console. Note that this message can vary depending on the version of Zooboot.
2.5 Getting Started with the AT91RM9200
The AT91RM9200 Development Kit is delivered with a CD-ROM containing all neces-sary information and step-by-step procedures for working with the most commondevelopment toolchains. Please refer to this CD-ROM, or to the AT91 web site,http://www.atmel.com/products/AT91/, for the most up-to-date information on gettingstarted with the AT91RM9200.
Setting Up the AT91RM9200 Development Board
2-4 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
AT91RM9200 Development Kit User Guide 3-1
Rev. 6006A–ATARM–07/03
Section 3
Board Description
3.1 AT91RM9200 Processor
� Incorporates the ARM920T™ ARM® Thumb® Processor
– 200 MIPS at 180 MHz
– 16-KByte Data Cache, 16-KByte Instruction Cache, Write Buffer
– Memory Management Unit
– In-circuit Emulator including Debug Communication Channel
– Mid-level Implementation Embedded Trace Macrocell
� Additional Embedded Memories
– 16K Bytes of SRAM and 128K Bytes of ROM
� External Bus Interface (EBI)
– Supports SDRAM, Static Memory, Burst Flash, Glueless Connection toCompactFlash®, SmartMedia™ and NAND Flash
� System Peripherals:
– Enhanced Clock Generator and Power Management Controller
– Two On-chip Oscillators with Two PLLs
– Very Slow Clock Operating Mode and Software Power OptimizationCapabilities
– Four Programmable External Clock Signals
– System Timer Including Periodic Interrupt, Watchdog and Second Counter
– Real-time Clock with Alarm Interrupt
– Debug Unit, Two-wire UART and Support for Debug Communication Channel
– Advanced Interrupt Controller with 8-level Priority, Individually MaskableVectored Interrupt Sources, Spurious Interrupt Protected
– Seven External Interrupt Sources and One Fast Interrupt Source
– Four 32-bit PIO Controllers with Up to 122 Programmable I/O Lines, InputChange Interrupt and Open-drain Capability on Each Line
– 20-channel Peripheral Data Controller (DMA)
� Ethernet MAC 10/100 Base-T
� USB 2.0 Full Speed (12 M-bits per second) Host Double Port and Device Port
Board Description
3-2 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
� Multimedia Card Interface (MCI)
� Three Synchronous Serial Controllers (SSC)
� Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)
� Master/Slave Serial Peripheral Interface (SPI)
� Two 3-channel, 16-bit Timer/Counters (TC)
� Two-wire Interface (TWI)
� IEEE 1149.1 JTAG Boundary Scan on All Digital Pins
3.2 Memory � 2-Mbyte parallel Flash memory
� Four banks of 2M x 32-bit SDRAM
� 128-Kbyte EEPROM with 2-wire interface
� 8-Mbyte serial DataFlash
3.3 Memory Card � SD Card/MMC
– Supports MultiMedia and SD Card
– Analog switches provide support for DataFlash Card
� Smart Media® Socket
� CompactFlash® Socket
� Smart Card Interface
3.4 Clock Circuitry and Analog Functions
� 32.768 kHz standard crystal for the AT91RM9200
� 18.432 MHz standard crystal for the AT91RM9200
� 50 MHz CMOS oscillator for the Display Controller
� Temperature sensor
� Analog-to-digital converter
� FingerChip (Socket only)
3.5 Reset Circuitry � Reset Controller
3.6 Power Supply Circuitry
� 3.3V DC/DC converter
� 1.8V DC/DC converter
Board Description
AT91RM9200 Development Kit User Guide 3-3
6006A–ATARM–07/03
3.7 Remote Communication
� Fast Ethernet Physical Layer Single Chip Transceiver
� IrDA Transceiver
� Host Interface via RS-232 DB9 male socket
� Line interface
� Debug Port via RS-232 DB9 connector
� Host and Device USB socket
3.8 User Interface � Graphic Display Controller
� TFT/SNT panel socket
� 15-pin standard socket for an external VGA monitor
� On-board buzzer and one LED managed via general PIO lines
3.9 Expansion Slots � Three expansion slots give access to all the microcontroller’s signals
3.10 Debug Interface � 38-pin trace Port socket
� 20-pin JTAG interface connector
� Serial Debug Unit
Board Description
3-4 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
AT91RM9200 Development Kit User Guide 4-1
Rev. 6006A–ATARM–07/03
Section 4
Configuration Straps
4.1 Configuration Straps and Jumper Settings
Table 4-1 gives details on configuration straps and jumper settings on the AT91RM9200development board and their default settings.
Table 4-1. Configuration Straps and Jumper Settings
DesignationDefault Setting Feature
S1 Closed The earth plane and the GDN potential are connected.
S3 Closed The ETM reset (NSRST) and the System Reset (NRST) are connected.
S4 Closed The PD6/DTXD PIO line is connected to the READY/NBUSY output signal of the SPI DataFlash (MN13).
S5 Opened The Write Protect feature of the SPI DataFlash (MN13) is disabled.
S6 Closed The PA26/TWCK/IRQ1 signal is connected to three remote devices (MN14, MN33, MN34).
S7 Closed The PA25/TWD/IRQ2 signal is connected to three remote devices (MN14, MN33, MN34).
S8 Opened The PA3/NPCS0/IRQ5 output signal is not connected to the NCS of the serial DataFlash (MN13).
S9 Closed The PA5/NPCS2/TXD3 signal is connected to the 10-bit SPI ADC (MN15).
S10 Closed The PC15 I/O line is connected to the 10-bit ADC to read the End Of Conversion event (MN15).
S11 Closed Not Used: The PS2 Controller is not installed.
S12 Closed Not Used: The PS2 Controller is not installed.
S13 Closed The PB12/TF2/ETX2 signal is connected to the NRGDT/FSD output signal of the Line Interface (MN23).
S14 Closed The PB16/RK2/ERX2 signal is connected to the NOFHK input signal of the Line Interface (MN23).
S15 Closed The PB17/RF2/ERXDV signal is connected to the NFSYN input signal of the Line Interface (MN23).
Configuration Straps
4-2 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
S16 Closed The PB13/TK2/ETX3 signal is connected to the SCLK output signal of the Line Interface (MN23).
S17 Closed The PB15/RD2/ERX2 signal is connected to the SDO output signal of the Line Interface (MN23).
S18 Closed Not Used: The Front End AC97 is not installed.
S19 Closed The PA30/DRXD/CTS2 signal is connected to the receive buffer output of the DBGU transceiver (MN26).
S20 Closed The AT91RM9200's PC14 PIO line is connected to the NREADY output signal of the Smart Card Interface (MN29).
S21 Closed The PA17/TXD0/TIOA0 is connected to the DATA input/output signal of the Smart Card Interface (MN29).
S22 Closed The PA22/RXD2/TIOB2 is connected to the RX output signal of the IrDA Transceiver (MN30).
S23 Closed Enables all output signals (DCD1, DSR1, RXD1, CTS1, RI1) of the Transceiver (MN28) used for the RS232 Port COM.
S24 Closed The PD4/ETXEN input line is connected to the USB device socket (J28) to detect a host connection.
S25 Closed The System Reset signal (NRST) is connected to the ICE/JTAG socket (J8, pin 15).
S26 Closed The NCS2 output signal is connected to the display controller (MN32).
S27 Closed The NCS0 output signal is connected to the parallel Flash memory (MN21).
S28 Closed Enables the OE signal from the Atmel FingerChip (MN31). Only the socket is installed.
S29 Closed The SMCS/NCS3 output signal is connected to the bidirectional buffer used by the Smart Media Connector (MN20B).
S30 Closed The PA15/EMDC/TCLK2 output signal is connected to the MDC input signal of the Ethernet Transceiver (MN22).
S31 Closed The PA16/EMDIO/IRQ6 input/output signal is connected to the MDIO input/output signal of the Ethernet Transceiver (MN22).
S32 Closed Disables the power-down mode of the Ethernet Transceiver (MN22).
S33 Closed Not Used: The Front End AC97 is not installed.
S34 Closed Not Used: The Front End AC97 is not installed.
S35 Closed Not Used: The Front End AC97 is not installed.
S36 Closed Connects the system ground to the Ethernet ground.
S37 Closed Not Used: The Front End AC97 is not installed.
Table 4-1. Configuration Straps and Jumper Settings
DesignationDefault Setting Feature
Configuration Straps
AT91RM9200 Development Kit User Guide 4-3
6006A–ATARM–07/03
Note: Shaded cells indicate configuration straps/jumpers with open connections.
Note: Signal names in bold indicate that the function is shared between several sig-nals.
S38 Opened The AT91RM9200 boots up from the parallel Flash Memory.
S39 Closed Enables the use of the User LED (DS5).
S40 Closed Not Used: The Buzzer is not installed.
Table 4-1. Configuration Straps and Jumper Settings
DesignationDefault Setting Feature
Configuration Straps
4-4 AT91RM9200 Development Kit User Guide
6006A–ATARM–07/03
AT91RM9200 Development Kit User Guide 5-1
Rev. 6006A–ATARM–07/03
Section 5
Schematics
5.1 Schematics This section contains the following schematics:
� AT91RM9200 Board Layout - Top View
� AT91RM9200 Board Layout - Bottom View
� Power Supply
� AT91RM9200 Chip
� Buffers
� SDRAM and Flash
� Serial Devices
� PS2 COM Ports
� 3V3 Memory Card
� Ethernet
� DAA
� AC97 Analog Front End
� Serial Interfaces
� Fingerchip
� VGA TFT/CRT Display
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WWW.STUDIEL.fr
PLAN D’EQUIPEMENT
CARTE AT91RM9200-DK
D C B A
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autorisation ecrite expose le contrevenant a des poursuites
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06271 VILLENEUVE-LOUBET
NOTA : COMPOSANTS A MONTER SELON NOMENCLATURE
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NOTA : COMPOSANTS A MONTER SELON NOMENCLATURE
VUE FACE SOUDURES
NOTA : COMPOSANTS A MONTER SELON NOMENCLATURE
VUE FACE SOUDURES
autorisation ecrite expose le contrevenant a des poursuites
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8 8
7 7
6 6
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CC
BB
AA
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PD17
PD10
PD5
PB24
PB19
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PB15
PB0
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A16
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PD15
PB11
D31
D30
D25
D17
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PB21
PB1
D21
PD16
PB17
D28
D15
D3
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PD24
PD14
PD7
PB13
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PD20
PB3
D11
PD8
PD3
PB27
PB18
D27
D18
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PB23
D10
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PB28
PB10
D23
D9
D7
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A8
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PD19
PD12
PD2
PB29
PB5
D22
D14
A22
PB6
D26
D6
D0
A12
A10
PB25
PB14
PB8
D20
A13
A1
PD23
PD13
PD11
PB20
PB9
PB2
D8
A19
VD
DO
SC
PD18
PD1
PB26
A24
D13
D5
A17
A14
A11
A7
A5
PD26
PD21
PB22
PB12
PB4
D19
PD0
PB16
PB7
A23
A0
CF
IOR
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BS
1_
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R1
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PA13
PA7
PA22
PA24PA25
PA4
PA21
PA1
PA31
PA5
PA27
PA8
PA14
PA26
PA16
PA0
PA15
PA18
PA11
PA19
PA17
PA3
PA28PA29PA30
PA12
PA2
PA6
PA20
PA9PA10
PA23
PC3
PC0
PC15PC14
PC11
PC2
PC5
PC12
PC1
PC13
PC6PC10
PC4
PA
31
NR
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PB
[0..
29]
PD
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27]
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A[0
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PA
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15]
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Th
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Wed
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May
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0205
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91
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MM
A
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SET
TEM
PERAT
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SE
NS
OR
BO
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MO
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SE
LEC
T
C46100NF
C63
10µF
C44100NF
C53100NF
C23
10
PF
C39100NF
C2247
0pF
R15
247
K
C61100NF
R9
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MN
5M
AX66
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B4
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C37100NF
C42100NF
C52100NF
C30
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C50100NF
C28
10
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C21
4.7
NF
C58100NF
C31 1
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C45100NF
R5
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R8
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R6
1K96
C56100NF
R13
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C43100NF
C48100NF
C36100NF
R11
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NF
CR
22
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4
1
3
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M92
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NB
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A0
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NB
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A1
M4
A2
M6
A3
M3
A4
N4
A5
N2
A6
L4
A7
P1
A8
N7
A9
N3
A10
M5
A11
P5
A12
P3
A13
P2
A14
N5
A15
T1
BA
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3
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A18
R3
A19
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A20
R4
A21
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PC
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4
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D2
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D3
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D4
M11
D5
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D6
U10
D7
U11
D8
R11
D9
T11
D10
P12
D11
U12
D12
T12
D13
R12
D14
U13
D15
P13
PC
16/D
16U
14
PC
17/D
17R
13
PC
18/D
18U
15
PC
19/D
19T1
4
PC
20/D
20U
16
PC
21/D
21T1
5
PC
22/D
22U
17
PC
23/D
23T1
6
PC
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15
PC
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25T1
7
PC
26/D
26P
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PC
27/D
27P
15
PC
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28N
13
PC
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29R
16
PC
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15
PC
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TC
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TD
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TM
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NTR
ST
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RA
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CA
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8
SD
WE
T8
PCK1/SCK2/PA24B12
IRQ3/TXD2/PA23A12
TIOB2/RXD2/PA22D12
TIOA2/RTS0/PA21D13
TIOB1/CTS0/PA20C12
TIOA1/SCK0/PA19A13
TIOB0/RXD0/PA18C13
TIOA0/TXD0/PA17B13
IRQ6/EMDIO/PA16D14
TCLK2/EMDC/PA15B14
TCLK1/ERXER/PA14A15
TCLK0/ERX1/PA13A17
MCDB3/ERX0/PA12B16
MCDB2/ERXDV/PA11B15
MCDB1/ETX1/PA10D15
MCDB0/ETX0/PA9E14
MCCDB/ETXEN/PA8C16
EXTCK/PCK2/PA7B17
RXD3/NPCS3/PA6E15
TXD3/NPCS2/PA5F16
PCK1/NPCS1/PA4F13
IRQ5/NPCS0/PA3G16
IRQ4/SPCK/PA2G15
PCK0/MOSI/PA1G14
PCK3/MISO/PA0G13
TCLK4/MCCDA/PA28F12
TCLK3/MCCK/PA27G12
IRQ1/TWCK/PA26E12
IRQ2/TWD/PA25E13
TCLK5/MCDA0/PA29E11 CTS2/DRXD/PA30F11 RTS2/DTXD/PA31A10
RTS3/TF0/PB0B10 CTS3/TK0/PB1C10 SCK3/TD0/PB2D10 MCDA1/RD0/PB3E10 MCDA2/RK0/PB4A9 MCDA3/RF0/PB5B9 TIOA3/TF1/PB6C9 TIOB3/TK1/PB7E9 TIOA4/TD1/PB8D9 TIOB4/RD1/PB9A8 TIOA5/RK1/PB10B8 TIOB5/RF1/PB11F9 ETX2/TF2/PB12C8 ETX3/TK2/PB13C7 ETXER/TD2/PB14D7 ERX2/RD2/PB15E7
NR
ST
E1
TS
T0
E4
VDDCORET10
VDDCOREU1
VDDCOREF6
VDDCORET2
VDDCOREL16
VDDCOREC14
PC
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24R
5
CFR
NW
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9/A
25P
7
ERX3/RK2/PB16F7 ERXDV/RF2/PB17A4 ECOL/RI1/PB18B3 RXCK/DTR1/PB19C5 TXD1/PB20A3 RXD1/PB21B4 SCK1/PB22C4 DCD1/PB23F3 CTS1/PB24F5 EF100/DSR1/PB25F4 RTS1/PB26G4 PCK0/PB27G6 FIQ/PB28J5 IRQ0/PB29J6
PD
0/E
TX0
E17
PD
1/E
TX1
F15
PD
2/E
TX2
F14
PD
3/E
TX3
E16
PD
4/E
TXE
ND
17
PD
5/E
TXE
RC
17
PD
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TXD
D16
PD
7/P
CK
0/TS
YN
CD
6
PD
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CK
1/TC
LKA
6
PD
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CK
2/TP
S0
B6
PD
10/P
CK
3/TP
S1
C6
PD
11/T
PS
2A
5
PD
12/T
PK
0B
5
PD
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PK
1B
2
PD
14/T
PK
2C
3
PD
15/T
D0/
TPK
3C
2
PD
16/T
D1/
TPK
4F
1
PD
17/T
D2/
TPK
5G
2
PD
18/N
PC
S1/
TPK
6G
5
PD
19/N
PC
S2/
TPK
7G
1
PD
20/N
PC
S3/
TPK
8H
2
PD
21/R
TS0/
TPK
9H
4
PD
22/R
TS1/
TPK
10H
3
PD
23/R
TS2/
TPK
11H
1
PD
24/R
TS3/
TPK
12J3
PD
25/D
TR1/
TPK
13J1
PD
26/T
PK
14J4
PD
27/T
PK
15J2
JTA
GS
EL
A2
TS
T1
D1
GNDM12
GNDP17
GNDM16
GNDJ12
GNDH16
GNDC15
GNDA14
GNDC11
GNDD11
GNDB7
GNDE8
GNDE6
GNDD4
GNDE3
GNDF2
GNDG3
GNDL1
GNDL5
GNDM2
GNDR1
GNDU2
GNDR2
GNDM7
GNDU5
GNDT9
GNDN12
GNDT13
VDDIOMP16
VDDIOMR17
VDDIOMK16
VDDIOMM1
VDDIOMP4
VDDIOMR6
VDDIOMT5
VDDIOMR10
VDDIOMR14
VDDIOPH14
VDDIOPA16
VDDIOPA11
VDDIOPB11
VDDIOPD8
VDDIOPA7
VDDIOPD5
VDDIOPD2
VDDIOPD3
VDDIOPH5
VDDIOPK4
VDDIOPL6
VD
DP
LLB
H13
GN
DP
LLB
H15
PLL
RC
BF1
7
XO
UT
K17
XIN
J17
VD
DO
SC
J14
GN
DO
SC
J13
XO
UT3
2H
17
XIN
32G
17
VD
DP
LLA
J15
GN
DP
LLA
J16
PLL
RC
AL1
7
SD
A10
N6
SD
CK
EP
9
SD
CK
U7
CFW
E/N
WE
/NW
R0
P8
CFIO
R/N
BS
1/N
WR
1T
7
CFI
OW
/NB
S3/
NW
R3
R8
BFC
S/N
CS
0U
6
SD
CS
/NC
S1
M9
NC
S2
T6
SM
CS
/NC
S3
R7
CFO
E/N
OE
/NR
DN
9
BFCK/PC0M15 SMOE/BFRDY/PC1M14 BFAVD/PC2L14 SMWE/BFBAA/PC3L15 BFOE/PC4K14 BFWE/PC5K13 NWAIT/PC6K15 CFCS/NCS4/PC10L12 CFCE1/NCS5/PC11N16 CFCE2/NCS6/PC12N17 NCS7/PC13M13 HOLD/PC14M17 HOLDA/PC15L13
DD
MK
2D
DP
K5
HD
PA
K1
HD
MA
K3
HD
PB
L2
HD
MB
L3
C19 1
00
NF
C59100NF
C51100NF
C62
10µF
C41100NF
C40100NF
C33
5.6
NF
S38
C49100NF
C64
10
0N
F
C32 1
00
NF
C60100NF
C57100NF
C35100NF
J2
12
R1
59
47
0R
CR
8S
TP
S1L3
0C55100NF
BP
11
42
3
MN
6
MA
X6
39
0XS2
9D4-
T
GN
D1
RE
SE
T2
MR
3
VC
C4
C34
68
0pF
C47100NF
C29 1
00
NF
Y1
18
.43
2MH
z
12
C38100NF
C26 1
00
NF
C27
10
PF
8 8
7 7
6 6
5 5
4 4
3 3
2 2
1 1
DD
CC
BB
AA
D11
D10
D31
D6
D13
D9
D30
D7
D27
D8
D25
D14
D29
D26
D28
D24
D12
D15
D4
D0
D2
D5
D3
D1
D22
D20
D16
D19
D18
D23
D17
D21
NW
R1
NW
R3
NT
RS
TTD
ITM
S
TD
O
TCK
PA
10
PA
21P
A20
PA
6
PA
19
PA
13P
A14
PA
18
PA
26
PA
28
PA
30
PA
2
PA
0
PA
7
PA
22
PA
5
PA
23
PA
25
PA
1
PA
29
PA
12
PA
27
PA
4
PA
9
PA
24
PA
17
PA
8
PA
16P
A15
PA
3
PA
11
PA
4
PA
12
PA
16P
A14
PB
4
PB
0
PB
6
PA
24
PA
0
PA
22P
A20
PA
8
PA
2
PA
18
PB
8
PA
28P
A30
PA
26
PA
6
PB
2
PA
10
PA
5
PA
13
PA
17P
A15
PB
5
PB
1
PB
7
PA
25
PA
1
PA
23P
A21
PA
9
PA
3
PA
19
PB
9
PA
29P
A31
PA
27
PA
7
PB
3
PA
11
DB22
PC14
NWR2
DB16
NCS0
DB30
DB24
PC10PC12
DB20
DB26
NWR0
PC0
PC4
NCS2
DB18
DB28
NRD
PC2
DB23
PC15
NWR3
DB17
DB31
DB25
PC13
DB21
DB27
NWR1
PC1
PC5
NCS3
DB19
DB29
PC3
PD21
PD8
PD7
PD18
PD14
PD17
PD15
PD12
PD24
PD13
PD19
PD27
PD10
PD22
PD23
PD26
PD9
PD20
PD11
PD16
PD25
NR
D
NW
R0
NC
S3
NC
S0
PC6
NT
RS
T
NR
ST
NRST
DB2
4
DB9
DB2
2
DB6
AB
3
AB
13
DB8
DB1
5
AB
22
AB
1
DB2
0
AB
10A
B11
AB
20
DB7
AB
25
DB8
DB1
9
AB
19
AB
24
DB2
DB1
2A
B8
AB
4
AB
10
AB
0
AB
21
AB
9
AB
23
AB
12
DB3
AB
2N
WR
2
DB1
3
DB2
8
AB
24
AB
14
AB
22A
B25
AB
20
AB
14
DB2
3
AB
8
DB9
AB
0
DB2
9
DB3
AB
9
DB4
DB1
1
DB5
AB
4
AB
16
AB
1
AB
17
DB5
DB6
DB1
4
AB
12
DB1
3
AB
18
DB1
DB1
0D
B11
DB2
1
AB
11
DB3
1
AB
5A
B7
AB
23
DB2
5
AB
3
DB2
7
AB
16
AB
18
DB1
0
DB1
7
DB2
6
DB1
6
AB
15
DB7
AB
19
AB
17
DB1
DB3
0
DB2
AB
21
DB1
2
AB
15
DB4
AB
2
DB0
AB
7
AB
2
DB0
DB1
4
AB
6
AB
13
DB1
5
DB1
8
AB
5
AB
6
PD24
PB
16
PB
5
PB
24
PD8
PB
20P
B19
PD11
PB
14
PB19
PB24
PD12
PD27
PB
8
PD14
PB12
PB16
PB22
PB
26
PB
22
PD3
PB
18
PD21
PB
9
PB29
PB20
PD25
PB
2
PB
17
PB
28
PB17
PB
11
PD1
PB
0
PB
29
PB21
PB26
PD4
PD6
PD20
PD0
PB
6
PB
13
PB25
PD16
PD10
PB
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Da
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pert
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epro
duct
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and
publ
icat
ion
wit
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our
wri
tten
aut
hori
zati
on s
hall
exp
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offe
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to
lega
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ED
T O
RG
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5 5
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DB5
DB4
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[0..
7]
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[0..
27]
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[0..
15]
3V3
3V3
3V3
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D IND
Da
te:
ST
UD
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1027
Av
du d
octe
ur L
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Tél 0
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02
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Da
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TYPE
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ME
RO
IND
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EFT
Th
is a
gr
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me
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is
our
pro
pert
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epro
duct
ion
and
publ
icat
ion
wit
hout
our
wri
tten
aut
hori
zati
on s
hall
exp
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offe
nder
to
lega
l pr
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ding
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ED
T O
RG
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0627
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EUVE
LO
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T
12 13
Wed
nesd
ay,
May
21
, 200
3
63SC
0205
14C
FIN
GE
RC
HIP
3
JP
G0
4/0
4/02
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M92
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GB
JP
GC
21
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Printed on recycled paper.
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standardwarranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for anyerrors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, anddoes not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel aregranted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for useas critical components in life support devices or systems.
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6006A–ATARM–07/03 /0M
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