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Routing for Reliability in Molecular Diode-based Programmable Nanofabrics

Kushal Datta, Arindam Mukherjee and Arun RavindranKushal Datta, Arindam Mukherjee and Arun Ravindran

Department of Electrical and Computer EngineeringDepartment of Electrical and Computer Engineering

University of North Carolina at CharlotteUniversity of North Carolina at Charlotte

MAPLD 2005/1031

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Nanofabric Architecture

SwitchBlock

Diode-based CMU Architecture

NanoFabrics: Spatial Computing Using Molecular ElectronicsSeth Copen Goldstein and Mihai BudiuProc. of The 28th Annual International Symposium on Computer Architecture, June 2001.

Nano Block

CMOS on Molecular: CMOL

MAPLD 2005/1031

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Circuit Primitives

A B

f = A . BA B

f = A+B

A B

Vdd

f = A . B

f f

f

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Circuit Primitives

A B

Vdd

f = A+B

A

AA

A

Vdd

f

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Nano Electronic Design AutomationAn example Problem Formulation

• Given– A logic design– A nanofabric

• Constraints– Entry and exit directions of signals in nano/switch blocks– Size of nano and switch blocks

• Minimize– The total number of diodes and switches used

Improve robustness

MAPLD 2005/1031

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Nano EDA Flow

Optimized Nano Layout

Routing Space Search

VHDL Code

Boolean Function net list

Decomposed List

Packed List

Placed Gate Array

PKS + script

Flow Map

VPACK

VPR

Placed Nanofabric

Alternate Routes

Our IP optimizer

Map FPGA Nanofabric

MAPLD 2005/1031

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Placement

• Use a standard algorithm of VPR and get a placed file.

• Modify the placed file.• Modification of the placed file involves

considering all the possible 12 transformations and deriving equations for them.

• Implement a mapping program for this.

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PlacementSample placed file

Equations based on the transformation from the placed file for gate array to the placed file for the nano fabric:

x = 2x – z y = 2y – z

y

A

B

C

D

E

F

G

H

0

1

0

1

0

1

01

x

Slice number (z)

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Global Routing Problem Formulation

Required AND gate literals enter from West (W) side

Required OR gate literals enter from North (N) side

If (R (li) = W) & (E (li)=N) 1 extra diode

If (R (li) = N) & (E (li)=W) 1 extra diode

li

li

li

li

Vdd

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Problem Formulation

A

CB S2

S1l3

l2

l1

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Future Design Flow

VLSI-inspired Nano-EDABio-inspired Nano-EDA

High Fault Tolerance Low Power

Optimized Nano Layout

Routing Space Search

VHDL Code

Boolean Function net list

Decomposed List

Packed List

Placed Gate Array

PKS + script

Flow Map

VPACK

VPR

Placed Nanofabric

Alternate Routes

Our IP optimizer

Map FPGA Nanofabric

MAPLD 2005/1031

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Integrate Placement with Global and Detailed Routing -

Improve Fault Tolerance

• Simulated Annealing

• Moves :– Select switch and nano blocks for placement

– Select switch and nano blocks for global routing

– Select entry and exit edges for global routing

– Select exact entry and exit row/column in a block fro detailed routing

MAPLD 2005/1031