datasheet - production dataesdlin1524bj placement and pcb layout recommendations docid12658 rev 4...

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October 2017 DocID12658 Rev 4 1/12 This is information on a product in full production. www.st.com ESDLIN1524BJ Automotive Transil™, transient voltage suppressor (TVS) for LIN bus Datasheet - production data Features AEC-Q101 qualified Asymmetrical bidirectional device Stand-off voltage: - 15 V (to comply with reverse battery) + 24 V (to comply with jump start) Low leakage current Complies with the following standards ISO 10605 (C = 150 pF, R = 330 Ω) 30 kV (air discharge) 30 kV (contact discharge) ISO 10605 (C = 330 pF, R = 330 Ω) 30 kV (air discharge) 30 kV (contact discharge) ISO 7637-3 Pulse 3a: VS = -150 V Pulse 3b: VS = 100 V HBM MIL STD 833, class 3 (> 4 kV) ISO 17987-7 (LIN bus) SAE J3076 (CXPI bus) Description The device is an asymmetrical Transil diode designed specifically for one automotive LIN bus line against electrostatic discharge (ESD) protection. The SOD323 is a very small package that saves space on high density printed circuit board. Transil diodes provide high overvoltage protection by clamping action and have instantaneous response to transient overvoltages. TM: Transil is a trademark of STMicroelectronics. Figure 1: Pin configuration 1 2 SOD323 1 2 Bar indicates pin1

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Page 1: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

October 2017 DocID12658 Rev 4 1/12

This is information on a product in full production. www.st.com

ESDLIN1524BJ

Automotive Transil™, transient voltage suppressor (TVS) for LIN bus

Datasheet - production data

Features AEC-Q101 qualified

Asymmetrical bidirectional device

Stand-off voltage:

- 15 V (to comply with reverse battery)

+ 24 V (to comply with jump start)

Low leakage current

Complies with the following standards

ISO 10605 (C = 150 pF, R = 330 Ω)

30 kV (air discharge)

30 kV (contact discharge)

ISO 10605 (C = 330 pF, R = 330 Ω)

30 kV (air discharge)

30 kV (contact discharge)

ISO 7637-3

Pulse 3a: VS = -150 V

Pulse 3b: VS = 100 V

HBM MIL STD 833, class 3 (> 4 kV)

ISO 17987-7 (LIN bus)

SAE J3076 (CXPI bus)

Description The device is an asymmetrical Transil diode designed specifically for one automotive LIN bus line against electrostatic discharge (ESD) protection. The SOD323 is a very small package that saves space on high density printed circuit board.

Transil diodes provide high overvoltage protection by clamping action and have instantaneous response to transient overvoltages.

TM: Transil is a trademark of STMicroelectronics.

Figure 1: Pin configuration

1

2

SOD323

1 2

Bar indicates pin1

Page 2: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

Characteristics ESDLIN1524BJ

2/12 DocID12658 Rev 4

1 Characteristics Table 1: Absolute maximum ratings (limiting values) Tamb = 25° C

Symbol Parameter Value Unit

PPP Peak pulse power dissipation 8/20 μs Tj initial = Tamb 160 W

Tstg Storage junction temperature range -65 to +175 °C

Tj Maximum operating junction temperature -40 to +150

TL Maximum temperature for soldering during 10 s 260 °C

Table 2: ESD maximum ratings

Symbol Parameter Conditions Value Unit

ESD Electrostatic discharge capability

ISO 10605 (C = 150 pF, R = 330 Ω)

air discharge

contact discharge

30

30

kV ISO 10605 (C = 330 pF, R = 330 Ω)

air discharge

contact discharge

30

30

HBM MIL STD 833 10

Figure 2: Electrical characteristics (definitions)

VCLVBR VRM

IRM

IR

IPP

V

I

IRM

IR

IPP

VRMVBR VCL

IRM

Symbol Parameter

VRM Stand-off voltage

VBR Breakdown voltage

VCL Clamping voltage

IRM Leakage current at VRM

IR Breakdown current at VBR

IPP Peak pulse current

C Junction capacitance

Page 3: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ Characteristics

DocID12658 Rev 4 3/12

Table 3: Electrical characteristics (Tamb = 25 °C)

Symbol Test conditions Min. Typ. Max. Unit

VBR From pin 2 to pin 1

IR = 5 mA, tp < 50 ms 25.4 27.8 30.3

V From pin 1 to pin 2 17.1 18.9 20.3

IRM From pin 2 to pin 1 VRM = 24 V

1 50 nA

From pin 1 to pin 2 VRM = 15 V

VCL

From pin 2 to pin 1 IPP = 1 A

8/20 µs

40

V From pin 2 to pin 1 IPP = 3 A

50

From pin 1 to pin 2 IPP = 1 A

25

From pin 1 to pin 2 IPP = 5 A

35

C VR = 0 V, f = 1 MHz

16 20 pF

αT(1) From pin 2 to pin 1

9.6

10-4/°C From pin 1 to pin 2

8.8

Notes:

(1)ΔVBR = αT x (Tamb - 25) x VBR(25° C)

Page 4: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

Characteristics ESDLIN1524BJ

4/12 DocID12658 Rev 4

1.1 Characteristics (curves)

Figure 3: Relative variation of peak pulse power versus initial junction temperature

Figure 4: Peak pulse power versus exponential pulse duration

Figure 5: Junction capacitance versus line voltage, 15 V side

Figure 6: Junction capacitance versus line voltage, 24 V side

Figure 7: Clamping test conditions

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

1.1

0 25 50 75 100 125 150 175

Tj (°C)

PPP[Tj initial] / PPP [Tj initial = 25 °C]

1.E+01

1.E+02

1.E+03

1 10 100

PPP(W)

Tj initial =25 °C

tP(µs)

0

2

4

6

8

10

12

14

16

18

20

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

C(pF)

F = 1 MHz

VOSC=30mVRMS

Tj =25°C

15 V side

VLINE(V)

0

2

4

6

8

10

12

14

16

18

20

0 2 4 6 8 10 12 14 16 18 20 22 24

C(pF)

F=1 MHz

VOSC=30 mVRMS

TJ=25 °C

24 V side

VLINE(V)

Voltage

probe

TEST BOARD

Ground plane

1

2

V

Test configuration

50

Ω

Page 5: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ Characteristics

DocID12658 Rev 4 5/12

Figure 8: Response to ISO 7637-3 pulse 3a (Us = -150 V)

Figure 9: Response to ISO 7637-3 pulse 3b (Us = 100 V)

Figure 10: ESD response to ISO 16605 (C = 150 pF, R = 330 Ω, 8 kV contact)

Figure 11: ESD response to ISO 16605 (C = 150 pF, R = 330 Ω, 8 kV contact)

Page 6: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

Package information ESDLIN1524BJ

6/12 DocID12658 Rev 4

2 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark.

Epoxy meets UL94, V0

Lead-free package

2.1 SOD323 package information

Figure 12: SOD323 package outline

Page 7: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ Package information

DocID12658 Rev 4 7/12

Table 4: SOD323 package mechanical data

Ref.

Dimensions

Millimeters Inches

Min. Max. Min. Max.

A

1.17

0.046

A1

0.10

0.004

A2 0.93 1.01 0.037 0.040

b 0.25 0.44 0.01 0.017

c 0.10 0.25 0.004 0.01

D 1.52 1.80 0.06 0.071

E 1.11 1.45 0.044 0.057

HD 2.30 2.70 0.09 0.106

L 0.10 0.46 0.004 0.02

Q1 0.10 0.41 0.004 0.016

Figure 13: Footprint recommendations, dimensions in mm

0.54

0.860.86

1.28

3.00

Page 8: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

Package information ESDLIN1524BJ

8/12 DocID12658 Rev 4

2.2 SOD323 packing information

Figure 14: Tape dimension definitions

Figure 15: ESDLIN1524BJ-HQ reel dimensions

User direction of unreelingAll dimensions in mm

4.0 ± 0.12.0 ± 0.05

8.0

±0.3

2.0 ± 0.05

1.7

0.1

3.5

±-

0.0

5

Ø 1.5 0.0 + 1

1.07 1± 0. 1. ± 0.52 1

0. 0 ± 0.053

2.8

01

±0.

GND 3GND

24

GND 3GND

24

GND 3GND

24

Page 9: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ Placement and PCB layout recommendations

DocID12658 Rev 4 9/12

3 Placement and PCB layout recommendations

Below figure illustrates the PCB placement and layout recommendations for optimal benefits of the ESDLIN1524BJ.

Figure 16: Placement and PCB layout recommendations

LIN Node

Voltageregulator

LINTransceiver

MCU

Connecto

rLIN

24

15

ESDLIN1524BJ located as close as possible to the connector

Vbat

Gnd

With ground wire

Connecto

r

LIN

GND

With ground plane

Connecto

r

LIN

GND

Vbat Vbat

Page 10: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

Ordering information ESDLIN1524BJ

10/12 DocID12658 Rev 4

4 Ordering information Figure 17: Ordering information scheme

Table 5: Ordering information

Order code Marking Package Weight Base qty. Delivery mode

ESDLIN1524BJ 24 SOD323 5 mg

3000 Tape and reel

ESDLIN1524BJ-HQ 10000

ESDLIN 15 24 B J

ESDLIN protection

Stand-off voltage 115 = 15 V

Stand-off voltage 224 = 24 V

Bidirectional

PackageJ = SOD323

Page 11: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ Revision history

DocID12658 Rev 4 11/12

5 Revision history Table 6: Document revision history

Date Revision Changes

28-Aug-2006 1 Initial release.

22-Sep-2006 2 Added Figure 6 Placement and layout recommendations

18-Jan-2013 3 Updated Table 6. Added Figure 10 and Figure 11.

17-Oct-2017 4

Updated title and cover page.

Updated Table 1: "Absolute maximum ratings (limiting

values) Tamb = 25° C" and Table 3: "Electrical

characteristics (Tamb = 25 °C)".

Added Figure 8: "Response to ISO 7637-3 pulse 3a (Us = -

150 V)", Figure 9: "Response to ISO 7637-3 pulse 3b (Us =

100 V)", Figure 10: "ESD response to ISO 16605 ( C = 150

pF, R = 330 Ω, 8 kV contact)" and Figure 11: "ESD

response to ISO 16605 ( C = 150 pF, R = 330 Ω, 8 kV

contact)".

Minor text changes to improve readability.

Page 12: Datasheet - production dataESDLIN1524BJ Placement and PCB layout recommendations DocID12658 Rev 4 9/12 3 Placement and PCB layout recommendations Below figure illustrates the PCB placement

ESDLIN1524BJ

12/12 DocID12658 Rev 4

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications , and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products.

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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

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