LM3S6911 MicrocontrollerDATA SHEET

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July 03, 20082Preliminary

Table of ContentsRevision History ............................................................................................................................. 18About This Document .................................................................................................................... 20Audience .............................................................................................................................................. 20About This Manual ................................................................................................................................ 20Related Documents ............................................................................................................................... 20Documentation Conventions .................................................................................................................. 20

1 Architectural Overview ...................................................................................................... 231.1 Product Features ...................................................................................................................... 231.2 Target Applications .................................................................................................................... 281.3 High-Level Block Diagram ......................................................................................................... 281.4 Functional Overview .................................................................................................................. 291.4.1 ARM Cortex™-M3 ..................................................................................................................... 301.4.2 Motor Control Peripherals .......................................................................................................... 301.4.3 Analog Peripherals .................................................................................................................... 311.4.4 Serial Communications Peripherals ............................................................................................ 311.4.5 System Peripherals ................................................................................................................... 331.4.6 Memory Peripherals .................................................................................................................. 331.4.7 Additional Features ................................................................................................................... 341.4.8 Hardware Details ...................................................................................................................... 35

2 ARM Cortex-M3 Processor Core ...................................................................................... 362.1 Block Diagram .......................................................................................................................... 372.2 Functional Description ............................................................................................................... 372.2.1 Serial Wire and JTAG Debug ..................................................................................................... 372.2.2 Embedded Trace Macrocell (ETM) ............................................................................................. 382.2.3 Trace Port Interface Unit (TPIU) ................................................................................................. 382.2.4 ROM Table ............................................................................................................................... 382.2.5 Memory Protection Unit (MPU) ................................................................................................... 382.2.6 Nested Vectored Interrupt Controller (NVIC) ................................................................................ 38

3 Memory Map ....................................................................................................................... 424 Interrupts ............................................................................................................................ 445 JTAG Interface .................................................................................................................... 475.1 Block Diagram .......................................................................................................................... 485.2 Functional Description ............................................................................................................... 485.2.1 JTAG Interface Pins .................................................................................................................. 495.2.2 JTAG TAP Controller ................................................................................................................. 505.2.3 Shift Registers .......................................................................................................................... 515.2.4 Operational Considerations ........................................................................................................ 515.3 Initialization and Configuration ................................................................................................... 545.4 Register Descriptions ................................................................................................................ 545.4.1 Instruction Register (IR) ............................................................................................................. 545.4.2 Data Registers .......................................................................................................................... 56

6 System Control ................................................................................................................... 586.1 Functional Description ............................................................................................................... 586.1.1 Device Identification .................................................................................................................. 58

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6.1.2 Reset Control ............................................................................................................................ 586.1.3 Power Control ........................................................................................................................... 616.1.4 Clock Control ............................................................................................................................ 616.1.5 System Control ......................................................................................................................... 646.2 Initialization and Configuration ................................................................................................... 656.3 Register Map ............................................................................................................................ 656.4 Register Descriptions ................................................................................................................ 66

7 Hibernation Module .......................................................................................................... 1177.1 Block Diagram ........................................................................................................................ 1187.2 Functional Description ............................................................................................................. 1187.2.1 Register Access Timing ........................................................................................................... 1187.2.2 Clock Source .......................................................................................................................... 1197.2.3 Battery Management ............................................................................................................... 1207.2.4 Real-Time Clock ...................................................................................................................... 1217.2.5 Non-Volatile Memory ............................................................................................................... 1217.2.6 Power Control ......................................................................................................................... 1217.2.7 Interrupts and Status ............................................................................................................... 1227.3 Initialization and Configuration ................................................................................................. 1227.3.1 Initialization ............................................................................................................................. 1227.3.2 RTC Match Functionality (No Hibernation) ................................................................................ 1237.3.3 RTC Match/Wake-Up from Hibernation ..................................................................................... 1237.3.4 External Wake-Up from Hibernation .......................................................................................... 1237.3.5 RTC/External Wake-Up from Hibernation .................................................................................. 1237.4 Register Map .......................................................................................................................... 1237.5 Register Descriptions .............................................................................................................. 124

8 Internal Memory ............................................................................................................... 1378.1 Block Diagram ........................................................................................................................ 1378.2 Functional Description ............................................................................................................. 1378.2.1 SRAM Memory ........................................................................................................................ 1378.2.2 Flash Memory ......................................................................................................................... 1388.3 Flash Memory Initialization and Configuration ........................................................................... 1398.3.1 Flash Programming ................................................................................................................. 1398.3.2 Nonvolatile Register Programming ........................................................................................... 1408.4 Register Map .......................................................................................................................... 1408.5 Flash Register Descriptions (Flash Control Offset) ..................................................................... 1418.6 Flash Register Descriptions (System Control Offset) .................................................................. 148

9 General-Purpose Input/Outputs (GPIOs) ....................................................................... 1619.1 Functional Description ............................................................................................................. 1619.1.1 Data Control ........................................................................................................................... 1629.1.2 Interrupt Control ...................................................................................................................... 1639.1.3 Mode Control .......................................................................................................................... 1649.1.4 Commit Control ....................................................................................................................... 1649.1.5 Pad Control ............................................................................................................................. 1649.1.6 Identification ........................................................................................................................... 1649.2 Initialization and Configuration ................................................................................................. 1649.3 Register Map .......................................................................................................................... 1669.4 Register Descriptions .............................................................................................................. 167

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10 General-Purpose Timers ................................................................................................. 20210.1 Block Diagram ........................................................................................................................ 20210.2 Functional Description ............................................................................................................. 20310.2.1 GPTM Reset Conditions .......................................................................................................... 20410.2.2 32-Bit Timer Operating Modes .................................................................................................. 20410.2.3 16-Bit Timer Operating Modes .................................................................................................. 20510.3 Initialization and Configuration ................................................................................................. 20910.3.1 32-Bit One-Shot/Periodic Timer Mode ....................................................................................... 20910.3.2 32-Bit Real-Time Clock (RTC) Mode ......................................................................................... 21010.3.3 16-Bit One-Shot/Periodic Timer Mode ....................................................................................... 21010.3.4 16-Bit Input Edge Count Mode ................................................................................................. 21110.3.5 16-Bit Input Edge Timing Mode ................................................................................................ 21110.3.6 16-Bit PWM Mode ................................................................................................................... 21210.4 Register Map .......................................................................................................................... 21210.5 Register Descriptions .............................................................................................................. 213

11 Watchdog Timer ............................................................................................................... 23811.1 Block Diagram ........................................................................................................................ 23811.2 Functional Description ............................................................................................................. 23811.3 Initialization and Configuration ................................................................................................. 23911.4 Register Map .......................................................................................................................... 23911.5 Register Descriptions .............................................................................................................. 240

12 Universal Asynchronous Receivers/Transmitters (UARTs) ......................................... 26112.1 Block Diagram ........................................................................................................................ 26212.2 Functional Description ............................................................................................................. 26212.2.1 Transmit/Receive Logic ........................................................................................................... 26212.2.2 Baud-Rate Generation ............................................................................................................. 26312.2.3 Data Transmission .................................................................................................................. 26312.2.4 Serial IR (SIR) ......................................................................................................................... 26412.2.5 FIFO Operation ....................................................................................................................... 26512.2.6 Interrupts ................................................................................................................................ 26512.2.7 Loopback Operation ................................................................................................................ 26612.2.8 IrDA SIR block ........................................................................................................................ 26612.3 Initialization and Configuration ................................................................................................. 26612.4 Register Map .......................................................................................................................... 26712.5 Register Descriptions .............................................................................................................. 268

13 Synchronous Serial Interface (SSI) ................................................................................ 30213.1 Block Diagram ........................................................................................................................ 30213.2 Functional Description ............................................................................................................. 30213.2.1 Bit Rate Generation ................................................................................................................. 30313.2.2 FIFO Operation ....................................................................................................................... 30313.2.3 Interrupts ................................................................................................................................ 30313.2.4 Frame Formats ....................................................................................................................... 30413.3 Initialization and Configuration ................................................................................................. 31113.4 Register Map .......................................................................................................................... 31213.5 Register Descriptions .............................................................................................................. 313

14 Inter-Integrated Circuit (I2C) Interface ............................................................................ 33914.1 Block Diagram ........................................................................................................................ 339

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14.2 Functional Description ............................................................................................................. 33914.2.1 I2C Bus Functional Overview .................................................................................................... 34014.2.2 Available Speed Modes ........................................................................................................... 34214.2.3 Interrupts ................................................................................................................................ 34314.2.4 Loopback Operation ................................................................................................................ 34314.2.5 Command Sequence Flow Charts ............................................................................................ 34414.3 Initialization and Configuration ................................................................................................. 35014.4 Register Map .......................................................................................................................... 35114.5 Register Descriptions (I2C Master) ........................................................................................... 35214.6 Register Descriptions (I2C Slave) ............................................................................................. 365

15 Ethernet Controller .......................................................................................................... 37415.1 Block Diagram ........................................................................................................................ 37515.2 Functional Description ............................................................................................................. 37515.2.1 Internal MII Operation .............................................................................................................. 37615.2.2 PHY Configuration/Operation ................................................................................................... 37615.2.3 MAC Configuration/Operation .................................................................................................. 37715.2.4 Interrupts ................................................................................................................................ 37915.3 Initialization and Configuration ................................................................................................. 38015.4 Ethernet Register Map ............................................................................................................. 38115.5 Ethernet MAC Register Descriptions ......................................................................................... 38215.6 MII Management Register Descriptions ..................................................................................... 399

16 Analog Comparators ....................................................................................................... 41816.1 Block Diagram ........................................................................................................................ 41816.2 Functional Description ............................................................................................................. 41916.2.1 Internal Reference Programming .............................................................................................. 42016.3 Initialization and Configuration ................................................................................................. 42116.4 Register Map .......................................................................................................................... 42116.5 Register Descriptions .............................................................................................................. 422

17 Pin Diagram ...................................................................................................................... 43018 Signal Tables .................................................................................................................... 43218.1 100-Pin LQFP Package Pin Tables ........................................................................................... 43218.2 108-Pin BGA Package Pin Tables ............................................................................................ 445

19 Operating Characteristics ............................................................................................... 45920 Electrical Characteristics ................................................................................................ 46020.1 DC Characteristics .................................................................................................................. 46020.1.1 Maximum Ratings ................................................................................................................... 46020.1.2 Recommended DC Operating Conditions .................................................................................. 46020.1.3 On-Chip Low Drop-Out (LDO) Regulator Characteristics ............................................................ 46120.1.4 Power Specifications ............................................................................................................... 46120.1.5 Flash Memory Characteristics .................................................................................................. 46320.1.6 Hibernation ............................................................................................................................. 46320.2 AC Characteristics ................................................................................................................... 46320.2.1 Load Conditions ...................................................................................................................... 46320.2.2 Clocks .................................................................................................................................... 46320.2.3 Analog Comparator ................................................................................................................. 46420.2.4 I2C ......................................................................................................................................... 46520.2.5 Ethernet Controller .................................................................................................................. 465

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20.2.6 Hibernation Module ................................................................................................................. 46820.2.7 Synchronous Serial Interface (SSI) ........................................................................................... 46920.2.8 JTAG and Boundary Scan ........................................................................................................ 47020.2.9 General-Purpose I/O ............................................................................................................... 47220.2.10 Reset ..................................................................................................................................... 472

21 Package Information ........................................................................................................ 475A Serial Flash Loader .......................................................................................................... 479A.1 Serial Flash Loader ................................................................................................................. 479A.2 Interfaces ............................................................................................................................... 479A.2.1 UART ..................................................................................................................................... 479A.2.2 SSI ......................................................................................................................................... 479A.3 Packet Handling ...................................................................................................................... 480A.3.1 Packet Format ........................................................................................................................ 480A.3.2 Sending Packets ..................................................................................................................... 480A.3.3 Receiving Packets ................................................................................................................... 480A.4 Commands ............................................................................................................................. 481A.4.1 COMMAND_PING (0X20) ........................................................................................................ 481A.4.2 COMMAND_GET_STATUS (0x23) ........................................................................................... 481A.4.3 COMMAND_DOWNLOAD (0x21) ............................................................................................. 481A.4.4 COMMAND_SEND_DATA (0x24) ............................................................................................. 482A.4.5 COMMAND_RUN (0x22) ......................................................................................................... 482A.4.6 COMMAND_RESET (0x25) ..................................................................................................... 482

B Register Quick Reference ............................................................................................... 484C Ordering and Contact Information ................................................................................. 499C.1 Ordering Information ................................................................................................................ 499C.2 Kits ......................................................................................................................................... 499C.3 Company Information .............................................................................................................. 500C.4 Support Information ................................................................................................................. 500

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List of FiguresFigure 1-1. Stellaris® 1000 Series High-Level Block Diagram ............................................................... 29Figure 2-1. CPU Block Diagram ......................................................................................................... 37Figure 2-2. TPIU Block Diagram ........................................................................................................ 38Figure 5-1. JTAG Module Block Diagram ............................................................................................ 48Figure 5-2. Test Access Port State Machine ....................................................................................... 51Figure 5-3. IDCODE Register Format ................................................................................................. 56Figure 5-4. BYPASS Register Format ................................................................................................ 57Figure 5-5. Boundary Scan Register Format ....................................................................................... 57Figure 6-1. External Circuitry to Extend Reset .................................................................................... 59Figure 6-2. Main Clock Tree .............................................................................................................. 62Figure 7-1. Hibernation Module Block Diagram ................................................................................. 118Figure 7-2. Clock Source Using Crystal ............................................................................................ 119Figure 7-3. Clock Source Using Dedicated Oscillator ......................................................................... 120Figure 8-1. Flash Block Diagram ...................................................................................................... 137Figure 9-1. GPIO Port Block Diagram ............................................................................................... 162Figure 9-2. GPIODATA Write Example ............................................................................................. 163Figure 9-3. GPIODATA Read Example ............................................................................................. 163Figure 10-1. GPTM Module Block Diagram ........................................................................................ 203Figure 10-2. 16-Bit Input Edge Count Mode Example .......................................................................... 207Figure 10-3. 16-Bit Input Edge Time Mode Example ........................................................................... 208Figure 10-4. 16-Bit PWM Mode Example ............................................................................................ 209Figure 11-1. WDT Module Block Diagram .......................................................................................... 238Figure 12-1. UART Module Block Diagram ......................................................................................... 262Figure 12-2. UART Character Frame ................................................................................................. 263Figure 12-3. IrDA Data Modulation ..................................................................................................... 265Figure 13-1. SSI Module Block Diagram ............................................................................................. 302Figure 13-2. TI Synchronous Serial Frame Format (Single Transfer) .................................................... 305Figure 13-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................................ 305Figure 13-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ...................................... 306Figure 13-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 .............................. 306Figure 13-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ..................................................... 307Figure 13-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ........................... 308Figure 13-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 .................... 308Figure 13-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ..................................................... 309Figure 13-10. MICROWIRE Frame Format (Single Frame) .................................................................... 310Figure 13-11. MICROWIRE Frame Format (Continuous Transfer) ......................................................... 311Figure 13-12. MICROWIRE Frame Format, SSIFss Input Setup and Hold Requirements ........................ 311Figure 14-1. I2C Block Diagram ......................................................................................................... 339Figure 14-2. I2C Bus Configuration .................................................................................................... 340Figure 14-3. START and STOP Conditions ......................................................................................... 340Figure 14-4. Complete Data Transfer with a 7-Bit Address ................................................................... 341Figure 14-5. R/S Bit in First Byte ........................................................................................................ 341Figure 14-6. Data Validity During Bit Transfer on the I2C Bus ............................................................... 341Figure 14-7. Master Single SEND ...................................................................................................... 344Figure 14-8. Master Single RECEIVE ................................................................................................. 345

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Figure 14-9. Master Burst SEND ....................................................................................................... 346Figure 14-10. Master Burst RECEIVE .................................................................................................. 347Figure 14-11. Master Burst RECEIVE after Burst SEND ........................................................................ 348Figure 14-12. Master Burst SEND after Burst RECEIVE ........................................................................ 349Figure 14-13. Slave Command Sequence ............................................................................................ 350Figure 15-1. Ethernet Controller Block Diagram .................................................................................. 375Figure 15-2. Ethernet Controller ......................................................................................................... 375Figure 15-3. Ethernet Frame ............................................................................................................. 377Figure 16-1. Analog Comparator Module Block Diagram ..................................................................... 418Figure 16-2. Structure of Comparator Unit .......................................................................................... 419Figure 16-3. Comparator Internal Reference Structure ........................................................................ 420Figure 17-1. 100-Pin LQFP Package Pin Diagram .............................................................................. 430Figure 17-2. 108-Ball BGA Package Pin Diagram (Top View) ............................................................... 431Figure 20-1. Load Conditions ............................................................................................................ 463Figure 20-2. I2C Timing ..................................................................................................................... 465Figure 20-3. External XTLP Oscillator Characteristics ......................................................................... 468Figure 20-4. Hibernation Module Timing ............................................................................................. 469Figure 20-5. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing Measurement .............. 469Figure 20-6. SSI Timing for MICROWIRE Frame Format (FRF=10), Single Transfer ............................. 470Figure 20-7. SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................................................. 470Figure 20-8. JTAG Test Clock Input Timing ......................................................................................... 471Figure 20-9. JTAG Test Access Port (TAP) Timing .............................................................................. 472Figure 20-10. JTAG TRST Timing ........................................................................................................ 472Figure 20-11. External Reset Timing (RST) .......................................................................................... 473Figure 20-12. Power-On Reset Timing ................................................................................................. 473Figure 20-13. Brown-Out Reset Timing ................................................................................................ 473Figure 20-14. Software Reset Timing ................................................................................................... 474Figure 20-15. Watchdog Reset Timing ................................................................................................. 474Figure 21-1. 100-Pin LQFP Package .................................................................................................. 475Figure 21-2. 108-Ball BGA Package .................................................................................................. 477

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List of TablesTable 1. Revision History .............................................................................................................. 18Table 2. Documentation Conventions ............................................................................................ 20Table 3-1. Memory Map ................................................................................................................... 42Table 4-1. Exception Types .............................................................................................................. 44Table 4-2. Interrupts ........................................................................................................................ 45Table 5-1. JTAG Port Pins Reset State ............................................................................................. 49Table 5-2. JTAG Instruction Register Commands ............................................................................... 54Table 6-1. System Control Register Map ........................................................................................... 65Table 7-1. Hibernation Module Register Map ................................................................................... 124Table 8-1. Flash Protection Policy Combinations ............................................................................. 138Table 8-2. Flash Resident Registers ............................................................................................... 140Table 8-3. Flash Register Map ........................................................................................................ 141Table 9-1. GPIO Pad Configuration Examples ................................................................................. 165Table 9-2. GPIO Interrupt Configuration Example ............................................................................ 165Table 9-3. GPIO Register Map ....................................................................................................... 166Table 10-1. Available CCP Pins ........................................................................................................ 203Table 10-2. 16-Bit Timer With Prescaler Configurations ..................................................................... 206Table 10-3. Timers Register Map ...................................................................................................... 212Table 11-1. Watchdog Timer Register Map ........................................................................................ 239Table 12-1. UART Register Map ....................................................................................................... 267Table 13-1. SSI Register Map .......................................................................................................... 313Table 14-1. Examples of I2C Master Timer Period versus Speed Mode ............................................... 342Table 14-2. Inter-Integrated Circuit (I2C) Interface Register Map ......................................................... 351Table 14-3. Write Field Decoding for I2CMCS[3:0] Field (Sheet 1 of 3) ................................................ 356Table 15-1. TX & RX FIFO Organization ........................................................................................... 378Table 15-2. Ethernet Register Map ................................................................................................... 381Table 16-1. Comparator 0 Operating Modes ..................................................................................... 419Table 16-2. Comparator 1 Operating Modes ...................................................................................... 420Table 16-3. Internal Reference Voltage and ACREFCTL Field Values ................................................. 420Table 16-4. Analog Comparators Register Map ................................................................................. 422Table 18-1. Signals by Pin Number ................................................................................................... 432Table 18-2. Signals by Signal Name ................................................................................................. 436Table 18-3. Signals by Function, Except for GPIO ............................................................................. 440Table 18-4. GPIO Pins and Alternate Functions ................................................................................. 443Table 18-5. Signals by Pin Number ................................................................................................... 445Table 18-6. Signals by Signal Name ................................................................................................. 449Table 18-7. Signals by Function, Except for GPIO ............................................................................. 454Table 18-8. GPIO Pins and Alternate Functions ................................................................................. 457Table 19-1. Temperature Characteristics ........................................................................................... 459Table 19-2. Thermal Characteristics ................................................................................................. 459Table 20-1. Maximum Ratings .......................................................................................................... 460Table 20-2. Recommended DC Operating Conditions ........................................................................ 460Table 20-3. LDO Regulator Characteristics ....................................................................................... 461Table 20-4. Detailed Power Specifications ........................................................................................ 462Table 20-5. Flash Memory Characteristics ........................................................................................ 463Table 20-6. Hibernation Module DC Characteristics ........................................................................... 463

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Table 20-7. Phase Locked Loop (PLL) Characteristics ....................................................................... 463Table 20-8. Clock Characteristics ..................................................................................................... 464Table 20-9. Crystal Characteristics ................................................................................................... 464Table 20-10. Analog Comparator Characteristics ................................................................................. 464Table 20-11. Analog Comparator Voltage Reference Characteristics .................................................... 464Table 20-12. I2C Characteristics ......................................................................................................... 465Table 20-13. 100BASE-TX Transmitter Characteristics ........................................................................ 465Table 20-14. 100BASE-TX Transmitter Characteristics (informative) ..................................................... 466Table 20-15. 100BASE-TX Receiver Characteristics ............................................................................ 466Table 20-16. 10BASE-T Transmitter Characteristics ............................................................................ 466Table 20-17. 10BASE-T Transmitter Characteristics (informative) ......................................................... 466Table 20-18. 10BASE-T Receiver Characteristics ................................................................................ 466Table 20-19. Isolation Transformers ................................................................................................... 467Table 20-20. Ethernet Reference Crystal ............................................................................................ 467Table 20-21. External XTLP Oscillator Characteristics ......................................................................... 468Table 20-22. Hibernation Module AC Characteristics ........................................................................... 468Table 20-23. SSI Characteristics ........................................................................................................ 469Table 20-24. JTAG Characteristics ..................................................................................................... 470Table 20-25. GPIO Characteristics ..................................................................................................... 472Table 20-26. Reset Characteristics ..................................................................................................... 472Table C-1. Part Ordering Information ............................................................................................... 499

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List of RegistersSystem Control .............................................................................................................................. 58Register 1: Device Identification 0 (DID0), offset 0x000 ....................................................................... 67Register 2: Brown-Out Reset Control (PBORCTL), offset 0x030 .......................................................... 69Register 3: LDO Power Control (LDOPCTL), offset 0x034 ................................................................... 70Register 4: Raw Interrupt Status (RIS), offset 0x050 ........................................................................... 71Register 5: Interrupt Mask Control (IMC), offset 0x054 ........................................................................ 72Register 6: Masked Interrupt Status and Clear (MISC), offset 0x058 .................................................... 73Register 7: Reset Cause (RESC), offset 0x05C .................................................................................. 74Register 8: Run-Mode Clock Configuration (RCC), offset 0x060 .......................................................... 75Register 9: XTAL to PLL Translation (PLLCFG), offset 0x064 .............................................................. 79Register 10: Run-Mode Clock Configuration 2 (RCC2), offset 0x070 ...................................................... 80Register 11: Deep Sleep Clock Configuration (DSLPCLKCFG), offset 0x144 .......................................... 82Register 12: Device Identification 1 (DID1), offset 0x004 ....................................................................... 83Register 13: Device Capabilities 0 (DC0), offset 0x008 ......................................................................... 85Register 14: Device Capabilities 1 (DC1), offset 0x010 ......................................................................... 86Register 15: Device Capabilities 2 (DC2), offset 0x014 ......................................................................... 88Register 16: Device Capabilities 3 (DC3), offset 0x018 ......................................................................... 90Register 17: Device Capabilities 4 (DC4), offset 0x01C ......................................................................... 92Register 18: Run Mode Clock Gating Control Register 0 (RCGC0), offset 0x100 .................................... 94Register 19: Sleep Mode Clock Gating Control Register 0 (SCGC0), offset 0x110 .................................. 95Register 20: Deep Sleep Mode Clock Gating Control Register 0 (DCGC0), offset 0x120 ......................... 96Register 21: Run Mode Clock Gating Control Register 1 (RCGC1), offset 0x104 .................................... 97Register 22: Sleep Mode Clock Gating Control Register 1 (SCGC1), offset 0x114 ................................. 100Register 23: Deep Sleep Mode Clock Gating Control Register 1 (DCGC1), offset 0x124 ....................... 103Register 24: Run Mode Clock Gating Control Register 2 (RCGC2), offset 0x108 ................................... 106Register 25: Sleep Mode Clock Gating Control Register 2 (SCGC2), offset 0x118 ................................. 108Register 26: Deep Sleep Mode Clock Gating Control Register 2 (DCGC2), offset 0x128 ....................... 110Register 27: Software Reset Control 0 (SRCR0), offset 0x040 ............................................................. 112Register 28: Software Reset Control 1 (SRCR1), offset 0x044 ............................................................. 113Register 29: Software Reset Control 2 (SRCR2), offset 0x048 ............................................................. 115

Hibernation Module ..................................................................................................................... 117Register 1: Hibernation RTC Counter (HIBRTCC), offset 0x000 ......................................................... 125Register 2: Hibernation RTC Match 0 (HIBRTCM0), offset 0x004 ....................................................... 126Register 3: Hibernation RTC Match 1 (HIBRTCM1), offset 0x008 ....................................................... 127Register 4: Hibernation RTC Load (HIBRTCLD), offset 0x00C ........................................................... 128Register 5: Hibernation Control (HIBCTL), offset 0x010 ..................................................................... 129Register 6: Hibernation Interrupt Mask (HIBIM), offset 0x014 ............................................................. 131Register 7: Hibernation Raw Interrupt Status (HIBRIS), offset 0x018 .................................................. 132Register 8: Hibernation Masked Interrupt Status (HIBMIS), offset 0x01C ............................................ 133Register 9: Hibernation Interrupt Clear (HIBIC), offset 0x020 ............................................................. 134Register 10: Hibernation RTC Trim (HIBRTCT), offset 0x024 ............................................................... 135Register 11: Hibernation Data (HIBDATA), offset 0x030-0x12C ............................................................ 136

Internal Memory ........................................................................................................................... 137Register 1: Flash Memory Address (FMA), offset 0x000 .................................................................... 142Register 2: Flash Memory Data (FMD), offset 0x004 ......................................................................... 143

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Register 3: Flash Memory Control (FMC), offset 0x008 ..................................................................... 144Register 4: Flash Controller Raw Interrupt Status (FCRIS), offset 0x00C ............................................ 146Register 5: Flash Controller Interrupt Mask (FCIM), offset 0x010 ........................................................ 147Register 6: Flash Controller Masked Interrupt Status and Clear (FCMISC), offset 0x014 ..................... 148Register 7: USec Reload (USECRL), offset 0x140 ............................................................................ 149Register 8: Flash Memory Protection Read Enable 0 (FMPRE0), offset 0x130 and 0x200 ................... 150Register 9: Flash Memory Protection Program Enable 0 (FMPPE0), offset 0x134 and 0x400 ............... 151Register 10: User Debug (USER_DBG), offset 0x1D0 ......................................................................... 152Register 11: User Register 0 (USER_REG0), offset 0x1E0 .................................................................. 153Register 12: User Register 1 (USER_REG1), offset 0x1E4 .................................................................. 154Register 13: Flash Memory Protection Read Enable 1 (FMPRE1), offset 0x204 .................................... 155Register 14: Flash Memory Protection Read Enable 2 (FMPRE2), offset 0x208 .................................... 156Register 15: Flash Memory Protection Read Enable 3 (FMPRE3), offset 0x20C ................................... 157Register 16: Flash Memory Protection Program Enable 1 (FMPPE1), offset 0x404 ............................... 158Register 17: Flash Memory Protection Program Enable 2 (FMPPE2), offset 0x408 ............................... 159Register 18: Flash Memory Protection Program Enable 3 (FMPPE3), offset 0x40C ............................... 160

General-Purpose Input/Outputs (GPIOs) ................................................................................... 161Register 1: GPIO Data (GPIODATA), offset 0x000 ............................................................................ 168Register 2: GPIO Direction (GPIODIR), offset 0x400 ......................................................................... 169Register 3: GPIO Interrupt Sense (GPIOIS), offset 0x404 .................................................................. 170Register 4: GPIO Interrupt Both Edges (GPIOIBE), offset 0x408 ........................................................ 171Register 5: GPIO Interrupt Event (GPIOIEV), offset 0x40C ................................................................ 172Register 6: GPIO Interrupt Mask (GPIOIM), offset 0x410 ................................................................... 173Register 7: GPIO Raw Interrupt Status (GPIORIS), offset 0x414 ........................................................ 174Register 8: GPIO Masked Interrupt Status (GPIOMIS), offset 0x418 ................................................... 175Register 9: GPIO Interrupt Clear (GPIOICR), offset 0x41C ................................................................ 176Register 10: GPIO Alternate Function Select (GPIOAFSEL), offset 0x420 ............................................ 177Register 11: GPIO 2-mA Drive Select (GPIODR2R), offset 0x500 ........................................................ 179Register 12: GPIO 4-mA Drive Select (GPIODR4R), offset 0x504 ........................................................ 180Register 13: GPIO 8-mA Drive Select (GPIODR8R), offset 0x508 ........................................................ 181Register 14: GPIO Open Drain Select (GPIOODR), offset 0x50C ......................................................... 182Register 15: GPIO Pull-Up Select (GPIOPUR), offset 0x510 ................................................................ 183Register 16: GPIO Pull-Down Select (GPIOPDR), offset 0x514 ........................................................... 184Register 17: GPIO Slew Rate Control Select (GPIOSLR), offset 0x518 ................................................ 185Register 18: GPIO Digital Enable (GPIODEN), offset 0x51C ................................................................ 186Register 19: GPIO Lock (GPIOLOCK), offset 0x520 ............................................................................ 187Register 20: GPIO Commit (GPIOCR), offset 0x524 ............................................................................ 188Register 21: GPIO Peripheral Identification 4 (GPIOPeriphID4), offset 0xFD0 ....................................... 190Register 22: GPIO Peripheral Identification 5 (GPIOPeriphID5), offset 0xFD4 ....................................... 191Register 23: GPIO Peripheral Identification 6 (GPIOPeriphID6), offset 0xFD8 ....................................... 192Register 24: GPIO Peripheral Identification 7 (GPIOPeriphID7), offset 0xFDC ...................................... 193Register 25: GPIO Peripheral Identification 0 (GPIOPeriphID0), offset 0xFE0 ....................................... 194Register 26: GPIO Peripheral Identification 1 (GPIOPeriphID1), offset 0xFE4 ....................................... 195Register 27: GPIO Peripheral Identification 2 (GPIOPeriphID2), offset 0xFE8 ....................................... 196Register 28: GPIO Peripheral Identification 3 (GPIOPeriphID3), offset 0xFEC ...................................... 197Register 29: GPIO PrimeCell Identification 0 (GPIOPCellID0), offset 0xFF0 .......................................... 198Register 30: GPIO PrimeCell Identification 1 (GPIOPCellID1), offset 0xFF4 .......................................... 199Register 31: GPIO PrimeCell Identification 2 (GPIOPCellID2), offset 0xFF8 .......................................... 200

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Register 32: GPIO PrimeCell Identification 3 (GPIOPCellID3), offset 0xFFC ......................................... 201

General-Purpose Timers ............................................................................................................. 202Register 1: GPTM Configuration (GPTMCFG), offset 0x000 .............................................................. 214Register 2: GPTM TimerA Mode (GPTMTAMR), offset 0x004 ............................................................ 215Register 3: GPTM TimerB Mode (GPTMTBMR), offset 0x008 ............................................................ 217Register 4: GPTM Control (GPTMCTL), offset 0x00C ........................................................................ 219Register 5: GPTM Interrupt Mask (GPTMIMR), offset 0x018 .............................................................. 222Register 6: GPTM Raw Interrupt Status (GPTMRIS), offset 0x01C ..................................................... 224Register 7: GPTM Masked Interrupt Status (GPTMMIS), offset 0x020 ................................................ 225Register 8: GPTM Interrupt Clear (GPTMICR), offset 0x024 .............................................................. 226Register 9: GPTM TimerA Interval Load (GPTMTAILR), offset 0x028 ................................................. 228Register 10: GPTM TimerB Interval Load (GPTMTBILR), offset 0x02C ................................................ 229Register 11: GPTM TimerA Match (GPTMTAMATCHR), offset 0x030 ................................................... 230Register 12: GPTM TimerB Match (GPTMTBMATCHR), offset 0x034 .................................................. 231Register 13: GPTM TimerA Prescale (GPTMTAPR), offset 0x038 ........................................................ 232Register 14: GPTM TimerB Prescale (GPTMTBPR), offset 0x03C ....................................................... 233Register 15: GPTM TimerA Prescale Match (GPTMTAPMR), offset 0x040 ........................................... 234Register 16: GPTM TimerB Prescale Match (GPTMTBPMR), offset 0x044 ........................................... 235Register 17: GPTM TimerA (GPTMTAR), offset 0x048 ........................................................................ 236Register 18: GPTM TimerB (GPTMTBR), offset 0x04C ....................................................................... 237

Watchdog Timer ........................................................................................................................... 238Register 1: Watchdog Load (WDTLOAD), offset 0x000 ...................................................................... 241Register 2: Watchdog Value (WDTVALUE), offset 0x004 ................................................................... 242Register 3: Watchdog Control (WDTCTL), offset 0x008 ..................................................................... 243Register 4: Watchdog Interrupt Clear (WDTICR), offset 0x00C .......................................................... 244Register 5: Watchdog Raw Interrupt Status (WDTRIS), offset 0x010 .................................................. 245Register 6: Watchdog Masked Interrupt Status (WDTMIS), offset 0x014 ............................................. 246Register 7: Watchdog Test (WDTTEST), offset 0x418 ....................................................................... 247Register 8: Watchdog Lock (WDTLOCK), offset 0xC00 ..................................................................... 248Register 9: Watchdog Peripheral Identification 4 (WDTPeriphID4), offset 0xFD0 ................................. 249Register 10: Watchdog Peripheral Identification 5 (WDTPeriphID5), offset 0xFD4 ................................. 250Register 11: Watchdog Peripheral Identification 6 (WDTPeriphID6), offset 0xFD8 ................................. 251Register 12: Watchdog Peripheral Identification 7 (WDTPeriphID7), offset 0xFDC ................................ 252Register 13: Watchdog Peripheral Identification 0 (WDTPeriphID0), offset 0xFE0 ................................. 253Register 14: Watchdog Peripheral Identification 1 (WDTPeriphID1), offset 0xFE4 ................................. 254Register 15: Watchdog Peripheral Identification 2 (WDTPeriphID2), offset 0xFE8 ................................. 255Register 16: Watchdog Peripheral Identification 3 (WDTPeriphID3), offset 0xFEC ................................. 256Register 17: Watchdog PrimeCell Identification 0 (WDTPCellID0), offset 0xFF0 .................................... 257Register 18: Watchdog PrimeCell Identification 1 (WDTPCellID1), offset 0xFF4 .................................... 258Register 19: Watchdog PrimeCell Identification 2 (WDTPCellID2), offset 0xFF8 .................................... 259Register 20: Watchdog PrimeCell Identification 3 (WDTPCellID3 ), offset 0xFFC .................................. 260

Universal Asynchronous Receivers/Transmitters (UARTs) ..................................................... 261Register 1: UART Data (UARTDR), offset 0x000 ............................................................................... 269Register 2: UART Receive Status/Error Clear (UARTRSR/UARTECR), offset 0x004 ........................... 271Register 3: UART Flag (UARTFR), offset 0x018 ................................................................................ 273Register 4: UART IrDA Low-Power Register (UARTILPR), offset 0x020 ............................................. 275Register 5: UART Integer Baud-Rate Divisor (UARTIBRD), offset 0x024 ............................................ 276Register 6: UART Fractional Baud-Rate Divisor (UARTFBRD), offset 0x028 ....................................... 277

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Register 7: UART Line Control (UARTLCRH), offset 0x02C ............................................................... 278Register 8: UART Control (UARTCTL), offset 0x030 ......................................................................... 280Register 9: UART Interrupt FIFO Level Select (UARTIFLS), offset 0x034 ........................................... 282Register 10: UART Interrupt Mask (UARTIM), offset 0x038 ................................................................. 284Register 11: UART Raw Interrupt Status (UARTRIS), offset 0x03C ...................................................... 286Register 12: UART Masked Interrupt Status (UARTMIS), offset 0x040 ................................................. 287Register 13: UART Interrupt Clear (UARTICR), offset 0x044 ............................................................... 288Register 14: UART Peripheral Identification 4 (UARTPeriphID4), offset 0xFD0 ..................................... 290Register 15: UART Peripheral Identification 5 (UARTPeriphID5), offset 0xFD4 ..................................... 291Register 16: UART Peripheral Identification 6 (UARTPeriphID6), offset 0xFD8 ..................................... 292Register 17: UART Peripheral Identification 7 (UARTPeriphID7), offset 0xFDC ..................................... 293Register 18: UART Peripheral Identification 0 (UARTPeriphID0), offset 0xFE0 ...................................... 294Register 19: UART Peripheral Identification 1 (UARTPeriphID1), offset 0xFE4 ...................................... 295Register 20: UART Peripheral Identification 2 (UARTPeriphID2), offset 0xFE8 ...................................... 296Register 21: UART Peripheral Identification 3 (UARTPeriphID3), offset 0xFEC ..................................... 297Register 22: UART PrimeCell Identification 0 (UARTPCellID0), offset 0xFF0 ........................................ 298Register 23: UART PrimeCell Identification 1 (UARTPCellID1), offset 0xFF4 ........................................ 299Register 24: UART PrimeCell Identification 2 (UARTPCellID2), offset 0xFF8 ........................................ 300Register 25: UART PrimeCell Identification 3 (UARTPCellID3), offset 0xFFC ........................................ 301

Synchronous Serial Interface (SSI) ............................................................................................ 302Register 1: SSI Control 0 (SSICR0), offset 0x000 .............................................................................. 314Register 2: SSI Control 1 (SSICR1), offset 0x004 .............................................................................. 316Register 3: SSI Data (SSIDR), offset 0x008 ...................................................................................... 318Register 4: SSI Status (SSISR), offset 0x00C ................................................................................... 319Register 5: SSI Clock Prescale (SSICPSR), offset 0x010 .................................................................. 321Register 6: SSI Interrupt Mask (SSIIM), offset 0x014 ......................................................................... 322Register 7: SSI Raw Interrupt Status (SSIRIS), offset 0x018 .............................................................. 324Register 8: SSI Masked Interrupt Status (SSIMIS), offset 0x01C ........................................................ 325Register 9: SSI Interrupt Clear (SSIICR), offset 0x020 ....................................................................... 326Register 10: SSI Peripheral Identification 4 (SSIPeriphID4), offset 0xFD0 ............................................. 327Register 11: SSI Peripheral Identification 5 (SSIPeriphID5), offset 0xFD4 ............................................. 328Register 12: SSI Peripheral Identification 6 (SSIPeriphID6), offset 0xFD8 ............................................. 329Register 13: SSI Peripheral Identification 7 (SSIPeriphID7), offset 0xFDC ............................................ 330Register 14: SSI Peripheral Identification 0 (SSIPeriphID0), offset 0xFE0 ............................................. 331Register 15: SSI Peripheral Identification 1 (SSIPeriphID1), offset 0xFE4 ............................................. 332Register 16: SSI Peripheral Identification 2 (SSIPeriphID2), offset 0xFE8 ............................................. 333Register 17: SSI Peripheral Identification 3 (SSIPeriphID3), offset 0xFEC ............................................ 334Register 18: SSI PrimeCell Identification 0 (SSIPCellID0), offset 0xFF0 ............................................... 335Register 19: SSI PrimeCell Identification 1 (SSIPCellID1), offset 0xFF4 ............................................... 336Register 20: SSI PrimeCell Identification 2 (SSIPCellID2), offset 0xFF8 ............................................... 337Register 21: SSI PrimeCell Identification 3 (SSIPCellID3), offset 0xFFC ............................................... 338

Inter-Integrated Circuit (I2C) Interface ........................................................................................ 339Register 1: I2C Master Slave Address (I2CMSA), offset 0x000 ........................................................... 353Register 2: I2C Master Control/Status (I2CMCS), offset 0x004 ........................................................... 354Register 3: I2C Master Data (I2CMDR), offset 0x008 ......................................................................... 358Register 4: I2C Master Timer Period (I2CMTPR), offset 0x00C ........................................................... 359Register 5: I2C Master Interrupt Mask (I2CMIMR), offset 0x010 ......................................................... 360Register 6: I2C Master Raw Interrupt Status (I2CMRIS), offset 0x014 ................................................. 361

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Register 7: I2C Master Masked Interrupt Status (I2CMMIS), offset 0x018 ........................................... 362Register 8: I2C Master Interrupt Clear (I2CMICR), offset 0x01C ......................................................... 363Register 9: I2C Master Configuration (I2CMCR), offset 0x020 ............................................................ 364Register 10: I2C Slave Own Address (I2CSOAR), offset 0x000 ............................................................ 366Register 11: I2C Slave Control/Status (I2CSCSR), offset 0x004 ........................................................... 367Register 12: I2C Slave Data (I2CSDR), offset 0x008 ........................................................................... 369Register 13: I2C Slave Interrupt Mask (I2CSIMR), offset 0x00C ........................................................... 370Register 14: I2C Slave Raw Interrupt Status (I2CSRIS), offset 0x010 ................................................... 371Register 15: I2C Slave Masked Interrupt Status (I2CSMIS), offset 0x014 .............................................. 372Register 16: I2C Slave Interrupt Clear (I2CSICR), offset 0x018 ............................................................ 373

Ethernet Controller ...................................................................................................................... 374Register 1: Ethernet MAC Raw Interrupt Status (MACRIS), offset 0x000 ............................................ 383Register 2: Ethernet MAC Interrupt Acknowledge (MACIACK), offset 0x000 ....................................... 385Register 3: Ethernet MAC Interrupt Mask (MACIM), offset 0x004 ....................................................... 386Register 4: Ethernet MAC Receive Control (MACRCTL), offset 0x008 ................................................ 387Register 5: Ethernet MAC Transmit Control (MACTCTL), offset 0x00C ............................................... 388Register 6: Ethernet MAC Data (MACDATA), offset 0x010 ................................................................. 389Register 7: Ethernet MAC Individual Address 0 (MACIA0), offset 0x014 ............................................. 391Register 8: Ethernet MAC Individual Address 1 (MACIA1), offset 0x018 ............................................. 392Register 9: Ethernet MAC Threshold (MACTHR), offset 0x01C .......................................................... 393Register 10: Ethernet MAC Management Control (MACMCTL), offset 0x020 ........................................ 394Register 11: Ethernet MAC Management Divider (MACMDV), offset 0x024 .......................................... 395Register 12: Ethernet MAC Management Transmit Data (MACMTXD), offset 0x02C ............................. 396Register 13: Ethernet MAC Management Receive Data (MACMRXD), offset 0x030 .............................. 397Register 14: Ethernet MAC Number of Packets (MACNP), offset 0x034 ............................................... 398Register 15: Ethernet MAC Transmission Request (MACTR), offset 0x038 ........................................... 399Register 16: Ethernet PHY Management Register 0 – Control (MR0), address 0x00 ............................. 400Register 17: Ethernet PHY Management Register 1 – Status (MR1), address 0x01 .............................. 402Register 18: Ethernet PHY Management Register 2 – PHY Identifier 1 (MR2), address 0x02 ................. 404Register 19: Ethernet PHY Management Register 3 – PHY Identifier 2 (MR3), address 0x03 ................. 405Register 20: Ethernet PHY Management Register 4 – Auto-Negotiation Advertisement (MR4), address

0x04 ............................................................................................................................. 406Register 21: Ethernet PHY Management Register 5 – Auto-Negotiation Link Partner Base Page Ability

(MR5), address 0x05 ..................................................................................................... 408Register 22: Ethernet PHY Management Register 6 – Auto-Negotiation Expansion (MR6), address

0x06 ............................................................................................................................. 409Register 23: Ethernet PHY Management Register 16 – Vendor-Specific (MR16), address 0x10 ............. 410Register 24: Ethernet PHY Management Register 17 – Interrupt Control/Status (MR17), address

0x11 .............................................................................................................................. 412Register 25: Ethernet PHY Management Register 18 – Diagnostic (MR18), address 0x12 ..................... 414Register 26: Ethernet PHY Management Register 19 – Transceiver Control (MR19), address 0x13 ....... 415Register 27: Ethernet PHY Management Register 23 – LED Configuration (MR23), address 0x17 ......... 416Register 28: Ethernet PHY Management Register 24 –MDI/MDIX Control (MR24), address 0x18 .......... 417

Analog Comparators ................................................................................................................... 418Register 1: Analog Comparator Masked Interrupt Status (ACMIS), offset 0x00 .................................... 423Register 2: Analog Comparator Raw Interrupt Status (ACRIS), offset 0x04 ......................................... 424Register 3: Analog Comparator Interrupt Enable (ACINTEN), offset 0x08 ........................................... 425Register 4: Analog Comparator Reference Voltage Control (ACREFCTL), offset 0x10 ......................... 426

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Register 5: Analog Comparator Status 0 (ACSTAT0), offset 0x20 ....................................................... 427Register 6: Analog Comparator Status 1 (ACSTAT1), offset 0x40 ....................................................... 427Register 7: Analog Comparator Control 0 (ACCTL0), offset 0x24 ....................................................... 428Register 8: Analog Comparator Control 1 (ACCTL1), offset 0x44 ....................................................... 428

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Revision HistoryThe revision history table notes changes made between the indicated revisions of the LM3S6911data sheet.

Table 1. Revision History

DescriptionRevisionDate

Started tracking revision history.2550March 2008

2881April 2008 ■ The ΘJA value was changed from 55.3 to 34 in the "Thermal Characteristics" table in the OperatingCharacteristics chapter.

■ Bit 31 of the DC3 register was incorrectly described in prior versions of the datasheet. A reset of 1indicates that an even CCP pin is present and can be used as a 32-KHz input clock.

■ Values for IDD_HIBERNATE were added to the "Detailed Power Specifications" table in the "ElectricalCharacteristics" chapter.

■ The "Hibernation Module DC Electricals" table was added to the "Electrical Characteristics" chapter.

■ The TVDDRISE parameter in the "Reset Characteristics" table in the "Electrical Characteristics" chapterwas changed from a max of 100 to 250.

■ The maximum value on Core supply voltage (VDD25) in the "Maximum Ratings" table in the "ElectricalCharacteristics" chapter was changed from 4 to 3.

■ The operational frequency of the internal 30-kHz oscillator clock source is 30 kHz ± 50% (prior datasheetsincorrectly noted it as 30 kHz ± 30%).

■ A value of 0x3 in bits 5:4 of the MISC register (OSCSRC) indicates the 30-KHz internal oscillator is theinput source for the oscillator. Prior datasheets incorrectly noted 0x3 as a reserved value.

■ The reset for bits 6:4 of the RCC2 register (OSCSRC2) is 0x1 (IOSC). Prior datasheets incorrectly notedthe reset was 0x0 (MOSC).

■ Two figures on clock source were added to the "Hibernation Module":

– Clock Source Using Crystal

– Clock Source Using Dedicated Oscillator

■ The following notes on battery management were added to the "Hibernation Module" chapter:

– Battery voltage is not measured while in Hibernate mode.

– System level factors may affect the accuracy of the low battery detect circuit. The designer shouldconsider battery type, discharge characteristics, and a test load during battery voltagemeasurements.

■ A note on high-current applications was added to the GPIO chapter:

For special high-current applications, the GPIO output buffers may be used with the following restrictions.With the GPIO pins configured as 8-mA output drivers, a total of four GPIO outputs may be used to sinkcurrent loads up to 18 mA each. At 18-mA sink current loading, the VOL value is specified as 1.2 V.The high-current GPIO package pins must be selected such that there are only a maximum of two perside of the physical package or BGA pin group with the total number of high-current GPIO outputs notexceeding four for the entire package.

■ A note on Schmitt inputs was added to the GPIO chapter:

Pins configured as digital inputs are Schmitt-triggered.

■ The Buffer type on the WAKE pin changed from OD to - in the Signal Tables.

■ The "Differential Sampling Range" figures in the ADC chapter were clarified.

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Revision History

DescriptionRevisionDate

■ The last revision of the datasheet (revision 2550) introduced two errors that have now been corrected:

– The LQFP pin diagrams and pin tables were missing the comparator positive and negative inputpins.

– The base address was listed incorrectly in the FMPRE0 and FMPPE0 register bit diagrams.

■ Additional minor datasheet clarifications and corrections.

■ As noted in the PCN, three of the nine Ethernet LED configuration options are no longer supported: TXActivity (0x2), RX Activity (0x3), and Collision (0x4). These values for the LED0 and LED1 bit fields inthe MR23 register are now marked as reserved.

■ As noted in the PCN, the option to provide VDD25 power from external sources was removed. Use theLDO output as the source of VDD25 input.

■ As noted in the PCN, pin 41 (ball K3 on the BGA package) was renamed from GNDPHY to ERBIAS. A12.4-kΩ resistor should be connected between ERBIAS and ground to accommodate future devicerevisions (see “Functional Description” on page 375).

■ Additional minor datasheet clarifications and corrections.

2972May 2008

■ Corrected resistor value in ERBIAS signal description.

■ Additional minor datasheet clarifications and corrections.

3108July 2008

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About This DocumentThis data sheet provides reference information for the LM3S6911 microcontroller, describing thefunctional blocks of the system-on-chip (SoC) device designed around the ARM® Cortex™-M3core.

AudienceThis manual is intended for system software developers, hardware designers, and applicationdevelopers.

About This ManualThis document is organized into sections that correspond to each major feature.

Related DocumentsThe following documents are referenced by the data sheet, and available on the documentation CDor from the Luminary Micro web site at www.luminarymicro.com:

■ ARM® Cortex™-M3 Technical Reference Manual

■ ARM® CoreSight Technical Reference Manual

■ ARM® v7-M Architecture Application Level Reference Manual

■ Stellaris® Peripheral Driver Library User's Guide

■ Stellaris® ROM User’s Guide

The following related documents are also referenced:

■ IEEE Standard 1149.1-Test Access Port and Boundary-Scan Architecture

This documentation list was current as of publication date. Please check the Luminary Micro website for additional documentation, including application notes and white papers.

Documentation ConventionsThis document uses the conventions shown in Table 2 on page 20.

Table 2. Documentation Conventions

MeaningNotation

General Register Notation

APB registers are indicated in uppercase bold. For example, PBORCTL is the Power-On andBrown-Out Reset Control register. If a register name contains a lowercase n, it represents morethan one register. For example, SRCRn represents any (or all) of the three Software Reset Controlregisters: SRCR0, SRCR1 , and SRCR2.

REGISTER

A single bit in a register.bit

Two or more consecutive and related bits.bit field

A hexadecimal increment to a register's address, relative to that module's base address as specifiedin “Memory Map” on page 42.

offset 0xnnn

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About This Document

MeaningNotation

Registers are numbered consecutively throughout the document to aid in referencing them. Theregister number has no meaning to software.

Register N

Register bits marked reserved are reserved for future use. In most cases, reserved bits are set to0; however, user software should not rely on the value of a reserved bit. To provide softwarecompatibility with future products, the value of a reserved bit should be preserved across aread-modify-write operation.

reserved

The range of register bits inclusive from xx to yy. For example, 31:15 means bits 15 through 31 inthat register.

yy:xx

This value in the register bit diagram indicates whether software running on the controller canchange the value of the bit field.

Register Bit/FieldTypes

Software can read this field. The bit or field is cleared by hardware after reading the bit/field.RC

Software can read this field. Always write the chip reset value.RO

Software can read or write this field.R/W

Software can read or write this field. A write of a 0 to a W1C bit does not affect the bit value in theregister. A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged.

This register type is primarily used for clearing interrupt status bits where the read operationprovides the interrupt status and the write of the read value clears only the interrupts being reportedat the time the register was read.

R/W1C

Software can read or write a 1 to this field. A write of a 0 to a R/W1S bit does not affect the bitvalue in the register.

R/W1S

Software can write this field. A write of a 0 to a W1C bit does not affect the bit value in the register.A write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. Aread of the register returns no meaningful data.

This register is typically used to clear the corresponding bit in an interrupt register.

W1C

Only a write by software is valid; a read of the register returns no meaningful data.WO

This value in the register bit diagram shows the bit/field value after any reset, unless noted.Register Bit/FieldReset Value

Bit cleared to 0 on c