Features

• Multisourced2x5packagestyle• Operateswith62.5/125µmand50/125µmmultimode

fiber• Single+3.3Vpowersupply• Wavesolder andaqueouswash process compatibil-

ity• ManufacturedinanISO9001certifiedfacility• FullcompliancewithATMForum• UNISONETOC-3multimodefiberphysicallayerspeci-

fication• Fullcompliancewiththeopticalperformancerequire-

mentsoftheFDDIPMDstandard• Fullcompliancewiththeopticalperformancerequire-

mentsof100Base-FXversionofIEEE802.3u• RoHScompliant• PECLSignalDetectOutput• Temperaturerange: HFBR-5961LZ 0°Cto+70°C HFBR-5961ALZ -40°Cto+85°C HFBR-5961GZ 0°Cto+70°C(NoEMIshield) HFBR-5961AGZ -40°Cto+85°C(NoEMIshield)

Applications

• SONET/SDHequipmentinterconnect,OC-3/SDHSTM-1rate

• FastEthernet• MultimodefiberATMbackbonelinks

Description

TheHFBR-5961xxZtransceiverfromAvagoprovidesthesystemdesignerwithaproducttoimplementarangeofsolutionsformultimodefiberFastEthernetandSONETOC-3 (SDH STM-1) physical layers for ATM and otherservices.

Thistransceiverissuppliedintheindustrystandard2x5DIPstylewithanLCfiberconnectorinterfacewithanexternalconnectorshield.

Transmitter Section

The transmitter section of the HFBR-5961xxZ utilizesa 1300 nm InGaAsP LED. This LED is packaged in theopticalsubassemblyportionofthetransmittersection.ItisdrivenbyacustomsiliconICwhichconvertsdiffer-ential PECL logic signals, ECL referenced (shifted) to a+3.3Vsupply,intoananalogLEDdrivecurrent.

Receiver Section

The receiver section of the HFBR-5961xxZ utilizes anInGaAs PIN photodiode coupled to a custom silicontransimpedance preamplifier IC. It is packaged in theopticalsubassemblyportionofthereceiver.

This PIN/preamplifier combination is coupled to acustom quantizer IC which provides the final pulseshaping for the logic output and the Signal Detectfunction. The Data output is differential. The SignalDetect output is single ended. Both Data and SignalDetect outputs are PECL compatible, ECL referenced(shifted) to a +3.3 V power supply. The receiveroutputs,DataOutput andDataOut Bar,aresquelchedatSignalDetectdeassert. Thatis,whenthelightinputpowerdecreasestoatypical-38dBmorless,theSignalDetectdeasserts,ie.theSignalDetectoutputgoestoaPECL low state. This forces the receiver outputs, DataOutandDataOutBartogosteadyPECLlevelshighandlowrespectively.

HFBR-5961LZ/ALZ/GZ/AGZMultimode Small Form Factor (SFF) Transceivers for ATM, FDDI, Fast Ethernet and SONET OC-3/SDH STM-1 with LC connector

Data Sheet

2

Figure 1. Block Diagram

DATA OUT

SIGNALDETECT

DATA IN

QUANTIZER IC

LED DRIVER IC

PIN PHOTODIODEPRE-AMPLIFIERSUBASSEMBLY

LEDOPTICALSUBASSEMBLY

DATA OUT

DATA IN

LCRECEPTACLE

RX SUPPLY

TX SUPPLY

RX GROUND

TX GROUND

Package

The overall package concept for the Avago transceiverconsistsofthreebasicelements;thetwoopticalsubas-semblies,anelectricalsubassembly,andthehousingasillustratedintheblockdiagraminFigure1.

ThepackageoutlinedrawingandpinoutareshowninFigures2and5.Thedetailsofthispackageoutlineandpinoutarecompliantwiththemultisourcedefinitionofthe2x5DIP. The lowprofileof theAvagotransceiverdesigncomplieswiththemaximumheightallowedfortheLCconnectorovertheentirelengthofthepackage.

The optical subassemblies utilize a high-volumeassemblyprocesstogetherwithlow-costlenselementswhichresultinacosteffectivebuildingblock.

The electrical subassembly consists of a high volumemultilayer printed circuit board on which the ICs andvarious surface mounted passive circuit elements areattached.

The receiver section includes an internal shield for theelectrical and optical subassemblies to ensure highimmunitytoexternalEMIfields.

The outer housing including the LC ports is moldedof filled nonconductive plastic to provide mechani-calstrength. ThesolderpostsoftheAvagodesignareisolatedfromtheinternalcircuitofthetransceiver.

The transceiver is attached to a printed circuit boardwiththetensignalpinsandthetwosolderpostswhichexit the bottom of the housing. The two solder postsprovide the primary mechanical strength to withstandthe loads imposed on the transceiver by mating withtheLCconnectorfibercables.

3

Figure 2. Pin Out Diagram

TRANSMITTER DATA IN BARTRANSMITTER DATA INNCTRANSMITTER SIGNAL GROUNDTRANSMITTER POWER SUPPLY

RX TX

ooooo

12345

ooooo

109876

RECEIVER SIGNAL GROUNDRECEIVER POWER SUPPLY

SIGNAL DETECTRECEIVER DATA OUT BAR

RECEIVER DATA OUT

Top

View

Mounting

Studs/Solder

Posts

Pin 7 Transmitter Signal Ground VEE TX:

Directly connect this pin to the transmitter groundplane.

Pin 8 NC:

Noconnection.

Pin 9 Transmitter Data In TD+:

No internal terminations are provided. See recom-mendedcircuitschematic.

Pin 10 Transmitter Data In Bar TD-:

No internal terminations are provided. See recom-mendedcircuitschematic.

Mounting Studs/Solder Posts

The mounting studs are provided for transceiver me-chanical attachment to the circuit board. It is rec-ommended that the holes in the circuit board beconnectedtochassisground.

Application Information

TheApplicationsEngineeringgroupisavailabletoassistyouwiththetechnicalunderstandinganddesigntrade-offsassociatedwiththesetransceivers.YoucancontactthemthroughyourAvagosalesrepresentative.

The following information is provided to answer someofthemostcommonquestionsabouttheuseoftheseparts.

Transceiver Optical Power Budget versus Link Length

Optical Power Budget (OPB) is the available opticalpowerforafiberopticlinktoaccommodatefibercablelosses plus losses due to in-line connectors, splices,optical switches, and to provide margin for link agingand unplanned losses due to cable plant reconfigura-tionorrepair.

Avago LED technology has produced 1300 nm LEDdevices with lower aging characteristics than normallyassociated with these technologies in the industry.The industry convention is 1.5 dB aging for 1300 nmLEDs. The1300nmAvagoLEDsarespecifiedtoexpe-riencelessthan1dBofagingovernormalcommercialequipment mission life periods. Contact your Avagosalesrepresentativeforadditionaldetails.

Pin Descriptions:

Pin 1 Receiver Signal Ground VEE RX:

Directlyconnectthispintothereceivergroundplane.

Pin 2 Receiver Power Supply VCC RX:

Provide+3.3Vdcviatherecommendedreceiverpowersupply filter circuit. Locate the power supply filtercircuitascloseaspossibletotheVCCRXpin.

Pin 3 Signal Detect SD:

Normal optical input levels to the receiver result in alogic“1”output.

Lowoptical inputlevelstothereceiverresult inalogic“0”output.

This Signal Detect output can be used to drive a PECLinput on an upstream circuit, such as Signal DetectinputofLossofSignal-Bar.

Pin 4 Receiver Data Out Bar RD-:

No internal terminations are provided. See recom-mendedcircuitschematic.

Pin 5 Receiver Data Out RD+:

No internal terminations are provided. See recom-mendedcircuitschematic.

Pin 6 Transmitter Power Supply VCC TX:

Provide +3.3 V dc via the recommended transmitterpower supply filter circuit. Locate the power supplyfiltercircuitascloseaspossibletotheVCCTXpin.

4

Figure 3. Recommended Decoupling and Termination Circuits

o V

EE R

X

o V

CC R

X

o S

D

o R

D-

o R

D+

Z = 50 Ω

Z = 50 Ω

TERMINATE ATTRANSCEIVER INPUTS

Z = 50 Ω

Z = 50 Ω

10 9 8 7 6

SD

LVPECL

VCC (+3.3 V)

TERMINATE ATDEVICE INPUTS

LVPECL

VCC (+3.3 V)

PHY DEVICE

TD+

TD-

RD+

RD-

VCC (+3.3 V)

Z = 50 Ω

1 2 3 4 5

TD-

o

TD+

o

N/C

o

V EE T

X o

V CC T

X o 1 µH

C2

1 µH

C1

C3 10 µF

VCC (+3.3 V)

TX

RX

Notes:C1 = C2 = C3 = 10 nF or 100 nF* Loading of R1 is optional.

100 Ω

100 Ω

130 Ω 130 Ω

130 Ω 130 Ω

LVTTL

130 Ω

82 Ω

Recommended Handing Precautions

Avago recommends that normal status precautions betakeninthehandlingandassemblyofthesetransceiv-erstopreventdamagewhichmaybeinducedbyelec-trostatic discharge (ESD). The HFBR-5961xxZ series oftransceiversmeetMIL-STD-883CMethod3015.4Class2products.

Careshouldbeusedtoavoidshortingthereceiverdataor signal detect outputs directly to ground withoutpropercurrentlimitingimpedance.

Solder and Wash Process Compatibility

The transceivers are delivered with protective processplugsinsertedintotheLCreceptacle.

This process plug protects the optical subassembliesduringwavesolderandaqueouswashprocessing andactsasadustcoverduringshipping.

These transceivers are compatible with either industrystandardwaveorhandsolderprocesses.

Shipping Container

The transceiver is packaged in a shipping containerdesigned to protect it from mechanical and ESDdamageduringshipmentofstorage.

Board Layout - Decoupling Circuit, Ground Planes and Termi-nation Circuits

It is importanttotakecare inthe layoutofyourcircuitboard to achieve optimum performance from thesetransceivers. Figure 3 provides a good example of aschematic for a power supply decoupling circuit thatworks will with these parts, It is further recommend-edthatacontiguousgroundplanebeprovided in thecircuit board directly under the transceiver to providea low inductance ground for signal return current.This recommendation is in keeping with good highfrequencyboardlayoutpractices.Figures3and4showtworecommendedterminationschemes.

5

Board Layout - Hole Pattern

The Avago transceiver complies with the circuit board“CommonTransceiverFootprint”holepatterndefinedinthe original multisource announcement which definedthe2x5packagestyle. Thisdrawing isreproduced inFigure 6 with the addition of ANSI Y14.5M compliantdimensioning to be used as a guide in the mechani-cal layoutofyourcircuitboard. Figure6 illustratestherecommended panel opening and the position of thecircuitboardwithrespecttothispanel.

Figure 4. Alternative Termination Circuits

o V

EE R

Xo

VC

C RX

o S

D

o R

D-

o R

D+

Z = 50 Ω 130 Ω

VCC (+3.3 V)

10 nF

Z = 50 Ω

130 Ω

82 Ω 82 Ω

TERMINATE ATTRANSCEIVER INPUTS

Z = 50 Ω

Z = 50 Ω

10 9 8 7 6

SD

LVPECL

VCC (+3.3 V)

TERMINATE AT DEVICE INPUTS

LVPECL

VCC (+3.3 V)

PHY DEVICE

TD+

TD-

RD+

RD-

Z = 50 Ω

1 2 3 4 5

TD-

o

TD+

o

N/C

o

V EE T

X o

V CC T

X o

1 µH

C2

1 µH

C1

C310 µF

VCC (+3.3 V)TX

RX

Note:C1 = C2 = C3 = 10 nF or 100 nF* Loading R1 is optional.

10 nF

130 Ω

82 Ω

VCC (+3.3 V)

130 Ω

82 Ω

VCC (+3.3 V)

10 nF

LVTTL

82 Ω

130 Ω

Regulatory Compliance

These transceiver products are intended to enablecommercial system designers to develop equipmentthat complies with the various international regula-tionsgoverningcertificationofInformationTechnologyEquipment. See the Regulatory Compliance Table fordetails. Additional information is available from yourAvagosalesrepresentative.

6

ALL DIMENSIONS IN MILIMETERS(INCHES)

Figure 5. Package Outline Drawing

7

Electrostatic Discharge (ESD)

There are two design cases in which immunity to ESDdamageisimportant.

Thefirstcaseisduringhandlingofthetransceiverpriorto mounting it on the circuit board. It is important tousenormalESDhandlingprecautionsforESDsensitivedevices. These precautions include using groundedwrist straps,workbenches,andfloormats inESDcon-trolledareas.

Thesecondcase toconsider is staticdischarges to theexterior the equipment chassis containing the trans-ceiver parts. To the extent that the LC connector isexposedtotheoutsideoftheequipmentchassisitmaybe subject to whatever ESD system level test criteriathattheequipmentisintendedtomeet.

Figure 6. Recommended Board Layout Hole Pattern

2.29(.090)

15.24(.600) MIN. PITCH

14.22 ± .10(.560 ± .004)A

A

0.81 ± .10(.032 ± .004)

20 x Ø

1.40 ± .10(.055 ± .004)

4 x Ø (NOTE 5) SEE DETAIL A

13.34(.525)

12.16(.479) 15.24

(.600)

7.59(.299)

10.16(.400)

4.57(.180)

7.11(.280)

1.78(.070)

9 X

3.56(.140)

5 4 3 2 1

6 7 8 9 10

SEE NOTE 3

8.89(.350)

10.16 ± .10(.400 ± .004)

TOP OF PCB

SECTION A - A

A

+ 1.50- 0(+.059)(- .000)

1.00

(.039)

+ 0- 0.75(+.000)(- .030)

15.75

(.620)

DETAIL B (4 x)

1.039

1.8.071

DETAIL A (3 x)

3(.118)

2 x Ø MAX. (AREA FOR EYELET'S)

6(.236)

1.40 ± .10(.055 ± .004)

2 x Ø (NOTE 4)

3(.118)

25.75(1.014)

MIN. PITCH

SEE DETAIL B

Electromagnetic Interference (EMI)

Mostequipmentdesignsutilizingthishighspeedtrans-ceiverfromAvagowillberequiredtomeettherequire-ments of FCC in the United States, CENELEC EN55022(CISPR22)inEuropeandVCCIinJapan.

Thisproductissuitableforuseindesignsrangingfromadesktopcomputerwithasingletransceivertoacon-centrator or switch product with a large number oftransceivers.

NOTES:1. THISPAGEDESCRIBESTHERECOMMENDEDCIRCUITBOARDLAYOUTANDFRONTPANELOPENINGSFORSFFTRANSCEIVERS.2. THEHATCHEDAREASAREKEEP-OUTAREASRESERVEDFORHOUSINGSTANDOFFS.NOMETALTRACESALLOWEDINKEEP-OUTAREAS.3. THISDRAWINGSHOWSEXTRAPINHOLESFOR2x6PINAND2x10PINTRANSCEIVERS.THESEEXTRAHOLESARENOTREQUIREDFORHFBR-5961xxZANDOTHER

2x5PINSFFMODULES.4. HOLESFORMOUNTINGSTUDSMUSTNOTBETIEDTOSIGNALGROUNDBUTMAYBETIEDTOCHASSISGROUND.5. HOLES FOR HOUSING LEADS OPTIONAL AND NOT REQUIRED FOR HFBR-5961L/HFBR-5961G. IF NEEDED IN FUTURE,THESE HOLES MUST BETIEDTO SIGNAL

GROUND.6. ALLDIMENSIONSAREINMILLIMETERS(INCHES).

8

Regulatory Compliance Table

Feature Test Method PerformanceElectrostaticDischarge(ESD)totheElectricalPins

MIL-STD-883C MeetsClass2(2000to3999Volts).Withstandupto2200Vappliedbetweenelectricalpins.

ElectrostaticDischarge(ESD)totheLCRecep-tacle

VariationofIEC61000-4-2 Typicallywithstandatleast25kVwithoutdamagewhentheLCconnectorreceptacleiscontactedbyaHumanBodyModelprobe.

ElectromagneticInter-ference(EMI)

FCCClassBCENELECCEN55022VCCIClass2

Transceiverstypicallyprovidea10dBmargintothenotedstandardlimitswhentestedatacertifiedtestrangewiththetransceivermountedtoacircuitcardwithoutachassisenclosure.

Immunity VariationofIEC61000-4-3 Typicallyshownomeasurableeffectfroma10V/mfieldsweptfrom80to450MHzappliedtothetransceiverwhenmountedtoacircuitcardwithoutachassisenclosure.

EyeSafety AELClass1EN60825-1(+A11) CompliantperAvagotestingundersinglefaultconditions.TUVCertification-R02071015

ComponentRecogni-tion

UnderwritersLaboratoriesandCanadianStandardsAssociationJointComponentRecognitionforInforma-tionTechnologyEquipmentincludingElectricalBusinessEquipment

ULFile#:E173874

200

100

l C – TRANSMITTER OUTPUT OPTICAL RISE/FALL TIMES – ns

1280 1300 1320

180

160

140

120

13601340

∆λ -

TR

AN

SMIT

TER

OU

TPU

T O

PTIC

AL

SPEC

TRA

L W

IDTH

(FW

HM

) - n

m 1.0

1.5

2.5

3.0

2.0

HFBR-5961xxZ TRANS-MITTER TEST RESULTSOF λC, ∆λ AND tr/f ARE

1260

tr/f – TRANSMITTEROUTPUT OPTICAL RISE/FALL TIMES – ns

3.0

CORRELATED AND COMPLYWITH THE ALLOWED SPECTRAL WIDTH AS AFUNCTION OF CENTERWAVELENGTH FORVARIOUS RISE ANDFALL TIMES.

0

1

2

3

4

5

6

-3 -2 -1 0 1 2 3

EYE SAMPLING TIME POSITION (ns)

REL

ATI

VE IN

PUT

OPT

ICA

L PO

WER

(dB

)

CONDITIONS:1. TA = +25 C2. VCC = 3.3 V dc3. INPUT OPTICAL RISE/ FALL TIMES = 2.1/1.9 ns.4. INPUT OPTICAL POWER IS NORMALIZED TO CENTER OF DATA SYMBOL.5. NOTE 15 AND 16 APPLY.

Figure 8. Relative Input Optical Power vs Eye Sampling Time Position

Figure 7. Transmitter Output Optical Spectral Width (FWHM) vs. Transmit-ter Output Optical Center Wavelength and Rise/Fall Times

Immunity

Equipment utilizing these transceivers will be subjecttoradio-frequencyelectromagneticfieldsinsomeenvi-ronments. Thesetransceivershaveahighimmunitytosuchfields.

For additional information regarding EMI, susceptibil-ity, ESD and conducted noise testing procedures andresults. Refer to Application Note 1166, MinimizingRadiated Emissions of High-Speed Data Communica-tionsSystems.

Transceiver Reliability and Performance Qualification Data

The2x5transceivershavepassedAvagoreliabilityandperformance qualification testing and are undergoingongoing quality and reliability monitoring. Details areavailablefromyourAvagosalesrepresentative.

These transceivers are manufactured at the AvagoSingapore location which is an ISO 9001 certifiedfacility.

Applications Support Material

ContactyourlocalAvagoComponentFieldSalesOfficeforinformationonhowtoobtainPCBlayoutsandeval-uationboardsforthe2x5transceivers.

9

Absolute Maximum RatingsStressesinexcessoftheabsolutemaximumratingscancausecatastrophicdamagetothedevice.Limitsapplytoeachparameter in isolation,allotherparametershavingvalueswithintherecommendedoperatingconditions. Itshouldnotbeassumedthatlimitingvaluesofmorethanoneparametercanbeappliedtotheproductatthesametime.Exposuretotheabsolutemaximumratingsforextendedperiodscanadverselyaffectdevicereliability.

Parameter Symbol Minimum Typical Maximum Units NotesStorageTemperature TS -40 +100 °C

LeadSolderingTemperature TSOLD +260 °C

LeadSolderingTime tSOLD 10 sec

SupplyVoltage VCC -0.5 3.63 V

DataInputVoltage VI -0.5 VCC V

DifferentialInputVoltage(p-p) VD 2.0 V 1

OutputCurrent IO 50 mA

Recommended Operating Conditions

Parameter Symbol Minimum Typical Maximum Units NotesCaseOperatingTemperatureHFBR-5961LZ/GZHFBR-5961ALZ/AGZ

TCTC

0-40

+70+85

°C°C

SupplyVoltage VCC 2.97 3.3 3.63 V

DataInputVoltage-Low VIL-VCC -1.810 -1.475 V

DataInputVoltage-High VIH-VCC -1.165 -0.880 V

DataandSignalDetectOutputLoad RL 50 W 2

DifferentialInputVoltage(p-p) VD 0.800 V

Transmitter Electrical CharacteristicsHFBR-5961LZ/GZ(TC=0°Cto+70°C,VCC=2.97Vto3.63V)HFBR-5961ALZ/AGZ(TC=-40°Cto+85°C,VCC=2.97Vto3.63V)

Parameter Symbol Minimum Typical Maximum Units NotesSupplyCurrent ICC 110 175 mA 3

PowerDissipation PDISS 0.4 0.64 W 5a

DataInputCurrent-Low IIL -350 -2 µA

DataInputCurrent-High IIH 18 350 µA

10

Receiver Electrical CharacteristicsHFBR-5961LZ/AGZ(TC=0°Cto+70°C,VCC=2.97Vto3.63V)HFBR-5961ALZ/AGZ(TC=-40°Cto+85°C,VCC=2.97Vto3.63V)

Parameter Symbol Minimum Typical Maximum Units NotesSupplyCurrent ICC 65 120 mA 4

PowerDissipation PDISS 0.225 0.44 W 5b

DataOutputVoltage-Low VOL-VCC -1.840 -1.620 V 6

DataOutputVoltage-High VOH-VCC -1.045 -0.880 V 6

DataOutputRiseTime tr 0.35 2.2 ns 7

DataOutputFallTime tf 0.35 2.2 ns 7

SignalDetectOutputVoltage-Low VOL-VCC -1.840 -1.620 V 6

SignalDetectOutputVoltage-High VOH-VCC -1.045 -0.880 V 6

SignalDetectOutputRiseTime tr 0.35 2.2 ns 7

SignalDetectOutputFallTime tf 0.35 2.2 ns 7

PowerSupplyNoiseRejection PSNR 50 mV

Transmitter Optical CharacteristicsHFBR-5961LZ/GZ(TC=0°Cto+70°C,VCC=2.97Vto3.63V)HFBR-5961ALZ/AGZ(TC=-40°Cto+85°C,VCC=2.97Vto3.63V)

Parameter Symbol Minimum Typical Maximum Units NotesOutputOpticalPowerBOL62.5/125µm,NA=0.275FiberEOL

PO -19-20

-15.7 -14 dBmavg 8

OutputOpticalPowerBOL50/125µm,NA=0.20FiberEOL

PO -22.5-23.5

-14 dBmavg 8

OpticalExtinctionRatio 0.02-47

0.2-27

%dB 9

OutputOpticalPoweratLogicLow0State PO(“0”) -45 dBmavg 10

CenterWavelength lC 1270 1308 1380 nm 23,Figure7

SpectralWidth-FWHMSpectralWidth-RMS

Dl 14763 nm 11,23Figure7

OpticalRiseTime tr 0.6 2.1 3.0 ns 12,23Figure7

OpticalFallTime tf 0.6 1.9 3.0 ns 12,23Figure7

SystematicJitterContributedbytheTransmitterOC-3

SJ 0.4 1.2 nsp-p 13a

DutyCycleDistortionContributedbytheTransmitterFE

DCD 0.36 0.6 nsp-p 13b

DataDependentJitterContributedbytheTransmitterFE

DDJ 0.07 0.6 nsp-p 13c

RandomJitterContributedbytheTransmitterOC-3FE

RJ 0.10.1

0.520.69

nsp-p 14a14b

11

Receiver Optical and Electrical CharacteristicsHFBR-5961LZ/GZ(TC=0°Cto+70°C,VCC=2.97Vto3.63V)HFBR-5961ALZ/AGZ(TC=-40°Cto+85°C,VCC=2.97Vto3.63V)

Parameter Symbol Minimum Typical Maximum Units NotesInputOpticalPoweratminimumatWindowEdgeOC-3FE

PINMIN(W)-30-31

dBmavg 15a,Figure815b

InputOpticalPoweratEyeCenterOC-3FE

PINMIN(C) -31-31.8

dBmavg 16a,Figure816b

InputOpticalPowerMaximumOC-3FE

PINMAX -14-14

dBmavg 15a15b

OperatingWavelength l 1270 1380 nm

SystematicJitterContributedbytheReceiverOC-3

SJ 0.2 1.2 nsp-p 17a

DutyCycleDistortionContributedbytheReceiverFE

DCD 0.08 0.4 nsp-p 17b

DataDependentJitterContributedbytheReceiverFE DDJ 0.07 1.0 nsp-p 17c

RandomJitterContributedbytheReceiverOC-3FE

RJ 0.30.3

1.912.14

nsp-p 18a18b

SignalDetect-AssertedOC-3FE

PA PD+1.5dB -31-33

dBmavg 19

SignalDetect-Deasserted PD -45 dBmavg 20

SignalDetect-Hysteresis PA-PD 1.5 dB

SignalDetectAssertTime(offtoon) 0 2 100 µs 21

SignalDetectDeassertTime(ontooff) 0 5 100 µs 22

Notes:1. ThisisthemaximumvoltagethatcanbeappliedacrosstheDifferentialTransmitterDataInputstopreventdamagetotheinputESDprotec-

tioncircuit.2. Theoutputsareterminatedwith50WconnectedtoVCC–2V.3. ThepowersupplycurrentneededtooperatethetransmitterisprovidedtodifferentialECLcircuitry.Thiscircuitrymaintainsanearlyconstant

current flow from the power supply. Constant current operation helps to prevent unwanted electrical noise from being generated andconductedoremittedtoneighboringcircuitry.

4. Thisvalueismeasuredwiththeoutputsterminatedinto50WconnectedtoVCC–2VandanInputOpticalPowerlevelof–14dBmaverage.5a.Thepowerdissipationofthetransmitteriscalculatedasthesumoftheproductsofsupplyvoltageandcurrent.5b.Thepowerdissipationofthereceiveriscalculatedasthesumoftheproductsofsupplyvoltageandcurrents,minusthesumoftheproducts

oftheoutputvoltagesandcurrents.6. ThisvalueismeasuredwithrespecttoVCCwiththeoutputterminatedinto50WconnectedtoVCC-2V.7. Thedataoutputriseandfalltimesaremeasuredbetween20%and80%levelswiththeoutputconnectedtoVCC–2Vthrough50W.8. Theseopticalpowervaluesaremeasured withthefollowingconditions: TheBeginningoflife(BOL)totheEndofLife(EOL)opticalpowerdegradationistypically1.5dBpertheindustryconventionforlongwave-

lengthLEDs.TheactualdegradationobservedinAvago’s1300nmLEDproductsis<1dB,asspecifiedinthisdatasheet.Overthespecifiedoperatingvoltageandtemperatureranges.With25MBd(12.5MHzsquare-wave),inputsignal.Attheendofonemeterofnotedopticalfiberwithcladdingmodesremoved. Theaveragepowervaluecanbeconvertedtoapeakpowervaluebyadding3dB.Higheroutputopticalpowertransmittersareavailableonspecialrequest.PleaseconsultwithyourlocalAvagosalesrepresentativeforfurtherdetails.

12

9. TheExtinctionRatioisameasureofthemodulationdepthoftheopticalsignal..Thedata“0”outputopticalpoweriscomparedtothedata“1”peakoutputopticalpowerandexpressedasapercentage.Withthetransmitterdrivenbya25MBd(12.5MHzsquare-wave)inputsignal,theaverageopticalpowerismeasured.Thedata“1”peakpoweristhencalculatedbyadding3dBtothemeasuredaverageopticalpower.Thedata“0”outputopticalpowerisfoundbymeasuringtheopticalpowerwhenthetransmitterisdrivenbyalogic“0”input.Theextinctionratioistheratiooftheopticalpoweratthe“0”levelcomparedtotheopticalpoweratthe“1”levelexpressedasapercentageorindecibels.

10.ThetransmitterwillprovidethislowlevelofOutputOpticalPowerwhendrivenbyaLogic“0”input.Thiscanbeusefulinlinktroubleshoot-ing.

11.TherelationshipbetweenFullWidthHalfMaximumandRMSvaluesforSpectralWidthisderivedfromtheassumptionofaGaussianshapedspectrumwhichresultsina2.35XRMS=FWHMrelationship.

12.Theopticalriseandfalltimesaremeasuredfrom10%to90%whenthetransmitterisdrivenbya25MBd(12.5MHzsquare-wave)inputsignal.The ANSI T1E1.2 committee has designated the possibility of defining an eye pattern mask for the transmitter optical output as an item forfurtherstudy.Avagowill incorporatethis requirement intothespecifications for theseproducts if it isdefined.The HFBR-59XXLproductstypicallycomplywiththetemplaterequirementsofCCITT(nowITU-T)G.957Section3.2.5,Figure5fortheSTM-1rate,excludingtheopticalreceiverfilternormallyassociatedwithsinglemodefibermeasurementswhichisthelikelysourcefortheANSIT1E1.2committeetofollowinthismatter.

13a.SystematicJittercontributedbythetransmitterisdefinedasthecombinationofDutyCycleDistortionandDataDependentJitter.System-aticJitterismeasuredat50%thresholdusinga155.52MBd(77.5MHzsquare-wave),223-1pseudorandomdatapatterninputsignal.

13b.DutyCycleDistortioncontributedbythetransmitterismeasuredatthe50%thresholdoftheopticaloutputsignalusinganIDLELineState,125MBd(62.5MHzsquare-wave),inputsignal.

13c.DataDependentJittercontributedbythetransmitterisspecifiedwiththeFDDItestpatterndescribedinFDDIPMDAnnexA.5.14a.RandomJittercontributedbythetransmitterisspecifiedwitha155.52MBd(77.5MHzsquare-wave)inputsignal.14b.RandomJittercontributedbythetransmitterisspecifiedwithanIDLELineState,125MBd(62.5MHzsquare-wave),inputsignal.SeeApplica-

tionInformation-TransceiverJitterPerformanceSectionofthisdatasheetforfurtherdetails.15a.ThisspecificationisintendedtoindicatetheperformanceofthereceiversectionofthetransceiverwhenInputOpticalPowersignalcharacter-

isticsarepresentperthefollowingdefinitions.TheInputOpticalPowerdynamicrangefromtheminimumlevel(withawindowtime-width)tothemaximumlevelistherangeoverwhichthereceiverisguaranteedtoprovideoutputdatawithaBitErrorRate(BER)betterthanorequalto1x10-10.

AttheBeginningofLife(BOL)overthespecifiedoperatingtemperatureandvoltageranges23inputisa155.52MBd,2-1PRBSdatapatternwith72“1”sand72“0”sinsertedpertheCCITT(nowITU-T)recommendationG.958AppendixI.

Receiverdatawindowtime-widthis1.23nsorgreaterfortheclockrecoverycircuittooperatein.Theactualtestdatawindowtime-widthissettosimulatetheeffectofworstcaseopticalinputjitterbasedonthetransmitterjittervaluesfromthespecificationtables.Thetestwindowtime-widthisHFBR-5961L3.32ns.

Transmitteroperatingwitha155.52MBd,77.5MHzsquare-wave,inputsignaltosimulateanycross-talkpresentbetweenthetransmitterandreceiversectionsofthetransceiver.

15b.ThisspecificationisintendedtoindicatetheperformanceofthereceiversectionofthetransceiverwhenInputOpticalPowersignalchar-acteristicsarepresentperthefollowingdefinitions.TheInputOpticalPowerdynamicrangefromtheminimumlevel(withawindowtime-width)tothemaximumlevelistherangeoverwhichthereceiverisguaranteedtoprovideoutputdatawithaBitErrorRate(BER)betterthanorequalto2.5x10-10.• AttheBeginningofLife(BOL)• Overthespecifiedoperatingtemperatureandvoltageranges• InputsymbolpatternistheFDDItestpatterndefinedinFDDIPMDAnnexA.5with4B/5BNRZIencodeddatathatcontainsadutycyclebase-

linewandereffectof50kHz.Thissequencecausesanearworstcaseconditionforinter-symbolinterference.• Receiver data window time-width is 2.13 ns or greater and centered at mid-symbol. This worst case window time-width is the minimum

allowedeye-openingpresentedtotheFDDIPHYPM_Dataindicationinput(PHYinput)pertheexampleinFDDIPMDAnnexE.Thisminimumwindowtime-widthof2.13nsisbasedupontheworstcaseFDDIPMDActiveInputInterfaceopticalconditionsforpeak-to-peakDCD(1.0ns),DDJ(1.2ns)andRJ(0.76ns)presentedtothereceiver.

TotestareceiverwiththeworstcaseFDDIPMDActiveInputjitterconditionrequiresexactingcontroloverDCD,DDJandRJjittercomponentsthatisdifficulttoimplementwithproductiontestequipment.ThereceivercanbeequivalentlytestedtotheworstcaseFDDIPMDinputjitterconditionsandmeettheminimumoutputdatawindowtime-widthof2.13ns.Thisisaccomplishedbyusinganearlyidealinputopticalsignal(noDCD,insignificantDDJandRJ)andmeasuringforawiderwindowtime-widthof4.6ns.Thisispossibleduetothecumulativeeffectofjittercomponentsthroughtheirsuperposition(DCDandDDJaredirectlyadditiveandRJcomponentsarermsadditive).Specifically,whenanearlyidealinputopticaltestsignalisusedandthemaximumreceiverpeak-to-peakjittercontributionsofDCD(0.4ns),DDJ(1.0ns),andRJ(2.14ns)exist,theminimumwindowtime-widthbecomes8.0ns-0.4ns-1.0ns-2.14ns=4.46ns,orconservatively4.6ns.Thiswiderwindowtime-widthof 4.6 ns guarantees the FDDI PMD Annex E minimum window time-width of 2.13 ns under worst case input jitter conditions to the Avagoreceiver.• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5 MHz square-wave), input signal to simulate any cross-talk present

betweenthetransmitterandreceiversectionsofthetransceiver.16a.AllconditionsofNote15aapplyexceptthatthemeasurementismadeatthecenterofthesymbolwithnowindowtime-width.16b.AllconditionsofNote15bapplyexceptthatthemeasurementismadeatthecenterofthesymbolwithnowindowtime-width.17a. SystematicJittercontributedbythereceiverisdefinedasthecombinationofDutyCycleDistortionandDataDependentJitter.System-

aticJitterismeasuredat50%thresholdusinga155.52MBd(77.5MHzsquare-wave),223-1psuedorandomdatapatterninputsignal.17b.DutyCycleDistortioncontributedbythereceiverismeasuredatthe50%thresholdoftheelectricaloutputsignalusinganIDLELineState,

125MBd(62.5MHzsquare-wave),inputsignal.Theinputopticalpowerlevelis-20dBmaverage.17c.DataDependentJittercontributedby thereceiver isspecifiedwiththeFDDIDDJtestpatterndescribed intheFDDIPMDAnnexA.5.The

inputopticalpowerlevelis-20dBmaverage.18a.RandomJittercontributedbythereceiverisspecifiedwitha155.52MBd(77.5MHzsquare-wave)inputsignal.18b.Random Jitter contributed by the receiver is specified with an IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal.The input

opticalpowerlevelisatmaximum“PINMin.(W)”.SeeApplicationInformation-TransceiverJitterSectionforfurtherinformation.

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.Data subject to change. Copyright © 2005-2009 Avago Technologies. All rights reserved. AV02-0820EN - April 24, 2009

Ordering Information

1300 nm LED (Operating Case Temperature 0 to +70 °C)

HFBR-5961LZ/HFBR-5961GZ

1300 nm LED (Operating Case Temperature -40 to +85 °C)

HFBR-5961ALZ/HFBR-5961AGZ

19.Thisvalueismeasuredduringthetransitionfromlowtohighlevelsofinputopticalpower.20.Thisvalueismeasuredduringthetransitionfromhightolowlevelsofinputopticalpower.AtSignalDetectDeassert,thereceiveroutputs

DataOutandDataOutBargotosteadyPECLlevelsHighandLowrespectively.21.TheSignalDetectoutputshallbeassertedwithin100usafterastepincreaseoftheInputOpticalPower.22.Signal detect output shall be de-asserted within 350 µs after a step decrease in the Input Optical Power. At Signal Detect Deassert, the

receiveroutputsDataOutandDataOutBargotosteadyPECLlevelsHighandLowrespectively.23.TheHFBR-5961Ltransceivercomplieswiththerequirementsforthetrade-offsbetweencenterwavelength,spectralwidth,andrise/falltimes

showninFigure7.ThisfigureisderivedfromtheFDDIPMDstandard(ISO/IEC9314-3:1990andANSIX3.166-1990)perthedescriptioninANSIT1E1.2Revision3.TheinterpretationofthisfigureisthatvaluesofCenterWavelengthandSpectralWidthmustliealongtheappropriateOpticalRise/FallTimecurve.