cycle time and throughput rate modelling … time and throughput rate modelling study through the...

Sensors & Transducers, Vol. 165, Issue 2, February 2014, pp. 213-220

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© 2014 by IFSA Publishing, S. L. http://www.sensorsportal.com

Cycle Time and Throughput Rate Modelling Study through the Simulation Platform

1 Fei Xiong, 2 Jin Yao

1 Business School of Sichuan University, Chengdu, P. R. China 2 Manufacturing Science and Engineering School of Sichuan University, Chengdu, P. R. China

Tel.: +86 13880925111 E-mail: [email protected], [email protected]

Received: 27 January 2014 /Accepted: 21 February 2014 /Published: 28 February 2014 Abstract: The shorter cycle time (CT) and higher throughput rate (TH) are primary goals of the industry, including sensors and transducer factory. The common way of cycle time reduction is to reduce WIP, but such action may also reduce throughput. This paper will show one practical healthy heuristic algorithm based on tool time modelling to balance both the CT and the TH. This algorithm considers the factors that exist in the work in process (WIP) and its constrains in modules of the factory. One computer simulation platform based on a semiconductor factory is built to verify this algorithm. The result of computing simulation experiments suggests that the WIP level calculated by this algorithm can achieve the good balance of CT and TH. Copyright © 2014 IFSA Publishing, S. L. Keywords: Work in process (WIP), Average utilization (AU), Cycle time, Throughput rate, Computing simulation. 1. Introduction

The cycle time and throughput are quite important daily business operation indicators in industry. The work in process (WIP) is the parameter to link the cycle time and the throughput. Many WIP control policies have been proved to be effective in the manufacturing system. And the WIP level estimation method is critical to apply all kinds of control policies. Many methods have been used to do the related research as follows: 1.1. Toyota Approach

Monden [1] originally summarized the Toyota approach for determining the appropriate number of kanbans at a workstation as follow:

(1 )N D L , (1)

where N is the number of kanbans, D is the average demand in units of standard containers, L is the lead time, is the safety factor.

Although it was successfully applied in Toyota factory, it had some limitations. In the one hand, the L and depend on subjective judgment which needs to be defined by experiments. In another hand, it is not well-suited to the evolution environment, when the demand changes or workstation capacity increase, the L and can’t be adjusted quickly and accurately.

1.2. Simulation Method

Simulation technology is widely used to predict the production performance [2]. Miller [3] used a

Article number P_RP_0075

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simulation model to estimate the WIP level under the fixed WIP control policy. Philipoom et al. [4] used simulation to determine the leading time at the workstations and thereby the number of kanbans required at each station to prevent backorders in a dynamic production environment. However some drawbacks also showed in this method. Firstly, only when the simulation model contains enough information which can represent the special system that it can be used. Secondly build and debug a simulation model cost a lot of time and only works for a special system. At last, the simulation model usually needs all kinds of data which is usually hard to obtain in actually manufacturing system. 1.3. Queuing Theory

Queuing theory is an important operation method which is usually used in manufacturing system. Lin and Lee [5] proposed a queuing network-based algorithm to determine the total standard WIP level so that the Fixed-WIP release control policy can apply. Li Xue-Min, Tian Qing and Zhang Zi-Yu [6] studied how to determine the WIP for an optical communication component production line and the problem is modeled by queuing models [M/M/s]:[∞/∞/FCFS]and [M/M/s]:[N/∞/FCFS]. However all of two used the ideal queuing model which is quite differently with actual production system. Normally product arrival time interval and processing time are not exponential distribution. Jiang Shu-Yu [7] proposed a heuristic algorithm based ConWIP (Consistent WIP) release control policy and G/G/m queuing network model. Simulation result shows that it can help in getting good combination of cycle time and throughput, but the algorithm need quite a lot of data (arrival rate and interarrival time for every wafer, arrival rate and interarrival time for every workstation) which greatly increase the burden of the people.

1.4. Other Methods

Mathematical modeling: Zhang Jie [8] proposed the mathematic model for optimizing inventory for WIP among operation by investigating the impact of facility states and process parameters upon the WIP inventory. Neural networks become very popular in various applications and are successfully implemented in manufacturing processes [9-11] developed algorithm integrated an artificial neural network (ANN) and the sequential quadratic programming (SQP) method to optimize the WIP Level. Zhao Zhou and Nakashima [12] proposed a network production system which set a public WIP area where WIP level is controlled by kanbans. Papadopoulos and Vidalis [13] proposed a heuristic algorithm to find the optimal buffer allocation to minimize the average WIP inventory. Lodding [14] established WIP control loops between manufacturing work centers to achieve the short and

reliable lead times. However these methods are either incomplete or difficult to determine effective objective functions.

Hence, in order to get higher throughput rate and shorter cycle time in manufacturing, a practical heuristic algorithm based on average utilization of each workstation was proposed. Refer to the Little’s Law in factory physics and tool IE time modelling, then one algorithm is established creatively to the relationship between the WIP level and average utilization in each workstation in front of bottleneck workstation. The remainder of the article is organized as follows. Section 2 will introduce the manufacturing system production, WIP control policy and general assumption. Section 3 will describe the detailed heuristic algorithm. Section 4 will simulate the CT and THin the production environment. Section 5 will shoe you the simulation result to validate the algorithm for this study. 2. Process Description and Assumptions

In this paper, one semiconductor assembly and test manufacturing (ATM) environment is as our research subject. Usually, semiconductor products are released into the production line by lot (normally 2625 units), every kind of product has its own processing route but most of them are similar. The production mode is as Fig. 1 showed: There are WIP buffer areas between the workstations in which some products would be classified and others wouldn’t. Workstations usually have a series of operations which are including machines. Based on different technologies, some machines can only process specific products and others can process all the products.

Fig. 1. ATM process mode diagrammatic sketch.

The ATM manufacturing uses the ConWIP lot release strategy. Based on the TOC theory, the bottleneck workstation must be paid more attention. The primary goal of the production scheduling is to make sure the machines in bottleneck workstation fully run. Hence the ConWIP control policy is


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applied in front of the bottleneck station as shown in Fig. 2.

Fig. 2. ConWIP in ATM system.

Actually the ATM system is quite complex because of complex process and steps. Meanwhile all kinds of discrete events would inevitably happen regularly or randomly such as machine preventive maintenance or unscheduled down which would increase the instability of the ATM system.

To achieve the goal of this study we give some general assumption about the ATM system as follows: Two products are considered in our study, which

has similar processing route but different processing time in each workstation.

The first-in-first-out (FIFO) dispatch rule is assumed to be executed at each workstation.

Product is processed by lot (standard 2625 units). Average process time is used which is calculated

by EUPH (effective units per hour) from the company. The machine unscheduled down time is expressed by MTTR (mean time to repair) and MTBF (mean time between failures).

Enough material and workers. From the Fig. 2 we know that the WIP at the

workstations in front of bottleneck station is what we need to study. The next section we would give out the detailed introduction. 3. Heuristic Algorithm

The Little’s Law in factory physics demonstrates the simple relationship among work in process (WIP), throughput rate (TH) and cycle time (CT) as follows:

WIP CT TH (2)

For every production stage, once the production task is defined the throughput rate is accordingly defined. So we consider the throughput rate as a designed parameter. Actually in real production activity throughput rate is a quite important target which needs to be set before production begins and to be reviewed regularly. After throughput rate is fixed,

WIP level and CT can be directly connected for each other. And we can estimate the proper health WIP level in the assembly and test production line by the time analysis and evaluation.

Normally we can divide the work in process in production line into three parts: the special WIP (hold lot and yield loss), the processing WIP (lot which is being processed) and the waiting WIP (lots which waiting in buffer area). The special WIP can be reduced by improving the quality control only, so we can estimate it by the empirical data. The processing WIP and waiting WIP can be estimated by utilization of machine because of their relationships with machine states.

In order to connect WIP level with the time study, this paper uses the machine time modelling as Fig. 3. This model gives out the time budget percentages for all the machine states.

Fig. 3. Machine time model.

Some related parameter explanations in Fig. 3 are listed as follows:

STD – scheduled down time (such as preventive maintenance), schedule down time percentage of workstation i is defined as P1i.

USTD – unscheduled down time (such as machine breakdown), unscheduled down time percentage of workstation i is defined as P2i.

EE – engineering experiment time (Engineer do experiments on machine), engineer experiment time percentage of workstation i is defined as P3i.

IDLE – idle time (caused by lack of material or worker) ，idle time percentage of workstation i is defined as P4i.

PPT – Pure process time, pure process time percentage of workstation i is defined as Ui. Ui is the machine average utilization of the workstation i.

All of the items above cost all the time, so P1i+P2i+P3i+P4i+Ui=100 %. In order to give out the heuristic algorithm, some parameters from the assembly and test factory are also list as follows:

EUPH – effective units per hour, effective units per hour on one machine in workstation is defined as Ei.

TH – bottleneck throughput rate which is defined as .

M – machine number in workstation, machine number in workstation i is defined as Mi.


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N – workstation number in front of bottleneck station which is defined as N.

– chip unit quantity in one lot, normally 2625. QPS – chip unit quantity need to be finished in

one shift. All the values of the parameters above can be

acquired from IE department. From section 2 we know that the WIP level we needed to estimate located in front of bottleneck workstation i, so we can calculate the healthy WIP level step by step as follows: 3.1. The Special WIP

This part of WIP is needed for hold lot or yield loss. That means when some quality problems which cause the unit of the lot to be hold or scrap happen, we need enough WIP to eliminate the effect on the latter bottleneck workstation. And the special lot percentage is usually controlled under (%) of QPS. So the special WIP needed in workstation i can be calculated as the below formula:

1i iWIP Q (3)

3.2. The Processing WIP

In the actual production activity the machine down time (STD and USTD) cost more time than the EE time and Idle time which we cal l it gap time. Actually the gap time is only a quite small part of the total time. The engineer experiment activity only can happen when it won’t cause obviously effect on the production and when the machine is idle the engineer will deal with the problem quickly. So here we assumed that there are only two states on the machine, down and up. The gap is considered together with pure processing time to estimate the processing WIP quantity.

The processing WIP level in workstation i:

4 3

2

( )i i ii

i i

U P PWIP

E U

(4)

3.3. The Waiting WIP

In the model assumption before, every machine down will cause production accumulation which is waiting WIP. IE time model divided the machine down time into SDT and USDT. So we calculated the WIP quantity from these two parts.

a) WIP caused by machine SDT. In assembly and test production system, SDT is

caused product conversion, change of consumables, preventive maintenance and so on. All of the events have the similar characters that when they happen and how long they should last can be decided by production management department. As the result of

the controllability of the scheduled down events, we assumed that only one machine can be scheduled stopped once a time in a workstation.

The WIP caused by machine can be calculated as follows: SDT

1

3i

ii i i

PWIP

E U M

(5)

b) WIP caused by machine USDT. USDT is caused by machine breakdown, user

maintenance delay, equipment spare part delay and so on. All of the events above also have the similar characteristics: randomness and uncontrollability. So the WIP quantity caused by machine USDT can also be estimated by IE time mode. However, just because of their randomness and uncontrollability the USDT often exceed the IE time budget. So the WIP caused by machine USDT can be divided into two parts: the WIP caused by machine USDT within IE budget and the WIP caused by machine SDT beyond IE budget. The WIP caused by machine USDT (within IE budget).

As mentioned above, normally the machine unscheduled down events are uncontrollable. So probability, permutation and combination were introduced to do assessment for a series of scenes (one machine stop，two machine stop, three machine stop and so on). We assume that the machine unscheduled down events surely happen. That means at least one machine stop (USDT) once a time. The real WIP needed can be calculated by the probability of occurrence of a special scene multiply the WIP estimated by IE model and then sum all the WIP estimated by all kinds of scenes. The computational formula is as follows:

2 2 2

4 12

1

1 1

i

i i

i

M jj jM M i i i

i Mji i ii

jC P P PWIP

E U MP

(6)

The WIP caused by machine USDT (beyond IE

budget). Statistics was introduced to estimate this part of WIP. The historical data of machine USDT records in every workstation from 2011.9 to 2011.12 was collected. The data preprocessing steps are as below: Remove the abnormal data by whiskers chart; Analysis the frequency of the processed data and

acquire the value of the USDT single duration of a certain workstation with 99 % confident level. Take workstation A for example, if we get the value B according to above steps, it means 99 % of a single duration of USDT in workstation A would happen within B. The WIP caused by machine USDT (exceed IE

budget) in workstation i can be estimated by the following formula:


217

2

5

)ii i

i i

PWIP L

E U

(1)

Summarizing all kinds of WIP in workstation i to

get the WIP level in single station:

1 2 3 4 5i i i i i iWIP WIP WIP WIP WIP WIP (1)

Summarizing all the WIP levels in all

workstations in front of bottleneck workstation to get the total WIP level need to be controlled in ConWIP release policy in Assembly and test production system.

1

_N

iistd WIP WIP

(1)

4. Build the Simulation Platform

First, as we discussed in section 2 and 3, establish the ATM simulation platform input Fig. 4 and output Fig. 5 in as below.

Then build the production line station simulation with C++ language in Flexsim platform as Fig. 6.

Fig. 4. Production line analysis &mechanism input.

Fig. 5. Production line analysis &mechanism output.

Fig. 6. Production line Analysis & Mechanism output.


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Additional, in order to verify the effectiveness of the heuristic algorithm above, a semiconductor assembly and test production line simulation mode was built based on Flexsim simulation software, which is the one famous manufacturing simulation tool. The related simulation experiment was designed as below: Determine the machine number of each

workstation which is needed in special scene according to production plan and the capability of each machine.

After calculating the WIP level needed (w) in the production line, change the WIP Level by (0.6 w, 0.7 w, 0.8 w, 0.9 w, 1.1 w, 1.2 w, 1.3 w, 1.4 w) to test the production system performance (CT and TH).

Change the average utilization budget (Ui) of each workstation as follows: Ui= {65 %, 70 %, 75 %, 80 %, 85 %, 90 %}

According to the heuristic algorithm get the corresponding WIP level needed (wi), and then changed the WIP level like the step2 to run the simulation model and get the corresponding system performance indicator (TH, CT).

Nine experiments for different levels.

WIP={0.6×wi,0.7×wi,0.8×wi,0.9×wi,1.0×wi,1.1×wi, 1.2×wi,1.3×wi,1.4×wi}

Three months was set as the simulation time, the data from the middle moth was recorded to guarantee the stability and validity of the data.

5. Result

The simulation result was showed as Table 1.This table includes the production system performance indicator CT and TH under different average utilization of each workstation and WIP level. From the table we can directly conclude that no matter how average utilization of each workstation changes the values of CT and TH get bigger as the WIP level increase. It is difficult to judge which WIP level is the better to get good combination of CT and TH. In order to solve the problem, Table 2 was made to show the variation tendency of average CT, average TH and standard deviation of CT (stdv_CT) when WIP level changes. In this table the growth rates of CT, TH and stdv_CT of other WIP levels relative to 1.0 W were showed.

Table 1. Throughput and cycle time under different WIP levels and average machine utilizations.

WIP Level

TH(lots/h) CT(d) 65% 70% 75% 80% 85% 90% 65% 70% 75% 80% 85% 90%

0.6 W 3.70 3.70 3.73 3.73 3.75 3.78 1.65 1.57 1.52 1.40 1.38 1.35 0.7 W 4.70 4.60 4.60 4.67 4.67 4.75 1.68 1.63 1.60 1.45 1.42 1.38 0.8 W 5.20 5.30 5.30 5.40 5.50 5.80 1.73 1.70 1.68 1.52 1.51 1.40 0.9 W 6.50 6.65 6.68 6.60 6.55 6.75 1.86 1.75 1.73 1.60 1.57 1.45 1.0 W 7.10 7.15 7.30 7.42 7.50 7.53 1.90 1.85 1.82 1.72 1.63 1.50 1.1 W 7.41 7.45 7.48 7.50 7.53 7.55 2.13 1.93 1.90 1.85 1.70 1.69 1.2 W 7.60 7.63 7.65 7.72 7.70 7.72 2.25 2.19 2.19 2.15 1.89 1.76 1.3 W 7.70 7.83 7.72 7.72 7.80 7.85 2.38 2.37 2.33 2.20 2.14 1.86 1.4 W 7.80 7.83 7.82 7.80 7.82 7.85 2.68 2.58 2.45 2.42 2.40 1.9

Table 2. Mean and growth rate of TH and CT, Standard deviation of CT and its growth rate.

WIP Level

TH CT Stdv_CT Mean (lot/h)

Growth Rate (%)

Mean (d)

Growth Rate (%)

STDV (d)

Growth Rate (%)

0.6 W 3.73 -49.11 1.48 -14.94 0.120 -20.52 0.7 W 4.67 -36.30 1.53 -12.07 0.125 -17sh.21 0.8 W 5.42 -26.10 1.59 -8.62 0.132 -12.58 0.9 W 6.62 -9.69 1.66 -4.60 0.147 -2.64 1.0 W 7.33 0.00 1.74 0.00 0.151 0.00 1.1 W 7.49 2.18 1.87 7.47 0.163 7.94 1.2 W 7.67 4.64 2.07 18.97 0.198 31.12 1.3 W 7.77 6.00 2.21 27.01 0.198 31.12 1.4 W 7.82 6.68 2.40 37.93 0.270 78.80

Fig. 7 is drawn based on Table 1. It visually described the variation tendency of CT and TH when WIP level changes under different average utilization (from 70 % to 90 %). Fig.8 was drawn according to

Table 2. It shows the variation tendency of CT and TH growth rate. In the end, the average utilizations of bottleneck workstation when Ui=90 % under different WIP levels were listed in Table 3.


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Fig. 7. TH and CT VS WIP level.

Fig. 8. TH and CT growth rate vs. WIP level.

Table 3. Bottleneck workstation’s average utilization (change with the WIP Level when the Ui=90 %).

WIP level 0.6 w 0.7 w 0.8 w Utilization 0.6833 0.7945 0.8712 WIP level 0.9 w 1.0 w 1.1 w Utilization 0.9138 0.9623 0.9735 WIP level 1.2 w 1.3 w 1.4 w Utilization 0.9752 0.9759 0.9763

6. Conclusion

Based on the CT and TH modelling result, we can draw some conclusions as below: When the semiconductor assembly and test

production system is relatively stable and ConWIP lot release policy is applied in front of bottleneck workstation, the system with higher average utilization can get better combination of CT and TH rate under the same WIP level. For example, in Fig. 7 when the WIP level is at 1.0 w, the system with 90 % average utilization can get higher throughput and short cycle time than the system with 70 % average utilization.

When the WIP level exceeds the 1.0w, the values of CT and TH rate increase with WIP increase. However, the variation tendencies of CT and TH rate are different, amplitude of variation of TH becomes smaller and smaller and amplitude of variation of CT rate becomes bigger and bigger. In Fig. 8, the slope of TH rate growth rate becomes smaller with WIP level grows and the slope of CT growth rate becomes bigger. In Table 2, we can see that the highest percentage improved in TH rate over that at 1.0 w is 6.68 %, meanwhile, it may cause 37.93 % increase in CT, which is not worthy.

When the WIP levels are below the 1.0 w, the values of CT and TH rate decrease with WIP reduction. However, we can get at most 14.94 % CT reduction when the WIP level is 0.6 w, and we have to pay up 49.11 % loss in TH rate accordingly, which is also not worthy.

From the Table 2, we can find that the standard deviation of CT at 1.0 w is smaller than those at 1.1 w and above. It indicates that the CT at 1.0 w which calculated by heuristic algorithm is more stable. It’s significant that the system with the standard WIP level calculated by heuristic algorithm have better order promising performance. Although we can’t guarantee that the heuristic

algorithm is always optimal for all factory indicators, but the WIP level calculated by it is a safe and reliable amount to achieve a high mean through put rate with relatively short cycle time. Meanwhile, the heuristic algorithm can be easily executed because the input parameter needed can be easily acquired from the factory. Its reliability and excitability can greatly improve the efficiency of the production decision. Acknowledgements

This work was supported by National Natural Science Foundation of China (Grant No. 51205264).

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GA: Industrial Engineering and Management Press, Institute of Industrial Engineers, 1983,

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[3]. D. J. Miller, Simulation of a semiconductor manufacturing line, Communications of the ACM, Vol. 33, Issue 10, 1990, pp. 99-108.

[4]. P. R. Philipoom, et al., An investigation of the factors influencing the number of kanbans required in the implementation of the JIT technique with kanbans, International Journal of Production Research, Vol. 25, Issue 3, 1987, pp. 457-472.


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[5]. Lin Yu-Hsin, Lee Ching-En, A total standard WIP estimation method for wafer fabrication, European Journal of Operational Research, Vol. 131, Issue 1, 2001, pp. 78-94.

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