custom silicon design automation with cadence pcell … · custom silicon design automation with...

CUSTOM SILICON DESIGN AUTOMATION WITH CADENCE PCELL DESIGNER

CUS-TECHTORIAL VGöran Jerke, Vinko Marolt, Christel Bürzele, Jaswant RajpurohitAutomotive Electronics, Robert Bosch GmbH

Peter Herth, Thomas Burdick,Guangjun CaoCadence Design Systems, Inc.

Automotive Electronics | AE/PJ-CE | 2019-05-08CDNLive EMEA 2019© Robert Bosch GmbH 2019. All rights reserved, also regarding any disposal, exploitation, reproduction, editing, distribution, as well as in the event of applications for industrial property rights.

AppCells

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What is an AppCell?Custom Silicon Design Automation with Cadence PCell Designer

PCells?

AppCell = App + PCell ?

Apps?

Icon copyrights: Bosch, DoubleDutch, Rob Hunt3


Cadence Virtuoso

LayoutSchematic

Schematic Entry

ModGen, DI, VRF, EAD, …

Layout Implementation

… …


PCells?

Apps?

Icon copyrights: Bosch, DoubleDutch, Rob Hunt

Custom SKILL

Custom SKILL

Custom SKILL

Custom SKILL

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Cadence Virtuoso

LayoutSchematic

Schematic Entry

ModGen, DI, VRF, EAD, …

Layout Implementation

… …


Icon copyrights: Bosch, DoubleDutch, Rob Hunt

"AppCell": PCell acting

as App within Virtuoso

AppCellAppCell AppCellAppCellAppCellAppCell AppCellAppCell

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PCells?

Apps?



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High-level SKILL++ scripts for VSE and VLS developed in Cadence PCell Designer.

AppCell: Fill the gap between selected instances

Help you to automate your work – they complement and enhance Virtuoso functionality. Deployed to projects as design libraries. They do not create any dependencies! Easily created and integrated into existing design flows and environments. Especially suited for end-user and project specific automation.


OverviewCustom Silicon Design Automation with Cadence PCell Designer

What is an AppCell?

Cadence PCell Designer Integrated Design Environment

Introduction to the AppCell Concept

AppCell Use Case Examples

Programming Overview and Flow Integration

Live Demo (Programming and Use Cases)

Online Documentation

Summary and Conclusion

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Cadence PCell Designer IDE

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Custom Silicon Design Automation with Cadence PCell DesignerCadence PCell Designer IDE

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CommandList

Access toPCell Methods

CodingComments

Variable andParameterViewer

GeometryObject Viewer

CommandsDocumentationViewer

Programming Window


Custom Silicon Design Automation with Cadence PCell DesignerCadence PCell Designer IDE - CommandsCreate and modify shapes, wires, connectivity

Define relations between object groups (follow)

Define the control flow

Create PCell documentation

Powerful GeoQuery language

Technology file look-up support

Transparent Virtuoso fluid shape support

SKILL/SKILL++ code can be embedded incl. CDF

Support for object oriented PCells

Support for hierarchical PCell modules (e.g., HIPE)

Support for AppCells 10

Create Functions Control Flow


Cadence PCell Designer IDE – GeoQuery and Cross-ProbingCustom Silicon Design Automation with Cadence PCell Designer

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Query task: Retrieve the BBox of all M1 shapes in the lower half of the instance BBox



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Step 1: Get all M1 shapes of the instance



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Step 2: Get the BBox of the instance



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Step 3: Get the lower half of the instance BBox



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Step 4: Get all M1 shapes in the lower half of the instance BBox



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Result: BBox of all M1 shapes in the lower half of the instance BBox


Cadence PCell Designer IDE – Version DiffCustom Silicon Design Automation with Cadence PCell Designer

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Pseudo codeabstracted fromPCell Designer PCell code


Introduction to the AppCell Concept

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Custom Silicon Design Automation with Cadence PCell DesignerIntroduction to the AppCell Concept

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PCell/CDF parameters: w, l, fingers, …

PCell myPCellCode Evaluation

Input

Evaluation

Classic PCell

Instances of schematic, symbol, layout PCellsOutput

Evaluation occurs in temporary cellview

PCell Programming:SKILL, SKILL++,PCell Designer, …


Custom Silicon Design Automation with Cadence PCell DesignerIntroduction to the AppCell Concept

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AppCell

PCell/CDF parameters: w, l, fingers, …

PCell myAppCellCode EvaluationContext

Input

Evaluation

- Instances of schematic, symbol, layout cells and PCells- Creation of new design objects (e.g., shapes, wires, instances, …) - Modification of existing design objects (e.g., parameters, arrangement, …)

Output

AppCell Programming:PCell Designer

Evaluation occurs in current cellview


AppCell Use Case Examples

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AppCell Use Case Example: AppCells complement VirtuosoCustom Silicon Design Automation with Cadence PCell Designer

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Programming Overview and Flow Integration

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AppCell ProgrammingCustom Silicon Design Automation with Cadence PCell Designer

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RMB

Enable PCell method as

AppCell

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2

3

PCell method


AppCell ProgrammingCustom Silicon Design Automation with Cadence PCell Designer

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Custom Silicon Design Automation with Cadence PCell DesignerAppCell Flow Integration AppCells are rolled-out for projects via regular PCell Designer PCell deployment mechanism

AppCell invocation in Virtuoso:ddGetObj(libraryName cellName viewName)->commands->methodName()

Example:

ddGetObj("CDNlive-EMEA-2019_PCD-Techtorial_appCells" "routeMosPCell" "layout")->commands->routeMos()

Flow integration: Bind keys Menus Tool bars Custom generators in IC618/IC18.1 Design Intent feature …

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Live Demo …

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Summary and Conclusion

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Online DocumentationCustom Silicon Design Automation with Cadence PCell Designer

NEW: Rapid Adoption Kits (RAKs) on PCell Designer topics avail. on https://support.cadence.com(1) Generating a Layout Parameterized Cell using PCell Designer – Basic(2) Generating a Schematic Parameterized Cell using PCell Designer

NEW: PCell Designer Community Forum https://community.cadence.com/cadence_technology_forums/f/pcell-designer

Fill Gap Align and Route MOS Routing

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https://support.cadence.com/

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091BRV

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V0000091B5w

https://community.cadence.com/cadence_technology_forums/f/pcell-designer


Summary and ConclusionCustom Silicon Design Automation with Cadence PCell Designer

AppCells are PCells that act as apps within Virtuoso Schematic and Layout.

AppCells: Complement the functionality of Cadence Virtuoso Not tied to PDKs anymore Leave no traces and they do not create additional dependencies Indistinguishable from manual results Provided as conventional project design and/or PDKs libraries No SKILL code loading required Versioning is simple Work wherever PCells work Schematic and layout

AppCells vs. Classic PCells: AppCells are evaluated in the current cellview enables context-awareness, context-modifications Awareness: AppCells can see and thereby consider their neighborhood directly Modification: AppCells can modify content in cellviews directly function macro

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Summary and ConclusionCustom Silicon Design Automation with Cadence PCell Designer

Simple flow integration: AppCells can be invoked in many ways (via bind keys, menu entries, icon bars, generators for DI accelerators) AppCells are loaded automatically during Virtuoso startup via design library loading As with all other PCell Designer created PCells, no additional license is required to execute AppCells

Cadence PCell Designer: Existing PCell (methods) can be easily and effortlessly transformed into an AppCell Powerful integrated (programming) design environment (editor, debugger, profiler, Virtuoso integration, …) Faster and safer PCell/AppCell development and know-how reuse compared to plain SKILL/SKILL++ coding

Conclusion: Now you can easily create your own apps for Virtuoso within a powerful programming environment.

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Thank You!


Appendix:

PCell Designer Programming Concept


Cadence PCell Designer – PCell ConceptCustom Silicon Design Automation with Cadence PCell Designer

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Define named groups of layout objects1.

Define relations between groups2.

Apply commands to groups in a defined sequence

3.

Structural Reuse

Source: CDNLive-EMEA 2013


Cadence PCell Designer – PCell ConceptCustom Silicon Design Automation with Cadence PCell Designer

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+

Hierarchical PCellsGeometry Queries in PCellsSupport for Fluid Shapes

Chop Obstruction

Follow-Shape

Source: CDNLive-EMEA 2014

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