current status of ieee standardization of€¦ · current status of ieee standardization of verilog...

Current Status ofCurrent Status ofIEEE Standardization ofIEEE Standardization ofVerilogVerilogA Hardware Description LanguageA Hardware Description Language

Anders NordstromIEEE 1364 Verilog Standards CommitteeFor the IEEE Ottawa ChapterMarch 26, 2003

© 2003 by Anders Nordstrom

© 2003 by Anders Nordstrom 2

Anders Nordstrom BackgroundAnders Nordstrom Background

l Senior ASIC Engineer at Elliptic Semiconductorl Director of Engineering at PacketDNA Technologiesl ASIC Design and Verification Manager at Nortel

Networksl Designed ASICs for SONET switching, Gigabit

Ethernet, Cell Switching & Multiprocessor computingengine

l Member of IEEE 1364 Verilog Standards Committeel Member of Accellera SystemVerilog Technical

Committeel Member of 0-In’s Customer Advisory Boardl Member of Co-Design’s Superlog Technical Advisory

Board.l Technical committee member for DVCon and SNUG


AgendaAgenda

l Introductionl What is Verilog?l Standardization Playersl History of Verilogl Learning Verilogl Quizl Verilog like Languagesl The IEEE 1364 WGl Verilog Future


What is Verilog?What is Verilog?

l Hardware Description Language

l Looks like C but it is not

l Beware of parallelism

l Used for Simulation, Synthesis,Formal Verification, Timingverification, Netlist


Verilog ExampleVerilog Example

always @ (posedge CLK)if (RESET)

Q <= 0;else

Q <= D;

assign full = (mem_addr == 32’h0000_4000)

case (state)IDLE: D = 0;READ: D = 4;WRITE: D = 8;

endcase


Quiz:Quiz:

lWhat does Verilog mean?


Quiz:Quiz:

lWhat does Verilog mean?lVeri-fication Log-ic HDL


Quiz:Quiz:

lWho said “I don’t know whatlanguage we are going touse in 10 years, but I know itwill be called Verilog”


Quiz:Quiz:

lWho said “I don’t know whatlanguage we are going touse in 10 years, but I know itwill be called Verilog”lPhil Moorby at IVC 1996


Why do we need a standard?Why do we need a standard?

l Proprietary languages defeat purposeof language ie communication.

l Enable tool developmentl Can not make money on a language

but someone has to do the work.l Minimizes re-learning for usersl Minimizes ambiguity, one

interpretation of language tokens inall tools


Verilog Standardization PlayersVerilog Standardization Players

l OVI

l VI

l IEEE

l Accellera


OVIOVI

l Open Verilog International

l Created in 1990

l Control and Promote Verilog

l Publish LRM

l VI is VHDL International


AccelleraAccellera

l Formed in 2000

lMerger of OVI and VI

l Identify and develop newstandards

l Foster use of new methodologies

lMain members: System houses,ASIC Vendors, EDA Vendors


Verilog History OverviewVerilog History Overview

l Proprietary Language

l Public Domain Language

l OVI Standards

l IEEE 1995 Standard

l IEEE 2001 Standard


First VerilogFirst Verilog

l 1984 Gateway Design Automation

l Verilog-XL Simulator

l Simulation language only

l Phil Moorby

l Bought by Cadence in 1989

l Licensed by Synopsys and LogicModeling Systems


Public Domain VerilogPublic Domain Verilog

l Cadence released Verilog topublic domain in 1990

l OVI Createdl Cadence still owned and sold

Verilog-XL Simulatorl Verilog HDL 1.0l Synopsys introduced limited

synthesis.


Towards IEEETowards IEEE

l OVI enhanced language

lMajor changes to PLI

l OVI Released Verilog HDL 2.0

l Submitted request to IEEE forstandardization in 1993


The Verilog 1995 StandardThe Verilog 1995 Standard

l First IEEE Verilog Standard

l Standardize what Verilog-XL did

l Did not include OVI Verilog 2.0enhancements


The birth of the 2nd VerilogThe birth of the 2nd Verilog

l Panel session at IVC 1996

l Presentation by Phil Moorby onhis vision for Verilog

l Attendees voted on “Top 5” listof desired new features

l Initial team formed


The 2001 Verilog StandardThe 2001 Verilog Standard

l Major enhancements for Design andVerification

l ANSI Style portsl Generatel Automatic Tasks and Functionsl Always @ (*)l Multi-dimensional arraysl Include all File I/O from Cl Parameter passing by Name


ANSI Style PortsANSI Style Ports

module mux8 (output reg [7:0] y,input wire [7:0] a,input wire [7:0] b,input wire en );

module mux8 (y, a, b, en);output [7:0] y;input [7:0] a;input [7:0] b;input en;reg [7:0] y;

Old Style:

New Style:


Generate StatementGenerate Statementmodule multiplier (a, b, product);parameter a_width = 8, b_width = 8;

localparam product_width = a_width +b_width;input [a_width-1:0] a;input [b_width-1:0] b;output [product_width-1:0] product;

generateif ((a_width < 8) || (b_width < 8))

CLA_multiplier #(a_width, b_width) u1 (a,b, product);

elseWALLACE_multiplier #(a_width, b_width) u1(a, b, product);

endgenerate

endmodule


Generate cont.Generate cont.

module Nbit_adder (co, sum, a, b, ci);parameter SIZE = 4;output [SIZE-1:0] sum;output co;input [SIZE-1:0] a, b;input ci;wire [SIZE:0] c;

genvar i;assign c[0] = ci;assign co = c[SIZE];

generatefor(i=0; i<SIZE; i=i+1)begin:addbit

wire n1,n2,n3; //internal netsxor g1 ( n1, a[i], b[i]);xor g2 (sum[i],n1, c[i]);and g3 ( n2, a[i], b[i]);and g4 ( n3, n1, c[i]);or g5 (c[i+1],n2, n3);

endendgenerate

endmodule


Automatic Tasks and FunctionsAutomatic Tasks and Functions

l New keyword: automatic

l Re-entrant tasks possible

l Recursive functions

function automatic [63:0] factorial;input [31:0] n;if (n == 1)

factorial = 1;else

factorial = n * factorial(n-1);endfunction


Combinatorial Sensitivity ListCombinatorial Sensitivity List

l Always @ (*)

lWildcard for all signals

l Eliminates simulation tosynthesis mismatches

l How synthesis always did itanyway


Always @ (*) ExampleAlways @ (*) Example

always @(sel or a or b or c or d)case (sel)2’b00: y = a;2’b01: y = b;2’b10: y = c;2’b11: y = d;endcase

always @(*)case (sel)2’b00: y = a;2’b01: y = b;2’b10: y = c;2’b11: y = d;endcase

Old Style:

New Style:


Multi-dimensional ArraysMulti-dimensional Arrays

//one-dimensional arrayreg [63:0] array_1D [127:0];

//two-dimensional arrayreg [63:0] array_2D [4095:0][127:0];

//declare a 3-dimensional array of 8-bit wire netswire [7:0] array3 [0:255][0:255][0:15];

//select one word out of a 3-dimensional arraywire [7:0] out3 = array3[addr1][addr2][addr3];


Enhanced File I/OEnhanced File I/O

l Verilog 1995 had limited file I/O

l Add most of C file I/O functions

l $fgetc (fd);

l $fgets (string, fd);

l $fread (reg_variable, fd);

l $fscanf (fd, format, arguments);


Parameter Passing by NameParameter Passing by Name

module RAM (addr, data_in, data_out, rd, wr);

parameter ADDR_WIDTH = 4;parameter DATA_WIDTH = 32;

RAM my_RAM #(.DATA_WIDTH(16)) (addr …


Learning VerilogLearning Verilog


Learning Verilog cont.Learning Verilog cont.

l Courses– Sunburst Design– Sutherland HDL

l Tutorials at DVCon and SNUGl FAQ’s and on-line tutorials

– www.verilog.com– www.see.ed.ac.uk/~gerard/Teach/Verilog/i

ndex.html– www.sunburst-design.com– www.sutherland-hdl.com


Learning Verilog cont.Learning Verilog cont.

l Usenet– comp.lang.verilog

l ESNUG– [email protected]

l Verification Guild– janick.bergeron.com


Quiz TimeQuiz Time……

• What are the IEEE 1076, 1487 and1364 standards?

• What is the difference between`define and parameters in Verilog?

• Is this legal Verilog:if (a=b) c <= 3;else c = 7;Why or why not?


Quiz TimeQuiz Time……

• What can you use automatictasks and functions for?

• When was Accellera formed?

• What was the purpose of thefirst Verilog?

• Do you have to be an IEEEmember to work on the VSG?


AnswersAnswers

l VHDL, SDF and Verilog

l Global vs local name space, canoverride a parameter

l No, assignment in if condition butit is legal in SystemVerilog


AnswersAnswers

l Recursion, use task many timesin parallel

l 1990

l To model a circuit for simulation

l No, but you have to be an IEEEand SA member to ballot


Verilog Related Verilog Related ActivitesActivites

l Superlog created by Co-DesignAutomation

l Higher level of abstraction thanVerilog

l Pointers, structures, queues

l Synthesizable subset donated toAccellera


Verilog Related Activities Cont.Verilog Related Activities Cont.

l Accellera formed SystemVerilogTechnical Committee afterSuperlog donation

l Added assertionsl Published LRM v3.0 June 2002l Added testbench automation

featuresl LRM v3.1 expected June 2003


Verilog EvolutionVerilog Evolution

Verilog 1995 Verilog 2005Verilog 2001

Superlog SystemVerilog

Vera


Too Many Languages ??Too Many Languages ??

l Verilog 1995 and 2001

l Superlog

l VHDL

l Hardware Verification Languages– Vera

– e

l SystemVerilog (3.0 , 3.1 , 3.2?)


SystemVerilog SourcesSystemVerilog Sources

l A subset of SUPERLOG

l OVL Assertions Library

l Proposals from SystemVerilogCommittee

l Synopsys Vera-Lite HVL

l PSL (Sugar)

l DirectC API


SystemVerilog FeaturesSystemVerilog Features

l Verilog connects modules usingports

l SystemVerilog adds Interfaces



l Abstract Data Types– 2 state types: int, shortint, char,

byte, bit– 4 state types: logic– Special types: void, shortreal

lModeling at C-level of abstractionl Efficient for simulation

performance



l Enumerated Types

l Structures



l Assertionconstruct

l Classes


Learning SystemVerilogLearning SystemVerilog


ButBut……

l SystemVerilog is not IEEE Verilog

l Should Verilog containAssertions and HVL features?

lWhat about queues and otheruseful constructs?


1364 WG or VSG1364 WG or VSG

l IEEE 1364 Working Group orVerilog Standards Group (VSG)

l 3 Task Forces look at differentaspects of Verilog

l PLI Task Force

l ASIC Task Force

l Behavioral Task Force


1364 Task Forces1364 Task Forces

lMembers from EDA companiesand users

lWorks independently to reviewand approve proposals

l Each passed proposal presentedto VSG monthly for vote


IEEE Standards ProcessIEEE Standards Process

l Form group

l Sign up sponsor (OVI, Accellera)

l Obtain PAR with schedule

l Collect proposals, evaluate,modify or reject

l Vote on all changes to LRM

l Produce updated LRM


IEEE Standards Process Cont.IEEE Standards Process Cont.

l Call for Ballot participationl Ballotl Receive ballot feedbackl Respond to feedbackl Re-ballot or passl IEEE approvall Print and distribute LRM


Benefits of IEEE ProcessBenefits of IEEE Process

l Thorough technical review by 3groups

l Ensure buy-in from EDA vendors

l Implementable standard

l Credible stable standard

l Maximizes backward compatibility

l Verilog standard reviewed by 200people


Drawbacks of IEEE ProcessDrawbacks of IEEE Process

l Slow process, 5 years betweenstandards

l Key features left out if agreementcan not be reached


Learn more about StandardizationLearn more about Standardization

l www.accellera.org

l www.boyd.com/1364


1364 WG Web Site1364 WG Web Site

l www.boyd.com/1364_btf


Verilog FutureVerilog Future

l IEEE 1364 Verilog 2006?

l Over 300 Errata andEnhancements so far

l Expect some SystemVerilogfeatures

lWhat else?


We need your helpWe need your help

l Join the IEEE 1364 Working Group

l You can help form the future Verilog.

l You’ll really learn Verilog, from thepeople who created it

l Peer recognition, fame and fortune :-)

l Networking

l Talk to a current VSG member to join


How much work is it?How much work is it?

l Bi-weekly 2h conference call

lMeetings at major conferences

l 2-10h / month reviewing andwriting proposals

l Discussion via email

l 75% attendance required forvoting right


Questions??Questions??

l Anders Nordstrom

l [email protected]

current status of ieee standardization of€¦ · current status of ieee standardization of verilog...

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