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Analog Integrated Circuits – Fundamental Building Blocks Current mirrors

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1. Current mirrors

All the circuits studied in the previous paragraphs were simple, controlled current sources. Their ana-lysis has been done under the assumption that all the transistors are correctly biased in the saturation region. The issue, that has not been discussed, is the method used to insure the correct biasing of the transistors. Practically the biasing conditions are reduced to the generation of all the constant voltages in the circuit. The vast majority of the gate potentials are generated by injecting a reference current in one or more diodes con-nected in series. The voltage drop on these diodes will serve for stabilizing the gate-source voltages of the transistors in the current source. The resulting class of sub-circuits is called current mirrors. The current mir-rors are particularly useful for the distribution of bias currents in larger circuits. They can also be employed as current amplifiers.

The basic parameter that describes the functionality of a current mirror is its current gain or reflection coefficient. The current gain is defined as a ratio between the generated output current and the input refe-rence current.

out

in

InI

(1)

The performance requirements for current mirrors are similar as for current sources:

the output resistance must be as large as possible in order to reduce the dependence of the output current on the output voltage;

the input resistance must be as small as possible; the minimum allowed output voltage must be as small as possible; the minimum input voltage must be also as small as possible; the current gain must be precisely defined, constant with the supply voltage and temperature

independent.

The following paragraphs present the most important current mirror structures. The emphasis lays on the analysis of the circuits based on the parameters listed above and on the methods used to improve the per-formances. Some of the effects, that will be considered during the analysis, are the channel length modula-tion (Early effect) and the transistor mismatch.

1.1. MOS current mirrors

1.1.1. The simple MOS current mirror

The simple current mirror can be obtained from the one transistor current source by using a second transistor in diode connection that generates the necessary gate-source voltage of the transistor in the output stage. The gate source voltage is set by the diode geometry and the injected input or reference current. Since the gates and the sources of the two transistor are connected together the gate-source voltage of the current source will be equal to the gate source voltage of the diode. The schematic of the circuit is given in Figure 1. The corresponding small signal equivalent model is shown in Figure 2.

Figure 1. NMOS and PMOS implementations of a simple current mirror


2

Figure 2. The small signal equivalent model of the simple MOS current mirror

The calculation of the current gain n starts with the expressions of the input and of the output currents.

21 1 1 1 1

22 2 2 2 2

1 21 2

1 2

1

1

;2 2

in D GS Th DS

out D GS Th DS

ox ox

I I V V V

I I V V VC W C W

L L

(2)

If the gate-source voltages of the transistors are assumed to be equal, the current gain results

22 2 2

21 1 1

11

GS Th DSout

in GS Th DS

V V VInI V V V

(3)

The input resistance of the mirror can be determined from the small signal equivalent model. First the input voltage is written as a function of the input current:

1 1 1 1 1in in DS in m GS DSV I I r I g V r (4)

The gate-source voltage VGS1 of the transistor M1 can be identified from the schematic as the input vol-tage. By replacing VGS1 with Vin in the equation (4) the input resistance results:

1

1 1 1

11

in DSin

in m DS m

V rRI g r g

(5)

The output resistance can be calculated with a similar method as for a simple, one transistor current source. The final expression of the output resistance is

1out

out DSout

VR rI

(6)

The minimum allowed output voltage is defined similarly as for the simple, one transistor current source and is equal to the drain-source voltage of the transistor M2 at which the device is still biased in the saturation region.

When taking a closer look to the equation (3) it can be noticed that there are three independent factors that can affect the value of the current gain. These factors are the channel length modulation (Early effect), the threshold voltage mismatch and the geometrical mismatch of the transistors. The theorem of superposi-tion can be used to emphasize each effect.

In order to clearly see the consequences of channel length modulation, the transistor geometries and the threshold voltages are considered perfectly matched. In this case the current gain of the mirror is

2

1

11

DS

DS

VnV

(7)


3

It results that the drain-source voltages of the two transistors must be balanced in order to reduce the influence of the channel length modulation. Figure 3 shows the typical variation of the current gain plotted against the mirror input-output voltage mismatch, equal to the drain source voltage difference of the tran-sistors (Vout−Vin=VDS2−VDS1).

Figure 3. Variation of the current gain against the input-output voltage imbalance

It can be seen that, for equal input and output voltages, the current gain is equal to unity. It can also be noticed that a 1V voltage imbalance can produce an error approximately equal to 9%. The 1V voltage diffe-rence may appear relatively easily in biasing circuits where the mirror is used for changing the sign of a given bias current. Usually in these cases the two branches of the circuit will see different load resistances and, as a consequence, the voltage drops will be imbalanced.

The analysis of the current gain errors caused by geometry and threshold voltage mismatch can be per-formed when considering the input-output (and implicitly the drain-source) voltages perfectly balanced. In this case the error is not influenced by the channel length modulation effect. In the calculations it is assumed that the threshold voltage mismatch is ΔVTh and the geometry mismatch is translated to Δβ. For the threshold voltages it holds true that

1 21 2

1 1; ;2 2 2

Th ThTh Th Th Th Th Th Th

V VV V V V V V V (8)

Similar equations can be written also for the β-s of the transistors:

1 21 2

1 1; ;2 2 2

(9)

By replacing the expressions in the equation (3) the current gain results:

2

2

1 12 21 12 2

GS Th Thout

inGS Th Th

V V VInI

V V V

(10)

Writing the threshold voltage and β as common terms for the numerator and the denominator leads to

2

2

1 12 2

1 12 2

Th

GS Thout

in Th

GS Th

VV VIn

I VV V

(11)


4

For further calculations let us consider the inverse binomial function and its Taylor series expansion, given by the following equation:

2 3

1 2 3 40

1 1k

kk

x x x xx a a a a a a

(12)

For low mismatch between the transistors, if Δβ << β and ΔVTh << 2(VGS-VTh), the second and higher order terms of the series can be neglected and the expression of the current gain may be approximated as

42

1 12 2

Th

GS Th

VnV V

(13)

After squaring the expressions and successively neglecting second order terms the current gain can be approximated as given in the following equation:

21

2Th

GS Th

VnV V

(14)

It results that the precision of the current gain can be improved if the transistors are sized for larger geometries or their drain currents are increased. In practice, an increase of the bias current either leads to higher consumption or the current value may be imposed by design specifications. Therefore, if operating frequency and circuit area limitations are not an issue, larger geometries are always preferred for better de-vice matching. Typically, the owner of the fabrication facility and the target process indicates the minimum transistor area that should be used for a matching better than ±3σ. The minimum area is obtained after statis-tical measurements. A ±3σ matching means transistors identical to an extent approximately equal to 99,7% (considering a gaussian statistical distribution of the geometry errors).

As a summary on the performances of the simple current mirror it can be concluded that not all the re-quirements listed at the beginning of this section are entirely and unconditionally satisfied. If necessary, a better precision of the current gain can be obtained by employing a structure that allows the balancing of the transistor drain-source voltages. The output resistance also needs improvement as a heritage from the simple current source output stage. One often used procedure, that reduces these deficiencies, is cascoding.

1.1.2. The cascode MOS current mirror

The cascode current mirror is derived from the simple current mirror by cascoding both branches of the circuit. The schematic of the resulting structure is given in Figure 4.

Figure 4. NMOS and PMOS implementations of a cascode current mirror

The bulk terminal of the transistors is connected either to the lowest potential, or to VDD for PMOS transistors. In Figure 4 the substrate connections of the transistors M3 and M4 facilitate the identification of VBS voltages when calculating the input and the output resistances. The small signal equivalent model of the circuit is given in Figure 5.


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Figure 5. Small signal model of the MOS cascode current mirror

the input resistance

In order to calculate the input and the output resistances, Thevenin’s and Norton’s theorems must be considered. The input of the current mirror is a current mode terminal. For a correct calculation of the input resistance the output terminal must be regarded as an interruption and the output current is equal to zero. This requirement results from the application of Thevenin’s theorem to the equivalent two-port network. Similarly, as a result of Norton’s theorem, for the correct calculation of the output resistance, the input must be considered shorted to the ground and the input voltage is equal to zero.

The input voltage can be expressed as the sum of the drain-source voltage drops on the transistors M1 and M3.

1 3in DS DSV V V (15)

Due to the diode connections the gate-source voltages of the transistors M1 and M3 are equal to their drain-source voltage. For the transistor M1

1 3 1 1 1 1 1 1 1 1 1DS in DS in DS m DS GS in DS m DS DSV I I r I r g r V I r g r V (16)

This equation can be solved for VDS1:

11

1 11DS

DS inm DS

rV Ig r

(17)

Similarly, for the drain source voltage of the transistor M3

3 1 2 3 3 3 3 3 3 3 3DS in DS in DS m DS DS mb DS BSV I I I r I r g r V g r V (18)

Considering that the VBS3 voltage is

13 3 3 1

1 1

01

DSBS B S GS in

m DS

rV V V V Ig r

, (19)

the equation (18) can be solved for VDS3 can be written as

3 3 1 33

3 3 1 1 3 31 1 1DS mb DS DS

DS inm DS m DS m DS

r g r rV Ig r g r g r

(20)

The input resistance is found by replacing the drain-source voltages VDS1 and VDS3 in the equation (15). The expression of Rin results


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1 3 3 1 3

1 1 3 3 1 1 3 31 1 1 1in DS DS mb DS DS

inin m DS m DS m DS m DS

V r r g r rRI g r g r g r g r

(21)

This equation can be simplified if the drain-source resistances of the transistors in the saturated region are assumed to be relatively large. The effect of the substrate can also be neglected. The input resistance is then approximated with

1 3

1 1in

m m

Rg g

(22)

The equation (22) suggests that the input resistance has been practically doubled compared to the input resistance of the simple current mirror.

the output resistance

The output resistance can be determined by similar calculations as for the simple current mirror. The starting point is the small signal equivalent model presented in Figure 5. The output voltage can be written:

2 4out DS DSV V V (23)

Next the drain-source voltage of the transistor M2 can be expressed as a function of the output current. The gate voltages of the transistors M2 and M4 are set by M1 and M3. Consequently, they will not be influ-enced by the variations of the output current and can be considered constant in the schematic and zero in the small signal model.

2 6 2 2 2 2 2 20

DS out DS out DS m DS GS out DSV I I r I r g r V I r

(24)

The drain-source voltage of the transistor M4 has a similar expression:

4 4

4 4 5 4 4 4 4 4 4 4 4

S S

DS out DS out DS m DS GS mb DS BSV V

V I I I r I r g r V g r V

(25)

Since the source potential of M4 is VS4=VDS2, the VDS4 voltage becomes

4 4 4 4 2 4DS out DS m mb DS DSV I r g g r r (26)

Replacing VDS2 and VDS4 into the equation (23) leads to the expression of the output resistance:

2 4 4 4 2 4out DS DS m mb DS DSR r r g g r r (27)

Equation (27) shows that the output resistance of the cascode current mirror is equal to the output re-sistance of the cascode current source.

Derivation of the minimum allowed output voltage

In order to determine the minimum allowed output voltage, all the transistors will be considered iden-tical and perfectly matched. In this case VDSat marks the minimum drain-source voltage of a transistor for which the device still operates in the saturated region. At the limit, the saturation condition is VDSat=VGS-VTh. From the schematic of the circuit in Figure 4 it can be seen that the gate-source voltages of all the transistors are equal and can be expressed as

1 2 3 4GS GS GS GS Th DSatV V V V V V (28)

The gate potential of the transistor M4 is equal to the sum of the gate-source voltages of the transistors


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M1 and M3. Then it holds true that

4 2 2G Th DSatV V V (29)

Since the gate-source voltages of M3 and M4 are also equal, the drain-source voltage drop across M2 is

2 4 4 2 2DS G GS Th DSat Th Dsat Th DSatV V V V V V V V V (30)

The expression of the minimum allowed output voltage results

min 2 4 2o DS DS Th DSatV V V V V (31)

From the schematic of the circuit and from the equation (31) results that the voltage drop on the tran-sistor M2 is equal to VTh+VDSat. However, in order to correctly operate in the saturation region, the transistor only requires a drain-source voltage equal to VDSat. As a consequence, the cascode current mirror is not the most efficient structure for low voltage applications.

the current gain

The precision of the current gain has been greatly improved by cascoding. The drain-source voltages of the transistors M1 and M2 are balanced by M3 and M4. Therefore, the current gain is not influenced by the input-output voltage imbalance and by the channel length modulation effect. The error caused by geometrical and threshold voltage mismatch will be unchanged and can be controlled by design for matching and good layout. In practice the transistors M3 and M4 are usually optimized for large transconductance, while M1-M2 are sized for good matching and large rDS. Figure 6 shows the variation of the current gain against the imba-lance of the input and the output voltages.

Figure 6. Variation of the current gain against the difference between the input and the output voltages

1.1.3. The low swing MOS cascode current mirror

The main drawback of the classical cascode current mirror is its lack of efficiency when considering the minimum allowed output voltage. The high output voltage requirements are the result of a large voltage drop on the transistor in the fundamental mirror M1-M2. From a thorough examination of the equations (30) and (31) along with the schematic of the cascode current mirror in Figure 4, it can be noticed that the mini-mum allowed output voltage could be lowered if the gate potential of the transistor M4 would be decreased with an amount equal to the threshold voltage VTh. This requires an alternative connection of the transistor M3 as shown in Figure 7.

The new gate potential of the transistor M4 is VTh+2VDSsat. The drain-source voltage of M2 will be

2 4 4 2DS G GS Th DSat Th Dsat DSatV V V V V V V V (32)


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Figure 7. Possible implementation of a low swing cascode current mirror

The drain source voltage of M4 must be chosen to be VDSat, according to the saturation condition. It re-sults that the minimum output voltage has been lowered with the required threshold voltage to Vomin=2VDSat and has now the lowest possible value that keeps the transistors on the output branch in saturation.

A special care must be taken of the biasing conditions for M3. The W/L ratio of this transistor must be lowered proportionally with the increase of its overdrive voltage 2VDSat. From the schematic it can be noticed that the overdrive voltage has been doubled in the new connection (equal to 2VDSat instead of VDSat). As a consequence, the size of the transistor must be only a quarter of its original value.

The main drawback of this mirror is that the drain-source voltages of the transistors M1 and M2 are not balanced. This will influence the precision of the current gain as described in the previous paragraphs. The solution to this problem is to connect a cascode transistor M5 in series with M1 which sets the balance of the voltages. The connection must not change the minimum input voltage and the input resistance. For a correct balancing the gate potential of this transistor must be equal to the gate potential of the transistor M4. If the two cascode transistors are designed for identical gate-source voltages, then VDS1 equals VDS2 and the channel length modulation will not influence the current gain. The schematic of the resulting circuit is presented in Figure 8.

Figure 8. The low swing cascode current mirror with drain source voltage balancing

Another possible problem with this structure is due to the difficult biasing conditions for the transistor M3. The gate-source voltage of this device must be sufficiently high in order to cope with the gate potential requirements of M4 and M5. This could lead to extremely small values for the channel width. A possible so-lution, that overcomes the biasing problem, is to let some of the large gate-source voltage drop on a resistor inserted in series with the source of M3. The schematic with the inserted resistor is given in Figure 9.

Figure 9. The low swing cascode current mirror with drain source voltage balancing


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The resistor takes over a fraction of the initial gate-source voltage. If the transistors M3, M4 and M5 are identical and Iref=Iin, then the voltage drop VR on the resistor will be equal to the drain-source voltages of M1 and M2. In practice, the active implementation (MOSFET in the triode region) of the resistor is typically pre-ferred due to area and tolerance constraints. A practical implementation of the complete low voltage cascode current mirror is given in Figure 10.

Figure 10. Practical NMOS and PMOS implementations of the low swing cascode current mirror with minimal voltage requirements

The drain-source voltage of M6 can be written as

6 6 3DS GS GSV V V (33)

For the transistor M3

3 3 3GS Th DSatV V V (34)

If the effect of the substrate on the threshold voltage is neglected and VTh3 is assumed to be equal with VTh6, then the equation (33) becomes:

6 6 3,6 3DS GS Th DSatV V V V (35)

Considering the saturation condition VDS6>VGS6-VTh6 for the transistor M6, from the equation (35) it is clear that the device will always be biased in the triode region, regardless of its VDSat voltage. Accordingly, it can successfully replace the passive resistor in the low swing current mirror.

The output resistance of the low voltage cascode current mirror is the same as for the classical ver-sion because the output stage has not been modified. The input resistance can be calculated from the small signal equivalent model given in Figure 11.

Figure 11. Small signal model of the low swing MOS cascode current mirror

From the small signal model the input voltage is



10

The drain source voltage of the transistor M1 can be written as

1 3 1 1 1 1 1 1 1 1DS in DS in DS m DS GS in DS m DS inV I I r I r g r V I r g r V (37)

Similarly, for M5

5 1 2 5DS in DSV I I I r , (38)

where the currents I1 and I2 can be expressed as functions of the input current and of the input voltage:

1 5 5 5 5 5 5 1 5 1 1

2 5 5 5 5 5 5 1 5 1 1

m GS m G S m DS m DS m in in

mb BS m B S mb DS mb DS m in in

I g V g V V g V g r g V I

I g V g V V g V g r g V I

(39)

Replacing the currents I1 and I2 in equation (38) leads to

5 5 5 5 1 5 1DS in DS m mb DS DS in m inV I r g g r r I g V (40)

The final expression of the input resistance results

1 5 5 5 1 5

1 1 1 5 5 1 5 1

11

DS DS m mb DS DSinin

in m DS m m mb DS DS m

r r g g r rVRI g r g g g r r g

(41)

This expression can be simplified by considering the large drain-source resistances and by neglecting the effect of the substrate. Practically, the input resistance of the low swing cascode current mirror is similar to the input resistance of the simple current mirror.

Taking into account its advantages, the low swing cascode current mirror is an often used solution in low voltage biasing circuits.

1.1.4. The Wilson current mirror

The Wilson current mirror is derived from the simple current mirror and may be regarded as an alter-native to the cascode current mirror discussed in the previous sections. This structure uses a shunt-series type negative feedback in order to enhance the value of the output resistance. The schematic of the circuit is given in Figure 12, while Figure 13 shows its small signal equivalent model.

Figure 12. Schematic of the unbalanced Wilson MOS current mirror


The output resistance is calculated Iin=0, according to Thevenin’s theorem. The output voltage can be written as a sum of the drain source voltage for the transistors M2 and M3.



11

Figure 13. Small signal model of the unbalanced Wilson MOS current mirror

The drain-source voltage of M2 is

2 2 2 2 2 2 2DS out DS out DS m DS DSV I I r I r g r V (43)

Solving this equation for VDS2 leads to

22

2 21DS

DS outm DS

rV Ig r

(44)

Similarly, the drain-source voltage of M3 is written

3 3 4 3DS out DSV I I I r (45)

The currents I3 and I4 are functions depending on the output current:

1 13 3 3 3 3 3 3 1 2 3 2

2 2

3 24 3 3 3 3 3 3 2

2 2

11

1

m DSm GS m G S m DS DS out m DS

m DS

mb DSmb BS mb B S mb DS out

m DS

g rI g V g V V g V V I g rg r

g rI g V g V V g V Ig r

(46)

By replacing the currents into the equation (45), the VDS3 voltage becomes

1 1 3 2 33 3 3 2 3

2 2 2 2

11 1

m DS mb DS DSDS out DS out m DS DS out

m DS m DS

g r g r rV I r I g r r Ig r g r

(47)

The output resistance is found after combining equations (42), (44) and (47).

2 1 3 1 33 3 3 3 1 1 3

2 2 2

1 11

DS m m DS DSout DS DS m mb m DS DS

m DS m

r g g r rR r r g g g r rg r g

(48)

From the expression of the output resistance it can be noticed that its approximate value is similar to the output resistance of the cascode mirror discussed in the previous paragraphs.


The input resistance is calculated with the output shorted to the ground according to Norton’s theorem. If Vout=0, the following relation holds true:

3 1 3 10out DS GS DS GSV V V V V (49)


12

The drain-source voltage of the transistor M3 and the output current for a grounded output are

3 3 4 3DS out DSV I I I r (50)

This equation gives the dependence of the VGS1 gate-source voltage on VGS3 by replacing the following expressions into the equation (50):

3 1

3 3 3

34 3 3 3 3 3 3 1 1 3

2 32 2 2 32 2 2 1 22 2 2

1 11

DS GS

m GS

mmb BS mb B S mb GS GS GS

m mbDS GS DS DSout m GS GS mDS DS DS

V VI g V

gI g V g V V g V V Vg gV V r rI I g V V g

r r r

(51)

In the next step the input voltage is written as

1 1 1 1 1 1in in DS in DS m DS GSV I I r I r g r V (52)

By inserting the expression of VGS1 from the equation (51) into (53) it results:

31 3

2 32 3

1 1m

in in DS GS

m mbDS DS

gV I r Vg g

r r

(53)

In order to obtain the input resistance, the gate-source voltage VGS3 of the transistor M3 is calculated as a function of the input voltage and the input current.

33 1 3

2 32 3

1 1m

GS in GS in GS

m mbDS DS

gV V V V Vg g

r r

(54)

Solving for VGS3 yields

2 3

2 33

2 3 32 3

1 1

1 1

m mbDS DS

GS in

m m mbDS DS

g gr rV V

g g gr r

(55)

The input resistance is calculated after introducing the expression of VGS3 into the equation (54).

1 2 3 3

2 3 2 3

1 32 3 3 1 3 1

2 3

1 1

1 1

DS m m mbDS DSin m m

inin m m

m m mb m m DSDS DS

r g g gr rV g gR

I g gg g g g g rr r

(56)

The approximation of the input resistance holds true if the rDS resistances of the transistors are consi-dered relatively large and the effect of the substrate is neglected. It can be seen that the value of Rin is similar to the input resistance of the cascode current mirror.

One of the main drawbacks of the Wilson current mirror is that the minimum allowed input and output voltages are relatively large. Their value can be determined by using similar methods as for the cascode cur-rent mirror.


13

min

min

22 2

o Th DSat

i Th DSat

V V VV V V

(57)

Another drawback of the circuit is that the drain-source voltages of the transistors M1 and M2 are not equal. This causes significant current gain errors due to the channel length modulation effect. The remedy to this issue is to build a balanced Wilson current mirror. The balanced Wilson mirror is derived from the sche-matic in Figure 12 by connecting a series transistor as a diode in the input branch of the circuit. The resulting structure is presented in detail in the following section.

1.1.5. The balanced Wilson MOS current mirror

The schematic of the balanced Wilson current mirror is presented in Figure 14. The transistors M3 and M4 help improving the precision of the current gain by balancing the drain-source voltages of the fundamen-tal mirror transistors M1 and M2.

Figure 14. Schematic of the balanced Wilson MOS current mirror

The input and the output resistances may be determined by calculations performed on the small signal model shown in Figure 15.

Figure 15. Small signal model of the balanced Wilson MOS current mirror


The output resistance is calculated for similar conditions as in the case of the unbalanced mirror. Due to Thevenin’s theorem, the input current is considered to be zero. The output voltage is written as the sum of the M2 and M3 transistor drain-source voltages.


The voltage VDS2 is

2 6 2 2 2 2 2DS out DS out DS m DS GSV I I r I r g r V (59)

The transistor M2 is connected as a diode and its gate-source voltage VGS2 is equal to the drain-source


14

voltage VDS2. The equality of the two voltages leads to

22

2 21DS

DS outm DS

rV Ig r

(60)

The drain-source voltage of M3 is expressed in a similar manner:

3 4 5 3 3 3 3 3 3 3 3DS out DS out DS m DS GS mb DS BSV I I I r I r g r V g r V (61)

Since the substrate of M3 is grounded, VBS3= VS3=VDS2 and the equation (61) becomes

3 2 33 3 3 3 3

2 21mb DS DS

DS out DS m DS GS outm DS

g r rV I r g r V Ig r

(62)

In order to find Rout, the gate-source voltage VGS3 must be calculated as a function of the output current and of the transistor parameters. Kirchhoff’s voltage law written for the input voltage leads to

23 2 3 2

2 21DS

in GS DS GS in DS in outm DS

rV V V V V V V Ig r

(63)

Writing Kirchhoff’s voltage law again for the input voltage yields

4 1 1 2 4 3 1in DS DS in DS in DSV V V I I I r I I r (64)

After setting Iin=0 and replacing the currents from the small signal model we get

4 4 4 4 4 4 1 1 1in m DS GS mb DS BS m DS GSV g r V g r V g r V (65)

The voltages in the above equation are

1 2 2

4 4 4 1 1 1 1 1 1 2

4 4 4 4 1 1 1 1 1 1 2

GS GS DS

GS G S in DS in in m GS DS in m DS DS

BS B S S DS in m GS DS m DS DS

V V VV V V V V V I g V r V g r V

V V V V V I g V r g r V

(66)

The input voltage from (65) becomes

4 4 1 1 4 4 4 21in m DS in m DS m mb DS DSV g r V g r g g r V (67)

The input voltage is then calculated as a function of the output current by replacing VDS2 from (60) and by rearranging the terms in (67).

1 1 2 4 4 4

2 2 4 4

11 1

m DS DS m mb DSin out

m DS m DS

g r r g g rV I

g r g r

(68)

The gate-source voltage VGS3 of the transistor M3 is obtained by inserting the expression of Vin into the equation (63).

1 1 4 4 42

32 2 4 4

11

1 1m DS m mb DSDS

GS outm DS m DS

g r g g rrV Ig r g r

(69)


15

The final expression of the output resistance results after combining (58), (60), (62) and (69).

1 1 4 4 42 3 3 3 3 2

32 2 2 2 4 4

111

1 1 1m DS m mb DSDS mb DS m DS DS

out DSm DS m DS m DS

g r g g rr g r g r rR rg r g r g r

(70)

By neglecting the effect of the substrate (gmb=0) and by considering very large rDS resistances, Rout may be approximated as

1 1 3 3

2

m DS m DSout

m

g r g rRg

(71)

This equation shows that the output resistances of both the balanced and the unbalanced MOS Wilson current mirrors is approximately the same.


The input resistance is calculated for Vout=0, according to Norton’s theorem. The demonstration starts with the input voltage resulting from Kirchhoff’s voltage law, written for the input branch of the mirror.


The voltage VDS4 is found from the small signal model in Figure 15. The inspection of the mirror sche-matic shows that, for M4 connected as a diode, the gate-source voltage VGS4 is equal to the drain-source vol-tage VDS4. Furthermore, the substrate terminal of the same transistor is grounded and its VBS4 voltage is equal to the drain-source voltage VDS1 of M1.

4 4 4 4 4 4 4 4 4 4 4 4 1DS in m GS mb BS DS in DS m DS DS mb DS DSV I g V g V r I r g r V g r V (73)

Rearranging the terms in the above equation leads to

4 4 44 1

4 4 4 4

11 1

DS mb DSDS in DS

m DS m DS

r g rV I Vg r g r

(74)

The input voltage is a sum of VDS1 and VDS4=f (VDS1). Thus, the VDS1 voltage must be written as a func-tion of the input current Iin and of the input voltage Vin.

1 1 1 1 1 1 1 1DS in m GS DS in DS m DS GSV I g V r I r g r V , (75)

where from small signal model

1 3 3 3 3 3 3GS DS out m GS mb BS DSV V I g V g V r (76)

The voltages and the output current Iout in the above equation are

3 3 3 1

3 3 3 3 2 1

2 22 2 1

2 2 21

GS G S in GS

BS B S S DS GS

DS DSout m GS GS

DS m DS

V V V V VV V V V V V

V rI g V Vr g r

(77)

Replacing the expressions of the voltages and of the output current from (77) into (76), leads to the following equation:


16

3 2 21 3 3 1 3 3 1 1

2

1DS m DSGS m DS in GS mb DS GS GS

DS

r g rV g r V V g r V V

r

(78)

This equation can be readily solved for VGS1. The solution is the expression of VGS1 as a function of Vin.

3 2 31

2 3 2 3 3 2 3

m DS DSGS in

DS DS m m mb DS DS

g r rV Vr r g g g r r

(79)

By replacing VGS1 into (75) we get

1 3 1 2 3

1 12 3 2 3 3 2 3

m m DS DS DSDS in DS in

DS DS m m mb DS DS

g g r r rV I r Vr r g g g r r

(80)

Then, successively replacing VDS1 in (74) and (72) yields

4 4 1 3 1 2 3 41

4 4 2 3 2 3 3 2 3 4 4

1 11 1

mb DS m m DS DS DS DSin in DS

m DS DS DS m m mb DS DS m DS

g r g g r r r rV I rg r r r g g g r r g r

(81)

The input resistance and its approximation for gmb4=0 and large rds result

41

4 4 2 3

1 34 4 1 3 1

4 42 3 3

2 3

1

1 1 1 11

DSDS

m DS m min

m mmb DS m m DS

m DSm m mb

DS DS

rrg r g gR

g gg r g g rg r g g g

r r

(82)

The calculated input and output resistances given in (82) and (71) show that the balanced Wilson and the cascode current mirrors have similar parameters while both suffer from relatively large biasing voltage requirements.

1.2. Bipolar transistor current mirrors

Bipolar current mirrors are built with the same circuit topologies as their MOS counterparts. The main differences in operation are caused by the finite base-emitter resistances of the transistors and the correspon-ding current losses in the base terminals.

1.2.1. The simple bipolar current mirror

The schematic of the simple current mirror implemented with bipolar transistors is given in Figure 16.

Figure 16. Schematic of the simple bipolar transistor current mirror

The current gain of the mirror can be analyzed by considering the non-zero base currents of the tran-


17

sistors, the emitter area (translated to saturation current) mismatch and the difference between the input and the output voltages. The calculation of n starts with the expressions of the collector currents IC1 and IC2.

1

2

11 1

22 2

1

1

BE

T

BE

T

VV CE

C SEA

VV CE

C SEA

VI I eV

VI I eV

(83)

The base-emitter voltages of the transistors are equal due to the circuit topology. Calculating the ratio of the two collector currents leads to

2 2 1 1 2 2 12 1 1

1 1 1 1

1S EA CE CE CE S CE CEC C C

S EA CE S CE EA

I V V V V I V VI I II V V I V V

(84)

The input current is determined by writing Kirchhoff's current law at the input node:

1 21 1 2 1

2 2 11 1

2 1

11 1

C Cin C B B C

S CE CEC C

S EA CE

I II I I I I

I V VI II V V

(85)

The output current can be identified from the schematic as Iout=IC2. In this case the current gain results:

2

1 12

2

1 1

1

11 1

S

S EA CEout C

in in S

S EA CE

I VI V VI In

I I I VI V V

, (86)

where ΔV=VCE2-VCE1=Vout-Vin is the input-output voltage imbalance. Ideally, if the transistor β approaches in-finity and the mirror is balanced in voltage, the current gain only depends on the emitter ratios of Q2 and Q1. If the input and the output voltages are balanced and β is finite, the current gain becomes

2 2

1 12 2S

S

I AnI A

(87)


The input resistance is calculated from the small signal model illustrated in Figure 17. The diode con-nection of the Q1 transistor, the base-emitter voltage VBE1 is equal to the collector-emitter voltage VCE1. Con-sequently, the current provided by the gm1VBE1 source is defined by the voltage across the source's own termi-nals. In this case, the source obeys Ohm's law and is transformed into a simple resistance with R=1/gm1 (see the second model in Figure 17). The input resistance of the mirror is then simply written

1 1 21 1

1 1|| || ||inin BE CE BE

in m m

VR r r rI g g

(88)

The expression above shows that, if the base-emitter and collector-emitter resistances are considered to be very large, typically much larger than 1/gm, then the input resistance of the mirror is approximately the same as the Rin of the MOS implementation.


18

Figure 17. Small signal model of the simple bipolar transistor current mirror


The output resistance of the simple bipolar current mirror is the output resistance of the source imple-mented with the transistor Q2.

2 2 2 2 2out

out out m BE CE out CE out CEout

VV I g V r I r R rI

(89)

The practical lowest output voltage of the mirror is defined by the biasing condition of the Q2 tran-sistor in the forward active region and is approximately equal to VBE2.

1.2.2. The simple bipolar current mirror with β compensation

The bipolar current mirror with β compensation (sometimes mentioned as emitter follower augmented) is a solution meant to improve the precision of the current gain by increasing the effective β of the transistors in the simple current mirror. The schematic of the circuit is given in Figure 18.

Figure 18. Schematic of the simple bipolar current mirror with β compensation

The purpose of the Q3 transistor is to decrease the current loss in Iin caused by the base currents of Q1 and Q2. The current gain n is determined in a similar manner as for the simple bipolar mirror. The collector currents of Q1 and Q2 are written again

1

2

11 1

22 2

1

1

BE

T

BE

T

VV CE

C SEA

VV CE

C SEA

VI I eV

VI I eV

(90)

The input current is


19

3 1 21 21 3 1 1 11 1 1

E C CB Bin C B C C C

I I II II I I I I I

(91)

After replacing IC2 from the equation (84), the collector current of Q1 becomes

12 2 1

1 1

11 11 1

inC

S CE CE

S CE EA

III V V

I V V

(92)

The equation (84) can be used again, this time to express Iout=IC2 as a function of Iin. The current gain is then

2

1 12

2

1 1

1

11 11 1

S

S EA CEout C

in in S

S EA CE

I VI V VI In

I I I VI V V

(93)

By comparing equations (86) and (93) it results that the β of Q1 and Q2 have been replaced by the en-hanced gain β(β+1). If the input and the output voltages are balanced, then the gain will exhibit a weak de-pendence on β according to

2

22

1 2S

S

InI

(94)


The input resistance is calculated from the small signal model given in Figure 19.

Figure 19. Small signal model of the simple bipolar transistor current mirror with β compensation

The input voltage of the mirror is

1 3in BE BEV V V (95)

The base-emitter voltages VBE1 and VBE3 of Q1 and Q3 can be found by writing Kirchhoff's current law at the input and at the base of Q1. The sum of currents at the input node is

31 1

1 3

in BEin m BE

CE BE

V VI g Vr r

(96)


20

Similarly, the sum of currents at the Q3 base terminal is

3 1 1 13 3

3 3 1 2

BE BE BE BEm BE

BE CE BE BE

V V V Vg Vr r r r

(97)

By rearranging the terms in equation (97), the base-emitter voltage VBE1 results as a function of VBE3.

1 3 3 3 3 1 2 33 1 2 3 3

1 1 1 1 1 || ||BE BE m BE m BE BE CEBE BE BE CE BE

V V g V g r r rr r r r r

(98)

In the next step VBE1 can be replaced in (96) which leads to

1

3

1 3 1 2 33 3

1 1 || ||

inin

CEBE

m m BE BE CEBE BE

VIrV

g g r r rr r

(99)

The base-emitter voltage of Q1 is then

3 1 2 31 3

1

1 3 1 2 33 3

1 || ||

1 1 || ||

inin m BE BE CE

CE BEBE

m m BE BE CEBE BE

VI g r r rr r

Vg g r r r

r r

(100)

The input resistance results by inserting equations (99) and (100) into (95) and expressing the ratio of the input voltage to the input current.

3 1 2 33

11 3 1 2 3

3 1 1 3

11 || ||1

1 1 1 1 || ||

m BE BE CEBEin

inin m

m m BE BE CEBE CE CE BE

g r r rrVR

I gg g r r r

r r r r

(101)

The expression of the input resistance is rather complicated, but if rBE and rCE of the transistors are considered to be very large, then the approximated Rin is the same as for the fundamental current mirror.


The output stage of the mirror has not been changed by the β compensation transistor. Consequently, the output resistance remains the same and is Rout=rCE2. The lowest allowed output voltage required for bia-sing the transistors is also identical

1.2.3. The simple bipolar current mirror with resistive degeneration

The bipolar current mirror with resistive degeneration is a form of the fundamental current mirror in which the degeneration resistor is added for higher output resistance and for lower sensitivity of the gain to the input-output voltage imbalance. The schematic of the mirror is given in Figure 20.

If the transistors are perfectly matched and their collector currents are considered to be equal (β very large) then VBE1=VBE2 and Kirchhoff's voltage law leads to the expression of the current gain.

11 1 2 2

2

outBE in BE out

in

I RV I R V I R nI R

(102)


21

Figure 20. Schematic of the simple bipolar current mirror with resistive degeneration

The equation (102) holds true only if the base emitter voltages are equal. This condition translates to identical emitter areas for Q1 and Q2. If a current gain other than unity is necessary, the emitter areas must be scaled proportionally with the resistance ratio in order to let VBE1 and VBE2 to be maintained equal.

21 2

2 1 1

S

S

IR An nR I A

(103)

If the condition in (103) is fulfilled, then the current gain is relatively independent of the input-output voltage imbalance and the finite β of the transistors. This can be seen by plotting the variation of n with the voltage imbalance as illustrated in Figure 21. The current gain remains approximately constant over a wide range of voltage differences as long as the output transistor is correctly biased in the forward active region.

Figure 21. Variation of the degenerated bipolar current mirror gain against the input-output voltage imbalance


The input resistance is calculated from the small signal model given in Figure 22. The output voltage is considered to be Vout=0 according to Norton’s theorem.

Figure 22. Small signal model of the simple bipolar transistor current mirror with re-sistive degeneration


22

The Q1 transistor is connected as a diode and VBE1=VCE1. Therefore, the current source gm1VBE1 is con-trolled by the voltage drop across its own terminals and the source can be replaced by an equivalent resis-tance 1/gm1. Kirchhoff’s voltage law written for the input node yields

2 22 2

2

BEin BE out

BE

V RV V I Rr

(104)

After rearranging the terms the output current can be expressed as a function of VBE2.

22 2 2

1 1inout BE

BE

VI VR R r

(105)

The input voltage is also

22 2 2 2

2

0BEout out m BE CE out

BE

VV I g V r I Rr

(106)

Replacing Iout with (105) in (106) leads to the Q2 base-emitter voltage VBE2 written as a function of Vin.

2 2

22 2

2 2 22 2

1

in CEBE

CE CEm CE

BE

V r RV

r rR g rR r

(107)

In order to find the input resistance, the input voltage Vin is written as a function of Iin, Iout and VBE2.

21 1 1

2 1

1 || ||BEin in BE CE

BE m

VV I R r rr g

(108)

Next, VBE2 is replaced with (107), and the terms in equation (108) will only depend on Vin and Iin. The input resistance is then

1 1 11

11

1 1 1 2 21

2 22 2 2 2 2 2

2

1

1 || ||1

1 || ||1

BE CEmin

inin m

BE CE CEm

CEBE CE m CE

BE

R r rgVR R

I gR r r r Rg

r Rr r R g r Rr

(109)

If the rCE and rBE resistances of the transistors are considered to be much larger than 1/gm1 and R2, then the input resistance is approximated by the sum of the diode resistance 1/gm1 and the passive resistance R1.


The output resistance is determined from the same small signal model in Figure 22, but this time the input current is considered to be Iin=0, according to Thevenin’s theorem.

Kirchhoff’s voltage law written at the output node gives

22 2 2 2

2

BEout out m BE CE out

BE

VV I g V r I Rr

(110)


23

The base-emitter voltage of Q2 is found by using the expression of the input voltage

2 2

2 2 1 1 12 2 10

1 || ||BE BEin BE out in BE CE

BE BE m

V VV V I R I R r rr r g

(111)

If Iin=0, then VBE2 is a function of Iout

22

1 112 1

2 2 2

1 || ||1

BE out

BE CEm

BE BE BE

RV Ir r

gR Rr r r

(112)

After replacing VBE2 in the equation (110), the output resistance results

1

22 2 2

22 2 2 2 2 2 2

1 112 1

2 2 2

1

1 || ||1

m CEBEout

out CE CE m CEout

BE CEm

BE BE BE

RR g rrVR r R r R g r R

I r rgR R

r r r

(113)

The equation above shows that, as expected, the output resistance resembles the Rout of a simple MOS current source with resistive degeneration.

The lowest required output voltage must satisfy the biasing condition of Q2 in the forward active re-gion and must also cover the voltage drop across the R2 resistor. In low voltage applications the passive re-sistor degeneration is often effectively replaced by a cascode structure.

1.2.4. The bipolar cascode current mirror

The topology of the bipolar cascode current mirror is identical with the topology of the MOS version. The circuit is illustrated in Figure 23.

Figure 23. Schematic of the bipolar cascode current mirror

The current gain is determined in a similar manner as for the previously discussed bipolar mirrors. The finite β and the input-output voltage imbalance will influence the accuracy of the current gain. The input current of the mirror results from Kirchhoff’s current law at the input node:

3

43 3 4 3 1

E

Ein C B B E

I

II I I I I

(114)


24

The emitter currents of Q3 and Q4 can be identified from the schematic as

1 2

3 1 1 2 1

4 2

C CE C B B C

E C

I II I I I I

I I

(115)

The input current is then

1 21 1 11

1in C CI I I

(116)

By using the equation (84) that relates IC2 and IC1 in the fundamental mirror Q1-Q2 the input current be-comes

2 2 11

1 1

1 1 11 11

S CE CEin C

S CE EA

I V VI II V V

(117)

The output current can be written as

2 2 14 4 2 1

1 1

11 1 1

S CE CEout C E C C

S CE EA

I V VI I I I II V V

(118)

The current gain results by calculating the ratio of Iout to Iin from equations (117) and (118).

2 2 1

1 1

2 2 1

1 1

11

1 2 11 11

S CE CE

S CE EAout

S CE CEin

S CE EA

I V VI V VIn

I V VII V V

(119)

If the transistors are identical and their VBE voltages are approximately equal, then the cascode pair Q3-Q4 balances the fundamental mirror’s input and output voltages. It results that VCE1=VCE2 and n is not sensi-tive to the mirror voltage imbalance. However, the finite β of the transistors causes an input current loss and influences the current gain according to

2

2 4 2n

(120)


The input resistance is calculated for a grounded output from the small signal model in Figure 24. The gmVBE voltage controlled current sources, corresponding to transistors Q1 and Q3 in diode connection, can be replaced by a 1/gm type resistance (the same as for a simple bipolar mirror). Then, the small signal model can be simplified as shown in Figure 25, where the equivalent resistances R1 and R3 are

1 1 1 2

1 1

3 3 33 3

1 1|| || ||

1 1|| ||

BE CE BEm m

BE CEm m

R r r rg g

R r rg g

(121)

The input voltage is given by Kirchhoff’s voltage law written for the input node.


25

Figure 24. Small signal model of the bipolar cascode current mirror

Figure 25. The simplified small signal model of the bipolar cascode current mirror

41 3

4

BEin in

BE

VV I R Rr

(122)

The base-emitter voltage of Q4 is readily found to be

4 41 3

inBE BE in

VV r IR R

(123)

The small signal model shows that the resistors R1 and R3 act as a voltage divider for the input voltage. Consequently, the divider output voltage, equal to VBE1 and VBE2, is

11 2

1 3BE BE in

RV V VR R

(124)

Writing again Kirchhoff’s voltage law for the input node, this time along the path rBE4-Q2, leads to

44 2 4 2 2 2

4

BEin BE CE BE out m BE CE

BE

VV V V V I g V rr

(125)

Similarly, the output voltage is

44 4 4 2 2 2

4

0BEout out m BE CE out m BE CE

BE

VV I g V r I g V rr

(126)

The input resistance Rin is found by inserting VBE2 and VBE4 of equations (123) and (124) into (125) and (126) and then eliminating Iout. After the calculations Rin results


26

4 4 44

2 2 4

4 4 42 3 1 3 4

2 1 3 2 4 1 3 2 2 4

1

11

CE m BEBE

in CE CE CEin

in CE m BEm m m m BE

CE m m CE CE m m CE CE CE

r g rrV r r rRI r g rg g g g r

r g g r r g g r r r

(127)

This rather complicated expression can be simplified significantly if the rBE and rCE resistances of the transistors are considered to be very large, typically much larger than 1/gm.

4 4 4

2 4 1 3

1 3 4 2 1 3 1 34 4

1 3 2 4 1 11

1 1m BE CE

CE CE m min

m m CE m m m m mm BE

m m CE CE m

g r rr r g gR

g g r g g g g gg rg g r r g

(128)

If the current gain β of the transistors is sufficiently large and the base currents are neglected, the input resistance of the bipolar cascode mirror is approximately the same as for the MOS implementation.


The output resistance is determined from the same simplified small signal model given in Figure 25. The input current is set to Iin=0 according to Thevenin’s theorem. The equivalent resistances R1 and R3 have the same significance defined in (121).

The base potentials of the transistors Q1 and Q2 are found by cancelling the input current and writing the voltage drop across R1:

11 2 4

4BE BE BE

BE

RV V Vr

(129)

Similarly, the input voltage, equal to the base potentials of Q3 and Q4, can be found from Kirchhoff’s voltage law written along the resistances R1 and R3.

43 4 1 3

4

BEin B B

BE

VV V V R Rr

(130)

Writing again the sum of voltages at the input node, this time along rBE4 and the transistor Q2, leads to

43 4 4 2 2 2

4

BEin B B BE out m BE CE

BE

VV V V V I g V rr

(131)

Equaling the expressions of Vin from (130) and (131) yields

24

1 3 2 2 2 1

4 4 4

1

out CEBE

CE m CE

BE BE BE

I rV R R r g r Rr r r

(132)

The output voltage is given by Kirchhoff’s voltage law written for the output node:

44 4 4 2 2 2

4

BEout out m BE CE out m BE CE

BE

VV I g V r I g V rr

(133)

Now VBE2 of (129) and VBE4 of (132) can be replaced into the expression of the output voltage. After rearranging the terms depending on Vout and Iout, the output resistance results


27

2 2 12 4 4

42 4 2 4 4 4 2

1 2 23 2

3 4 4

1

11

CE mCE m CE

BEoutout CE CE CE CE m CE CE

m CEout CE

BE BE BE

r g Rr g r

rVR r r r r g r rR g rI R r

r r r

(134)

If the rBE and rCE resistances of the transistors are very large then the output resistance of the bipolar cascode current mirror has the same form as its MOS counterpart.

The practical minimum output voltage requirement of the bipolar cascode mirror is set by the correct biasing condition of both, Q2 and Q4, transistors in the forward active region and is typically around 2VBE.

1.2.5. The bipolar Wilson current mirror

The topology of the bipolar Wilson current mirror is identical with the MOS implementation presented in Figure 12. The MOS transistors have been replaced by bipolar transistors and the resulting schematic is gi-ven in Figure 26.

Figure 26. Schematic of the bipolar Wilson current mirror

The current gain is calculated by writing Kirchhoff's current law in each circuit node and considering the finite β of the transistors and the collector-emitter voltage imbalances.

3 2 2 11 3 1 11 1 1 1

E C C Cin C B C C

I I I II I I I I

(135)

Regrouping and rearranging the terms of the above equation yields

21

111

Cin C

II I

(136)

Now recall the relation (84) between IC1 and IC2, valid for the fundamental bipolar mirror Q1-Q2:

2 2 12 1

1 1

1S CE CEC C

S CE EA

I V VI II V V

(137)

The input current Iin is then a function of only IC1 according to

2 2 11

1 1

11 11

S CE CEin C

S CE EA

I V VI II V V

(138)

The output current of the mirror Iout is


28

3 3 2 2 11 1out C E C B BI I I I I I

(139)

Expressing IB1 and IB2 as functions of IC1 and IC2 leads to

1 2 2 12 1

1 1

1 11 1

C S CE CEout C C

S CE EA

I I V VI I II V V

(140)

The current gain results by calculating the ratio Iout/Iin from the equations (138) and (140).

2 2 1

1 1

2 2 1

1 1

1 11

11 11

S CE CE

S CE EAout

in S CE CE

S CE EA

I V VI V VIn

I I V VI V V

(141)

The VCE1 voltage can never be equal to VCE2 due to topology imposed constraints. From the schematic results that the identity VCE1=VCE2+VBE3 holds true and the voltage imbalance of the fundamental mirror Q1-Q2 is ΔV=VBE3. The current gain n is then affected by both the finite β and the voltage imbalance.


The input resistance is calculated for Vout=0 according to Norton's theorem. The calculations are per-formed on the small signal model given in Figure 27.

Figure 27. Small signal model of the bipolar Wilson current mirror

The transistor M2 is connected as a MOS diode, its base-emitter voltage being equal to the collector-emitter voltage. Consequently, the current delivered by the source gm2VBE2 in the small signal model will be controlled by the voltage drop across the source's own terminals and the source can be replaced by a resis-tance taking the value 1/gm2. It results, that the resistances rBE1, rBE2, 1/gm2 and rCE2 will be all connected in parallel, forming the equivalent resistance R2.

2 1 2 22 2

1 1|| || ||BE BE CEm m

R r r rg g

(142)

The small signal model is then simplified as shown in Figure 28. Kirchhoff's voltage law written for the input node gives


The base-emitter voltage VBE2 may be expressed from the output branch of the mirror as shown in the equation (144).


29

Figure 28. The simplified small signal model of the bipolar Wilson current mirror

32 2

3

BEBE out

BE

VV R Ir

(144)

The input voltage from the equation (143) becomes

3 22 3 2 3

3 3

1BEin out BE out BE

BE BE

V RV R I V R I Vr r

(145)

The output current results after writing Kirchhoff's voltage law for the output node.

33 3 3 2 3 3 3 3 2

3

0BEout CE out m BE BE CE out m CE BE out

BE

VV r I g V V r I g r V R Ir

(146)

This equation is solved for Iout:

3 3 3 23

3 3 2

m CE BEout BE

BE CE

g r r RI Vr r R

(147)

After inserting Iout into the expression (145) and rearranging the terms, VBE3 results

3 3 2

33 3 2 3 2 3 31

in BE CEBE

BE CE CE m BE

V r r RV

r r R r R g r

(148)

The Vin voltage can be again calculated by writing Kirchhoff's voltage at the input node, this time on the path through Q1.

31 1 1

3

BEin CE in m BE

BE

VV r I g Vr

(149)

By considering VBE1=VBE2 and successively eliminating VBE2, VBE3 and Iout from the equations, the input voltage Vin can be written as a function of the input current Iin, and the input resistance results

1 3 3

2 3

13 3

2 3

11 1 1

11 11

inin

inm m BE

CE

CEBE m

CE

VRI g g r

R rr

r gR r

(150)


30

If the rBE and rCE resistances are considered to be very large and R2=1/gm2, the Rin can be approximated

2 3

1 3

m min

m m

g gRg g

, (151)

which is the same expression as obtained for the MOS implementation of the Wilson mirror.


The output resistance is calculated from the same simplified small signal model in Figure 28 where the input current is Iin=0 according to Thevenin's theorem.

Kirchhoff's voltage law written for the output node gives the equation

3 3 3 2out CE out m BE BEV r I g V V (152)

The unknown voltages in this equation are VBE2 and VBE3. The base-emitter voltage of Q2 can be identi-fied from the small signal model as a function of VBE3 and the output current Iout.

32 2

3

BEBE out

BE

VV R Ir

(153)

In the next step the input voltage Vin is written by using Kirchhoff's voltage law at the input node.

22 3 2 3

3

1in BE BE out BEBE

RV V V I R Vr

(154)

An alternative expression of the input voltage is found by applying Kirchhoff's voltage law along the transistor Q1.

2

3 11 1 1 1 1 2 3

3 30 BE

BE CEin CE in m BE m CE BE BE

BE BEV

V rV r I g V g r V Vr r

(155)

Replacing VBE2 with its expression from (153) leads to

1 1 1 21 1 2 3

3

CE m CEin m CE out BE

BE

r g r RV g r R I Vr

(156)

The base-emitter voltage of Q3 results as a function of Iout after matching the two expressions of Vin from the equations (154) and (156).

31

3 2 1 1 3 1

1 1 11

outBE

CE

BE m CE BE CE

IVr

r R g r r r

(157)

The voltage VBE3 is the inserted into the equation (153) of VBE2 yielding

21 1

2 3 1

11out

BEm CE

BE CE

IV g rR r r

(158)

Now, VBE2 and VBE3 can be replaced in the expression (152) of Vout. As all terms are functions of either


31

Iout or Vout, the output resistance results

3 33

1 11

2 3 13 2 1 1 3 1

1111 1 1

1

out m CEout CE

m CEout CE

BE CEBE m CE BE CE

V g rR r g rI rR r rr R g r r r

(159)

If rBE and rCE resistances are considered to be very large and R2 is equal to 1/gm2, the output resistance can be approximated as

3 33

2

3 1 3 1

1 1 1m CE

out CEm

BE m BE CE

g rR rg

r g r r

(160)

Since the transistors Q1 and Q2 are identical and their collector currents are very similar, the transcon-ductances gm1 and gm2 can be also considered to be equal. The output resistance can further be simplified

3 3 1 3

1 32m CE CE BE

outCE BE

g r r rRr r

(161)

If the base-emitter resistance rBE3 approaches infinity, the output resistance will have the same appro-ximated expression as the MOS implementation of the mirror.

The lowest allowed output voltage is defined by the correct biasing of all transistors in the forward active region. The schematic of the mirror suggests that practical Wilson mirrors require around 2VBE voltage to operate correctly.

1.2.6. The balanced bipolar Wilson current mirror

The Wilson current mirror in Figure 26 can be balanced in order to reduce the sensitivity of the current gain to the input-output voltage mismatch. The symmetry of the mirror is achieved by inserting a fourth tran-sistor (Q4) into the scheamtic as shown in Figure 29.

Figure 29. Schematic of the balanced bipolar Wilson current mirror

The current gain of the balanced Wilson mirror can be found bys performing a similar derivation as for the unbalanced implementation. The finite transistor β-s and the voltage mistmatch of the fundamental mirror Q1-Q2 are taken into account. The current Iin can be written by applying Kirchhoff's current law at the input node.

3 34 44 4 3 41 1 1 1

E EE Ein C B B E

I II II I I I I

(162)

By replacing IE4 with IC1 and IE3 with IC2+IB1+IB2 the input current becomes


32

22 1 2 2

1 11

1 1 1 1C C C C

in C CI I I II I I

(163)

Considering the relation (84) between IC1 and IC2 of the fundamental mirror Q1-Q2,

2 2 12 1

1 1

1S CE CEC C

S CE EA

I V VI II V V

, (164)

leads to

22 2 1

11 1

1 11

S CE CEin C

S CE EA

I V VI II V V

(165)

The output current can now be written

3 1 2 13 2 1 2 2 21 1 1 1

E C C Cout C C B B C C

I I I II I I I I I I

(166)

By using again the equation (84), the output current will be

2 2 11

1 1

1 11

S CE CEout C

S CE EA

I V VI II V V

(167)

The current gain results after dividing the output current of (167) to the input current of (165)

2 2 1

1 12

2 2 1

1 1

1 11

1 11

S CE CE

S CE EAout

in S CE CE

S CE EA

I V VI V VIn

I I V VI V V

(168)

The voltages VCE1 and VCE2 are equal due to the symmetrical cascode transistors. If all transistors are identical, then the current gain is independent on the voltage mismatch and can be written

2

2

22 2

n

(169)


The input resistance is calculated from the small signal model given in Figure 30, where Vout=0 accor-ding to Norton's theorem. The initial small signal model can be further simplified. Recall that for diode con-nected transistors VBE=VCE and the current through the device is defined by the voltage drop across its own terminals. Consequently the transistor is simply replaced by a 1/gm type resistance in the small signal model. By replacing Q4 and Q2 with the appropriate resistors, the model in Figure 30 can be simplified as illustrated in Figure 31. The equivalent resistances R2 and R4 are identified as

2 1 2 2

2 2

4 4 44 4

1 1|| || ||

1 1|| ||

BE BE CEm m

BE CEm m

R r r rg g

R r rg g

(170)


33

Figure 30. Small signal model of the balanced bipolar Wilson current mirror

Figure 31. The simplified small signal model of the balanced bipolar Wilson current mirror

Kirchhoff's voltage law, written for the input branch of the mirror, gives


A first relation between VBE2 and VBE3 can be obtained by writing VBE2 as the voltage drop across the terminals of the resistor R2.

32 2

3

BEBE out

BE

VV R Ir

(172)

The second equation is

3 3 3 2 0out CE out m BE BEV r I g V V (173)

After inserting VBE2 of (172) into (173), the base-emitter voltage VBE3 of Q3 becomes

3 2

32

3 33

out CEBE

m CEBE

I r RV Rg r

r

(174)

The VBE2 voltage is then

2 3 3 3

23 3 3 2

1out CE m BEBE

m CE BE

I R r g rV

g r r R

(175)

Replacing VBE2 and VBE3 in the equation (171) leads to the expression of the output current as a func-tion of Vin.


34

3 3 3 2

3 3 2 2 3 3 31m CE BE

out inBE CE CE m BE

g r r RI Vr r R R r g r

(176)

VBE2 and VBE3 are then

33

2

32 3 3

3 23

32 3 3

1

1 1 1

1 1

1 1 1

in mBE

BE

mCE BE

inCE

BE

mCE BE

V gr

Vg

R r r

Vr R

Vg

R r r

(177)

The input resistance is found by writing Kirchhoff's voltage law along the path R4-Q1.

3 34 1 1 1

3 3

BE BEin in CE in m BE

BE BE

V VV R I r I g Vr r

(178)

Next the VBE1=VBE2 and VBE3 voltages are replaced with their expressions from (177). In this case, the input resistance results

1 1

3 32 3 1 4

1 43 3

2 3 3

11 1 1

11 1 1

inin

m CEinm BE

CE CE

CEBE m

CE BE

VR g rI g rR r r R

r Rr g

R r r

(179)

If rBE and rCE are considered to be very large, the Rin can be approximated as

2 3

2 1 3 3 1 3

1 3 2 3

11

m min

m m m BE m m

CE BE m m

g gR g g g r g gr r g g

(180)


The output resistance is calculated from the same simplified small signal model in Figure 31 for iin=0 according to Thevenin's theorem. First, the output voltage is written along the output branch of the mirror.

3 3 3 2out out m BE CE BEV I g V r V (181)

The base-emitter voltage VBE2 is found from the model by writing the current through R2 and applying Ohm's law.

32 2

3

BEBE out

BE

VV I Rr

(182)

Now, Kirchhoff's voltage law is written twice for the input voltage, once along the rBE3 and the R2 re-sistances and next along the input branch of the mirror.


35

3 1

3 34 1 1 1

3 30 0

in BE BE

BE BEin in in m BE CE

BE BE

V V V

V VV I R I g V rr r

(183)

By eliminating VBE1=VBE2 from the equations (182) and (183), the VBE3 voltage results as a function of the output current.

1 1

34 1 1 1

2 3 2 3 3

11 1

out m CEBE

CE m CE

BE BE BE

I g rV R r g r

R r R r r

(184)

Replacing this VBE3 into the equation (182) leads to the expression of VBE1=VBE2.

4 1

31 2

4 1 1 1

2 3 2 3 3

1

1 1

CEout

BEBE BE

CE m CE

BE BE BE

R rIr

V V R r g rR r R r r

(185)

Finally, VBE2 and VBE3 are inserted into (181) and the output resistance results

4 1

3 3 1 13

34 1 1 1

2 3 2 3 3

1 1

1 1

CEm CE m CE

BEout CE

CE m CE

BE BE BE

R r g r g rrR r R r g r

R r R r r

(186)

If the resistances rBE - rCE are considered to be very large and gm1 is equal to gm2, then the simplified expression of Rout is

3 3 1 3

1 32m CE CE BE

outCE BE

g r r rRr r

, (187)

which is identical to the approximated output resistance of the unbalanced Wilson mirror. In practical implementations both the input and the output voltages must be larger than 2VBE in order

to accommodate the correct biasing of all transistors in the forward active region.

Bibliography

1. P.E. Allen, D.R. Holberg, CMOS Analog Circuit Design, Oxford University Press, 2002 2. B. Razavi, Design of Analog CMOS Integrated Circuits, McGraw-Hill, 2002 3. D. Johns, K. Martin, Analog Integrated Circuit Design, Wiley, 1996 4. P.R.Gray, P.J.Hurst, S.H.Lewis, R.G, Meyer, Analysis and Design of Analog Integrated Circuits,

Wiley,2009 5. R.J. Baker, CMOS Circuit Design, Layout and Simulation, 3rd edition, IEEE Press, 2010

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