cu cmp: macro-scale manufacturing for nano-scale quality ... · - 22 - laboratory for manufacturing...

Cu CMP: Macro-scale Manufacturing for Nano-scale Quality Requirements

Jung-Hoon Chun

Laboratory for Manufacturing and Productivity Massachusetts Institute of Technology

Cambridge, MA 02139

April 23, 2009

- 2 - Laboratory for Manufacturing and Productivity

Manufacturing in the US (2007 Federal Bureau of Economic Analysis Data)

Output: 1.6 trillion dollars

20% of the world output

13.4% of the US GDP

Slow growth rate/declining economic sector

Weak in consumer goods

Strong in durable and high value added goods

High productivity and innovation driven manufacturing


Nano-scale Science & Technology

Understanding phenomena at nano-scale

Utilizing nano-scale phenomena/behaviors

Producing nano-scale features


Cleanwafer

Photoresistcoating

Exposure

Development

Etching

Cleanwafer

Plating

CMP

MetallizationwithCu:Macro-scale Manufacturing for Nano-scale Quality Requirements


Outline

Extrusion Spin Coating

Non-Uniform Planarization during Cu CMP

Nano-Scale Scratching in Cu CMP


ConventionalSpinCoating

(a) Deposition (b) Spin-up

(c) Spin-off

a Ω

Ω 1 Ω 1


ProblemswithSpinCoating

Aninitialcoatinglayerisestablishedusinganinefficientcoatingmethod(~70%waste)

Properamountofphotoresisttoobtainspecificcoatingthicknessanduniformityisunpredictableo Photoresistiswastediftoomuchisappliedo Incompletecoverageordefectsoccuriftoolittleisapplied


Extrusion-SpinCoating

Deposition:Depositresistontowafer

Spin-up:Acceleratewafertoobtaininitialcoatingthickness

Spin-off:Spinathighspeedtofinalthickness

Deposition:Applythinlayerofresistbyextrusioncoating

Spin-off:Spinathighspeedtofinalthickness

ConventionalSpinCoating Extrusion-SpinCoating


ExperimentalApparatus


CoatingThicknessProfile

Spincoatedat3000RPMin100%solventconcentrated

environment:0.622mmwith12Å

Extrusion-Spincoatedat1500RPMin100%solventconcentratedenvironment:0.841mm

with6Å

Spincoatedat3000RPMin0%solventconcentratedenvironment:

0.772mmwith78Å

100 mm

1 µm


Cu CMP Process Surface Non-uniformity


Polishing Stages: Feature and Wafer-Level


Key model parameters: α , β and SCu/Ox

Approach:

Control Strategy for Dishing and Erosion

Cu

SiO2


Avoid overpolishing by translating pad away from polished center region:

Face-up Chemical-Mechanical Polishing


Patterned Wafer Polishing Experiments SKW6-2 200-mm Cu/SiO2 Test Wafer


Patterned Wafer Polishing Experiments Dielectric Erosion

w (µm) Mean (nm) Std. Dev. (nm) Mean/hI Std. Dev./hI

5 28.66 12.19 0.03 0.01 10 23.13 8.55 0.03 0.01 20 12.79 6.70 0.02 0.008 50 6.12 5.32 0.01 0.006

100 0.82 0.86 0.001 0.001

Table: Dielectric erosion after face-up CMP.


Patterned Wafer Polishing Experiments Cu Dishing

w (µm) Mean (nm) Std. Dev. (nm) Mean/hI Std. Dev./hI

2.5 27.31 3.04 0.03 0.003 3.5 40.72 2.72 0.05 0.003 4.5 22.96 2.07 0.03 0.002

5 72.48 12.16 0.09 0.01 10 155.84 17.67 0.18 0.02 20 222.64 19.67 0.26 0.02 50 434.95 34.74 0.51 0.04

100 576.42 30.59 0.68 0.03

Table: Cu dishing after face-up CMP.

Wafer-scale variation is low. Once parameters are optimized, e.g. barrier slurry and stiffer pad with

in-situ conditioning, dishing can be low across the entire wafer.


Patterned Wafer Polishing Experiments SKW6-2 200-mm Cu/SiO2 Test Wafer

Feature-scale non-uniformity


Controlling Feature-scale Non-uniformity Spin Coating

Feature-scale non-uniformity is high for wide interconnects:

Even though wafer-scale polishing is controlled by face-up polishing, dishing is still dependent on feature-scale non-uniformity.

Must minimize α and hsi to minimize dishing. Previous attempts to fill Cu trenches by

electroplating were unsuccessful for wide structures, w > 10 µm.

Can fill trenches by spin coating a layer of polymer, e.g. photoresist on the wafer prior to polishing.

Ideal

Actual

Spin Coated


Controlling Feature-scale Non-uniformity Spin Coating, Step Coverage

w (µm) Step-height (nm)

No Coating hSU-8 = 1 µm hSU-8 = 2 µm hSU-8 = 4 µm

5 732 28 16 12

10 1135 58 33 30

20 1132 77 45 36

50 1133 455 63 61

100 1173 1096 396 194

Table: Interconnect step-heights after spin coating with SU-8 of various thicknesses.


Face-up Polishing Summary


Summary

Polishing experiments were conducted on patterned Cu wafers to validate wafer-scale uniformity.

Material removal was fairly uniform across a 100-mm region.

Erosion for all subdies was below 30 nm. Dishing ranged from 23 nm to 576 nm, increasing with linewidth,

but variation was less than 35 nm for all subdies.

Dishing can be reduced by minimizing feature-scale non-uniformity – spin coating wafers with SU-8 photoresist improved feature-scale uniformity and reduced dishing.


Scratching in CMP

1 µm

Source: Intel

Cu Low-k Dielectric


Thank You!

cu cmp: macro-scale manufacturing for nano-scale quality ... · - 22 - laboratory for manufacturing...

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