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Challenges

With

Package

Challenges

With

Package

on

Package

(on

Package

(PoPPoP)

)

ec no ogyec no ogyGreg Caswell

Sr. Member of the Technical Staff

CTEA meeting

2004 2010

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gen agen a PoP Back round Root Cause

Configurations andExamples

Next Generation PoP Through Mold Via

PoP compared to SiP

Assembly

Drop Testing Impact

Reliability

Underfill

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ene s

o

ene s

o

oo The benefits of PoPare well known. They include Less board real estate Better performance (shorter communication paths

between the micro and memory) ower uncton temperatures at east compare to

stacked die)

Greater control over the supply chain (opportunity to

Easier to debug and perform F/A (again, compared tostacked die or multi-chip module or system in package)

logic manufacturer, the top package is the memorymanufacturer, and the two connections (at least for one-pass) are the OEM

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ac age

on

ac age

oac age

on

ac age

o A confi uration where two acka ed inte rated

circuits are placed directly on top of each othero Can also be known as stacked packages

Interconnects are between the top package and

o Top package traditionally contains multiple orstacked die

o Bottom package traditionally contains smaller /thinner die

4

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o

ac e

so

ac e

s Bottom Package

o

to allow for top PoPattacho Molded using special process to

keep perimeter clearo

allow for top package clearance

Top Packageo Based on conventional stacked die BGA but larger ball size

and thinner mold bodyo Ball pitch and size constrained by need to clear bottom

package

Packages must be capable of being placed on the printedcircuit board (PCB) and reflowed simultaneously to eachother and to the board

5

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o

ac e

s

con .o

ac e

s

con . Both packages are relatively thin

o Maximum height typically 1.4 to 1.6 mmo Focus tends to be on slimming top package

T nnng o ottom pac age can e cuo Thinner substrate can increase warpageo Smaller ball size can impact drop testing and temp

Standard package sizes

o ,o 0.65mm pitch, with 0.5mm and 0.4mm availableo Ball size can vary from 0.45 to 0.35mm

6

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PoP

Exam lesPoP

Exam les Stacked Package on Package (PoP): The placement is oftenarranged through a soldering operation, but can also be performed

Example of

package on

pac age ev ce

from Samsung

Example of package

on package devices,

w s ac e e neach package, from

Mitsubishi

7

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o

xamp es

con .o

xamp es

con .

8

Texas Instruments

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WhyWhyPoPPoP?? Yield / Flexibility / Ownership

No issues with known good die(KGD)

Memory can be easilyupgraded

o Also allows for multiple

sourcing

Ownership is clearly defined

o Bottom package: Logic

manuf.o Top package: Memory

manuf.

o Board level connection: OEM

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Thermal

Com arisonThermal

Com arison

10

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o

seso

ses Dominant use

o Integration of digital logic device in bottompackage with combination memory devices (i.e.

o Top package typically stacked die

Some pure memory PoPsolutions also available

o Increasing interest from high rel industries

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o

ssem y

rocesso

ssem y

rocess

through one or two reflows

reflow (aka, one-pass)

Top package is typically

oFlux (sticky) or solder paste

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o

ssem y

con .o

ssem y

con .

PoPcan also be offeredas a two-pass assembly

o IDM assembles top and

bottom package and places-level assembly

Other assembly options include use of solder onpad (SoP) on bottom package

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o er

on

a

oo er

on

a

o Consists of solder balls

on the topside of thebottom package

Designed to induce alarger solder joint collapse

to absorb package warpage

Difficulties

(limited self-alignment)

o Top package can slide off the balls,

leading to a poor solder joint or bridging

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Design Factors Impacting Warpage

Mold

Material property

DieDie size

r n age

Thickness

am na e u s ra ePropertiesThickness

e a acMaterial propertyThickness

2011 Amkor Technology, Inc. June 2011, SMTA LSMITAmkor restricted release to SMTA

Routing

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arpagearpage Many technical challenges present in PoPassembly

o Improper re ow pro es can ea to so er a s so g ng

or migrating off the pado Excessive warpage can lead to solder ball bridging, solder

slum in head and illow defects or o en oints

Number one challenge in assembly is controlling and

matching warpage of top and bottom packageso More than 90% of the defects in PoPassembly are due to

package warpage (cit. KIC)

,temperature control and timeo The extent and degree of warpage is increasing as

substrates become thinner

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PackagePackageWarpageWarpage Due to mismatch in CTE

between the substrate, mold

o Die attach can also playa role

High Tg mold compoundsare used to balance CTE

mismatch between die andsu strate

Effect of mold compound

ecomes neg g e a re owtemperatures

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WarpageWarpage (cont.)(cont.) General warpage trend at room temp.

o Inconclusive

Some claim bottom is smiling (positive,

concave) while top is crying(negative, convex)o Others claim the reverse

Partially dependent if CTE of mold

compound is more / less thansubstrate

Example: Periphery of bottompackage is devoid of mold compound

,substrate could expand morecompared to substrate under themold compound

Desirable to have matching warpage

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arpagearpage an

e s

an

e s

19

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Thinner die and smaller die tend to minimize

warpageo Larger / thicker die tend to drive crying at RT

20

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WarpageandReflowWarpageandReflowro ero e

21

Ramkumar, 2008 European Electronic Assembly Reliability Summit

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Reliabilit :

Dro

Testin

/

Reliabilit :

Dro

Testin

/

War a eWar a e Each board was dropped

tmes per -

B22o 1500g for 0.5ms

The bottom package was

always first to fail

No significant differences in

o Reliability seemed to beindependent of yieldsand war a e

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Reliability:

Drop

Testing

/

Reliability:

Drop

Testing

/

WarpageWarpage

- -

Test vehicle was a mechanical dummy of a cell phoneThe drop-test was 3 cycles on six sides = 18 drops from 1.5m

23

- -

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DropTesting/WarpageDropTesting/Warpagecon .con .

Four different failure modesobserved during drop testing

on combination B

Combination B Low yield with ENIG surface

24

Poor warpage alignment

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UnderfillUnderfill Typically a filled epoxyo Hi h modulus (>10 GPa)

o

Range of coefficient of thermal expansion (CTE)values (16ppm 30ppm)

Improves drop test performance

bending

Improves thermal cycling robustnesso Reduce shear stress on solder

expansion mismatch

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UnderfillUnderfill DesignDesignons era onsons era ons

Design Considerations for Package on PackageUnderfill

In PoP, the top and bottom packages are usually

Both levels must be underfilled for good reliability.

They also must be filled simultaneously. e op ayer un er smore sowy an e o om

layer because of the thermal delta between the topand bottom levels.

In order to underfillboth levels simultaneously, thefluid must reach the top of the second level gap.

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Reliability:Reliability:UnderfillUnderfill andThermalCyclingandThermalCycling

Temp cycle

27

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UnderfillUnderfill and

Thermal

Cycling

(cont.)and

Thermal

Cycling

(cont.)

28

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UnderfillUnderfill and

Temperature

Cyclingand

Temperature

Cycling

Ra id time to failure for underfill D F G

Best reliability

29

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ReliabilitReliabilit Underfill is increasingly being considered for

o Improves 2nd

level reliability under drop testing

However, increasing indications that use ofunderfill may greatly reduce reliability under

Case Study (-40 to 125C)

o With underfill: 300 cycleso Without underfill: >1000 cycles

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WarpageWarpage ResolutionResolution High Density PoP(Package-

on-Package) and PackageStacking Development

Ways around package

warpageo Solder on pad (SOP)

investigations showed atendency to failure at the

bottom joints we see that the

numerous failures on the topjoints early in the testing inleg 3. For this reason a better

ball and bottom packageSOP was selected in leg4which improved the BLR

31

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Next Gen PoP: Increased - Integration,

Miniaturization, Performance & Collaboration

amics

Signal processing

P integration Bband + applications - increased pin counts

P core speed 2 3X w/ each node (1GHz @ 45nm)

Transition to FC accelerates from 65nm

ystemDy

Memory Interface

Higher speed memory interface SDRAM DDR > LP DDR2Wider memory bus 16 32

Shared to s lit bus to 2 channel architectures

kaging

llenges

Increased pin counts with size reduction requires 0.4mm pitch top and bottom

Warpage control with thinner / higher density PoP stacks

Si nal inte rit o timization decou lin ca inte ration

PaCh Power efficiency and thermal mngmt

Si / pkg co-design for PoP to optimize for cost / performance

evice

namics 65nm

400mW

rocessor

CMOS Node

Peak Power

45nm

800mW

28nm

1.2 W


D

2008 2010 2012

.

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Thru Mold Via Technology (TMV)

Enabling technology for next generation PoP reqmts Improves warpage control and PoP thickness reduction

TMV removes bottlenecks for f ine pitch memory interfaces

Increases die to package size ratio (30%)

Improves fine pitch board level reliabili ty

Supports Wirebond, FC, stacked die and passive integration


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Construction and package stack-up for the TMV PoP

Test Vehicle reported at SMTAI 2008

Reference : "Surface Mount Assembly and Board Level Reliability for High


Interconnect Technology - Joint Amkor and Sony Ericsson", Paper

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Viking RAMStack


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Summary

390million PoP components shipped in 2010 up from < 5mill ion in 2005. Forecasted to grow at same high rate as

Smart hones

DDR2 2 channel and other new memory architecturesdriving higher density PoP memory interfaces

Amkor pioneered 1st Generation PoP (PSvfBGA) and nowleading in Next Gen high density PoP with TMV

technology shipping in HVM

One pass SMT PoP stacking enables optimization of supply/ logistics and lowest total cost of ownership

TMV PoP SMT stacking study and industry report to

facilitate SMT yield / quality optimization


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