CSE477 L07 Pass Transistor Logic.1 Irwin&Vijay, PSU, 2003

CSE477VLSI Digital Circuits

Fall 2003

Lecture 07: Pass Transistor Logic

Mary Jane Irwin ( www.cse.psu.edu/~mji ) www.cse.psu.edu/~cg477

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L07 Pass Transistor Logic.2 Irwin&Vijay, PSU, 2003

Review: Static Complementary CMOS

VDD

F(In1,In2,…InN)

In1In2

InN

In1In2

InN

PUN

PDN

PUN and PDN are dual logic networks

……

High noise margins VOH and VOL are at VDD and

GND, respectively

Low output impedance, high input impedance

No static power consumption Never a direct path between

VDD and GND in steady state

Delay a function of load capacitance and transistor on resistance

Comparable rise and fall times (under the appropriate relative transistor sizing conditions)

CSE477 L07 Pass Transistor Logic.3 Irwin&Vijay, PSU, 2003

Review: Static CMOS Full Adder Circuit

B

B B

B B

B

B

B

A

A

A

A

A

AA

A

Cin

Cin

Cin

Cin

Cin

!Cout !Sum

!Cout = !Cin (!A v !B) v !A !B

Cout = Cin (A v B) v A B

!Sum = Cout (!A v !B v !Cin) v !A !B !Cin

Sum = !Cout (A v B v Cin) v A B Cin

CSE477 L07 Pass Transistor Logic.4 Irwin&Vijay, PSU, 2003

NMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals

NMOS switch closes when the gate input is high

Remember - NMOS transistors pass a strong 0 but a weak 1

A B

X YX = Y if A and B

X Y

A

B X = Y if A or B

CSE477 L07 Pass Transistor Logic.5 Irwin&Vijay, PSU, 2003

PMOS Transistors in Series/Parallel

Primary inputs drive both gate and source/drain terminals

PMOS switch closes when the gate input is low

Remember - PMOS transistors pass a strong 1 but a weak 0

A B

X YX = Y if A and B = A + B

X Y

A

B X = Y if A or B = A B

CSE477 L07 Pass Transistor Logic.7 Irwin&Vijay, PSU, 2003

Pass Transistor (PT) Logic

AB

FB

0

A

0

B

B= A BF = A B

Gate is static – a low-impedance path exists to both supply rails under all circumstances N transistors instead of 2N No static power consumption Ratioless Bidirectional (versus undirectional)

CSE477 L07 Pass Transistor Logic.8 Irwin&Vijay, PSU, 2003

VTC of PT AND Gate

A

0

B

BF= AB

0.5/0.25

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

0 1 2

B=VDD, A=0VDD

A=VDD, B=0VDD

A=B=0VDDV

out,

V

Vin, V

Pure PT logic is not regenerative - the signal gradually degrades after passing through a number of PTs (can fix with static CMOS inverter insertion)

CSE477 L07 Pass Transistor Logic.9 Irwin&Vijay, PSU, 2003

Differential PT Logic (CPL)

A

B

AB

PT NetworkF

A

B

AB

Inverse PT Network F

F

F

F=AB

A

A

B F=AB

B

B B

AND/NAND

A

A

B F=A+B

BF=A+B

BB

OR/NOR

A

A F=AB

F=AB

BB

XOR/XNOR

A

A

CSE477 L07 Pass Transistor Logic.10 Irwin&Vijay, PSU, 2003

CPL Properties

Differential so complementary data inputs and outputs are always available (so don’t need extra inverters)

Still static, since the output defining nodes are always tied to VDD or GND through a low resistance path

Design is modular; all gates use the same topology, only the inputs are permuted.

Simple XOR makes it attractive for structures like adders

Fast (assuming number of transistors in series is small)

Additional routing overhead for complementary signals

Still have static power dissipation problems

CSE477 L07 Pass Transistor Logic.12 Irwin&Vijay, PSU, 2003

CPL Full Adder

A

A

BB CinCin

!Sum

Sum

Cout

!CoutA

A

B

B

B

B Cin Cin

Cin

Cin

CSE477 L07 Pass Transistor Logic.13 Irwin&Vijay, PSU, 2003

NMOS Only PT Driving an Inverter

Vx does not pull up to VDD, but VDD – VTn

In = VDD

A = VDD

Vx = VDD-VTn

M1

M2

BSD

Threshold voltage drop causes static power consumption (M2 may be weakly conducting forming a path from VDD to GND)

Notice VTn increases for pass transistor due to body effect (VSB)

VGS

CSE477 L07 Pass Transistor Logic.14 Irwin&Vijay, PSU, 2003

Voltage Swing of PT Driving an Inverter

Body effect – large VSB at x - when pulling high (B is tied to GND and S charged up close to VDD)

So the voltage drop is even worse

Vx = VDD - (VTn0 + ((|2f| + Vx) - |2f|))

In = 0 VDD

VDD

xOut

0.5/0.25

0.5/0.25

1.5/0.25

0

1

2

3

0 0.5 1 1.5 2Time, ns

Vol

tage

, V

In

Out

x = 1.8VD

S

B

CSE477 L07 Pass Transistor Logic.15 Irwin&Vijay, PSU, 2003

Cascaded NMOS Only PTs

B = VDD

Out

M1

yM2

Swing on y = VDD - VTn1 - VTn2

xM1

B = VDD

OutyM2

Swing on y = VDD - VTn1

C = VDD

A = VDD

C = VDD

A = VDD

Pass transistor gates should never be cascaded as on the left

Logic on the right suffers from static power dissipation and reduced noise margins

x = VDD - VTn1

G

S

G

S

CSE477 L07 Pass Transistor Logic.16 Irwin&Vijay, PSU, 2003

Solution 1: Level Restorer

For correct operation Mr must be sized correctly (ratioed)

Level Restorer

M1

M2

A=0 Mn

Mr

x

B

Out =1

off

= 0A=1 Out=0

on

1

Full swing on x (due to Level Restorer) so no static power consumption by inverter

No static backward current path through Level Restorer and PT since Restorer is only active when A is high

CSE477 L07 Pass Transistor Logic.17 Irwin&Vijay, PSU, 2003

Transient Level Restorer Circuit Response

0

1

2

3

0 100 200 300 400 500

Vol

tage

, V

Time, ps

W/Lr=1.75/0.25

W/Lr=1.50/0.25

W/Lr=1.25/0.25W/Lr=1.0/0.25

W/Ln=0.50/0.25

W/L2=1.50/0.25

W/L1=0.50/0.25

node x never goes below VM of inverter so output never switches

Restorer has speed and power impacts: increases the capacitance at x, slowing down the gate; increases tr (but decreases tf)

CSE477 L07 Pass Transistor Logic.18 Irwin&Vijay, PSU, 2003

Solution 2: Multiple VT Transistors Technology solution: Use (near) zero VT devices for the

NMOS PTs to eliminate most of the threshold drop (body effect still in force preventing full swing to VDD)

Impacts static power consumption due to subthreshold currents flowing through the PTs (even if VGS is below VT)

Out

In2 = 0V

In1 = 2.5V

A = 2.5V

B = 0V

low VT transistors

sneak path

on

off but leaking

CSE477 L07 Pass Transistor Logic.20 Irwin&Vijay, PSU, 2003

Solution 3: Transmission Gates (TGs)

Full swing bidirectional switch controlled by the gate signal C, A = B if C = 1

A B

C

C

A B

C

C

B

C = VDD

C = GND

A = VDD B

C = VDD

C = GND

A = GND

Most widely used solution

CSE477 L07 Pass Transistor Logic.21 Irwin&Vijay, PSU, 2003

TG Multiplexer

GND

VDD

In1 In2S S

S S

S

S

S

In2

In1

F

F

F = !(In1 S + In2 S)

CSE477 L07 Pass Transistor Logic.23 Irwin&Vijay, PSU, 2003

Transmission Gate XOR

B

A A B

1

off

off

an inverter

B !A

0

on

on

weak 0 if !A

weak 1 if A

A !B

CSE477 L07 Pass Transistor Logic.24 Irwin&Vijay, PSU, 2003

TG Full Adder

Sum

Cout

A

B

Cin

CSE477 L07 Pass Transistor Logic.25 Irwin&Vijay, PSU, 2003

Differential TG Logic (DPL)

A

A

B

B

B

AND/NAND

F=AB

F=AB

XOR/XNOR

A

A

B

B

A

A

B

F=AB

F=AB

A

A

B

B A B A

GND

GND

VDD

VDD

B

CSE477 L07 Pass Transistor Logic.26 Irwin&Vijay, PSU, 2003

Next Time: The MOS Transistor

MOS transistor dynamic behavior (R and C)

Wire capacitance

CSE477 L07 Pass Transistor Logic.27 Irwin&Vijay, PSU, 2003

Next Lecture and Reminders Next lecture

MOS transistor dynamic behavior- Reading assignment – Rabaey, et al, 3.2.3 & 3.3.3-3.3.5

Wiring capacitance- Reading assignment – Rabaey, et al, 4.1-4.3.1

Reminders HW#2 due September 30th (Tuesday) Project specs due (on-line) October 9th Evening midterm exam scheduled

- Monday, October 20th , 20:15 to 22:15, Location TBD

- Only one midterm conflict scheduled