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Chapter 5

Interfacing and Communication

5.1 I/O Fundamentals

I/O devices cannot connect directly to the CPU because:

The formats required for different devices are different.

Some require single piece of data.

Some require a block of data

Some expect data sequentially

Some expect data parallel

Incompatibilities in speed make synchronization difficult.

Therefore, there must be:

A means to individually address different devices.

A way in which peripheral device can initiate communication with CPU. Eg, enable

response to unexpected input.

An efficient means of transferring data directly between I/O and memory for large data

transfers since programmed I/O is suitable only for slow devices and individual word

transfers

Buses that interconnect high-speed I/O devices with the computer must support high

data transfer rates

Means for handling devices with extremely different control requirements

To enable this, we need the I/O interface or I/O module.

5.1.1 I/O Interface / I/O module

Is necessary because of

Different formats required by the devices

Incompatibilities in speed between the devices and the CPU make synchronization

difficult

Bursts of data vs. streaming data

Device control requirements that would tie up too much CPU time

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Figure 5.1: I/O modules in a computer system

5.1.1.1 I/O Module Interfaces

CPU and the device (CPU interface)

Device and the CPU (Device interface)

Figure 5.2: I/O Module Interfaces

5.1.1.2 I/O Module Functions

Recognizes messages from device(s) addressed to it and accepts commands from the

CPU

Provides a buffer where the data from memory can be held until it can be transferred to

the device

Provides the necessary registers and controls to perform a direct memory transfer

Physically controls the device

Copies data from its buffer to the device/from the CPU to its buffer

Communicates with CPU

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5.1.2 I/O Techniques

There are a number of I/O techniques available.

Handshaking

Buffering

Polling

Programmed I/O

Interrupt-driven I/O

5.1.2.1 Handshaking

Provides some status bits in a secondary input port to indicate that a device is ready to

accept or transmit data.

For example, a one in a single bit in an I/O port can tell the CPU that a printer is ready to

accept more data. A zero would indicate that the printer is busy and the CPU should not

send new data to the printer.

Likewise, a one bit in a different port could tell the CPU that a keystroke from the

keyboard is available at the keyboard data port. A zero in that same bit could indicate

that no keystroke is available.

The CPU can test these bits prior to reading a key from the keyboard or writing a

character to the printer.

5.1.2.2 Programmed I/O

CPU controlled I/O

Input from device transferred from I/O module to I/O register one word at a time under

program control.

Output pass from I/O data register to I/O module under program control.

For multiple devices additional info sent with I/O instruction. Each I/O module has

identification address that allows it to identify I/O instruction addressed to it and ignore

others.

Slow full instruction cycle must be performed for each I/O data transferred.

Used with keyboards.

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5.1.2.3 Interrupt Driven I/O

Signal that causes the CPU to alter its normal flow of instruction execution

frees CPU from waiting for events

provides control for external I/O initiation

Examples

Unexpected input

Abnormal situation

Illegal instructions

Multitasking, multiprocessing

Saves registers of a program before control is transferred to the interrupt handler

Allows program to resume exactly where it left off when control returns to interrupted

program

5.1.2.4 Buffering

5.1.2.5 Polling

Technique/approach to taking care of peripheral devices.

Microprocessor checking each device in rotation at frequent intervals to see if it need

service.

The computer time spent in polling is largely wasted.

Not efficient when the processor needs to perform other tasks.

Need better system that allow processor to be free to continue normal sequential

execution and only stop to deal with a peripheral when it specially needed attention.

So that, interrupt system has been design to satisfy the requirement for external input

control and freeing the CPU from waiting for events to occur.

5.2 Interrupt

Peripheral devices demand the attention of microprocessor at various and predictable times

during normal program execution. The best example of the random need for attention is the

use of the keyboard on a computer. Every time a key is pressed, the microprocessor must

deal with an activity. Other peripheral devices such as disk drives, CRTs and printers also

need to interact with the microprocessor. Just how the microprocessor accomplishes the

task of working these devices is the subject of this device

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5.2.1 What is Interrupt

Interrupt is a call for the microprocessor to interact or service the interrupting unit.

The interrupt will cause the computer to suspend the program being executed and jump

into a special interrupt processing program.

There are many circumstances under which it would be desirable to interrupt the normal

flow of a program in the computer to react to special event.

Example:

User command from keyboard

Command from other external input

Abnormal situation power failure

Execution of an illegal instruction

Completion signaling of an I/O task

5.2.2 Interrupt Terms

Interrupt lines (hardware)

One or more special control lines to the CPU

Interrupt request

Interrupt handlers

Program that services the interrupt

Also known as an interrupt routine or device driver

5.2.3 Interrupt Capability

Allow computer to take special actions when required.

Used to time-share the CPU between several different programs at once.

Satisfy the requirement for external input control.

Provides the desirable feature of freeing the CPU from waiting for events to occur.

Provides one or more special control lines to the central processor know as interrupt

lines.

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Figure 5.3: Interrupt Request

The messages sent to the computer on these IRQ lines also known as interrupt

5.2.4 Interrupt Servicing

Lower priority interrupts are held until higher priority interrupts are complete

Suspend program in progress

Save context, including last instruction executed and data values in registers, in the PCB

or the stack area in memory

Branch to interrupt handler program

Interrupt handler program action taken by the processor when an interrupt occurs.

Also known as interrupt routine.

When interrupt occurs, the processor will then execute the interrupt routine called for.

The process of determining the appropriate course of action by the interrupt handler

program (interrupt routine) is known as servicing the interrupt.

There are 4 distinct steps that microprocessor takes after an interrupt.

1. The microprocessor finished the current instruction, until the end of an instruction

cycle.

The interrupt signal will not be acknowledge until the current instruction is carried

out.

2. Normal operation is suspended.

All the pertinent information about the program being suspended is saved /

preserved in a known part of memory. Either in a special area associated with

the program (process control block) or in a part of memory known as stack area.

Pertinent information including:

Location of the last instruction executed.

CPU

Printer

Disk Drive Keyboard

Mouse

IRQ

IRQ IRQ

IRQ

IRQ Interrupt ReQuest

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Values of data in various registers that contain pieces of information relate to the

algorithm being carried out when the interrupt occurred.

The contents of the registers and the status of microprocessor in general must be

preserved so that it can again resume operation when the interrupt has been

serviced.

3. The microprocessor jumps to the location in memory where the interrupt service

routine has been stored and executes the routine. The address of the routine may

be fixed in the microprocessor design.

4. When interrupt routine complete its task, it would return control to the interrupted

program.

The processor returns from an interrupt. The return includes restoring the

microprocessor to its exact condition before the interrupt occurred.

All registers were restored to their original values. The information they

contained must be retrieved from memory and placed back in their respective

registers.

Finally, the program counter (PC) is loaded with retrieval address of instruction

that would have been executed if an interrupt had not occurred.

The original program would resume execution exactly where it left off.

Figure 5.4: Servicing an Interrupt

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Figure 5.5: Sequence of Event During Interrupt

5.2.5 Interrupt Usage

The way in which an interrupt is used depends on the nature of the device.

There are several different ways in which interrupt are used:

As an external event notifier

Real-time or time-sensitive

As a completion signal.

Printer ready or buffer full

As a means of allocating CPU time.

Time sharing

As an abnormal event indicator.

Illegal operation, hardware error

5.2.5.1 Interrupts As An External Event Notifier

Interrupt are useful as notifiers to the CPU of external events that require action.

Frees the CPU from necessity of performing polling.

Example:

Keyboard input.

Figure 5.6 shows the steps in processing a keyboard input interrupt.

Normal Execution

Normal Execution Continues

Finish Current Instruction

Suspend Operation

Store registers

Jump to Subroutine and

Execute

Return to Normal Operation

Restore Microprocessor Status

Contents of registers stored in stack

Contents of registers returned from

stack

Interrupt

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Figure 5.6: Using a Keyboard Handler Interrupt

Keyboard input can be processed using a combination of programmed I/O and interrupt.

Suppose a key is struck on the keyboard. This causes an interrupt to occur. The current

program is suspended, and control is transferred to the keyboard interrupt handler

program. The keyboard interrupt handler first inputs the character, using programmed

I/O, and determines what character has been received. It would next determine if the

input is one that requires special action. If so, it would perform the required action, for

example, suspending the program or freezing the data on the screen. Otherwise, it would

pass data to the program expecting input from that keyboard. Normally, the input

character would be stored in a known memory location; ready for the program to use

when it is reactivated.

When the action is complete, that is, when the interrupt has been serviced, the computer

normally restores the register values and returns control to the suspended program,

unless the interrupt specifies a different course of action. This program would be case,

for example, if the user typed a command to suspend the program being run.

5.2.5.2 Interrupt As A Completion Signal

Controlling the flow of data to an output device.

Interrupt serves to notify the computer of completion of a particular course of action.

Example:

Printer

Printer is a slow output device. The computer capable of outputting characters to the

printer much faster than the printer can handle them.

Interrupt can be used to control the flow of characters to the printer in an efficient way.

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Interrupt capability prevents the loss of output and allows the printer to control the flow of

characters to a rate that printer can accept.

Allows the CPU to perform other tasks while it waits for the printer to complete its

printing.

Figure 5.7 shows this application.

Figure 5.7: Using a Print Handler Interrupt

The computer sends one or more characters at a time to the printer, depending on the

type of printer. When the printer is ready to accept more characters, it sends an interrupt

to the computer. This interrupt indicates that the printer has completed printing the

characters previously received and is ready for more characters.

In this case, the interrupt capability prevents the loss of output, since it allows the printer

to control the flow of characters to a rate that the printer can accept. Without the interrupt

capability, it would be necessary to output characters at a very slow rate to assure that

the computer did not exceed the ability of the printer to accept output. The use of an

interrupt also allows the CPU to perform other tasks while it waits for the printer to

complete its printing.

5.2.5.3 Interrupt As A Means Of Allocating CPU Time

Interrupt is used as a method of allocating CPU time to different programs that are

sharing the CPU.

The CPU can only execute one program at a time.

Time share multiple programs implies that the computer system must share the CPU by

allocating small segments of time to each program, in rapid rotation among them.

Each program is allowed to execute some instructions.

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After a certain period of time, that program is interrupted and relinquishes control to a

dispatcher program within the operating system (OS) that allocates the next block of time

to another program.

Figure 5.8 shows this application.

Figure 5.8: Using an interrupt for time sharing

The computer system provides an internal clock that sends an interrupt periodically to

the CPU.

The time between interrupt pulses is known as a quantum.

When the interrupt clock occurs, the interrupt routine returns control to the OS. OS

determines which program will receive CPU time next.

This is effective method for allowing the OS to share CPU resources among several

programs at once.

5.2.5.4 Interrupt As An Abnormal Event Indicator

Interrupt used to handle abnormal events that effect operation of the computer system.

The events are directed at the problems within the computer system itself.

Example:

Execution of an illegal instruction.

Divide by zero

Nonexistent op code

Hardware error detected

One obvious example of an external event requiring special computer action is power

failure.

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Most computers provide enough internal power storage to save the work that being

performed and to shut down gracefully, provided that the computer has quick

notification of the power failure. A power line monitor that connects to the interrupt

facility provides this capability.

The interrupt routine will save the status of programs that are in memory, close open

files, and perform other housekeeping operations that will allow the computer to

restart without loss any data. It will then halt the computer.

Another important application is when a program attempt to execute an illegal instruction

such as a divided by 0 or a nonexistent op code or when a hardware error is detected,

such as parity error.

When the error occurs it is not possible to complete the executing program.

System will attempt to recover from the error and that the appropriate personnel are

notified.

Interrupt routine can notify the user of the error and return control of the CPU to the

operating system program. You should notice that these interrupt are actually

generated from inside the CPU, whereas the other interrupt that we have discussed

so far are generated externally.

Internal interrupts are sometimes called traps or exceptions.

5.2.6 Interrupt Processing Methods

Two different processing methods are used to determine which device initiated the interrupt.

Vectored interrupt

Address of interrupting device is included in the interrupt

Requires additional hardware to implement

Polling

Identifies interrupting device by polling each device

General interrupt is shared by all devices

5.2.7 Multiple interrupts

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Figure 5.9: Multiple Interrupts

5.2.8 Types of interrupt

Interrupt can be divided into TWO categories:

Maskable

Interrupt that can be selectively disabled.

Interrupt that not be accepted.

Non-maskable

Interrupt that never disabled.

Interrupt that will always be acknowledged and accepted.

Example: power failure.

5.3 External Storage, Physical Organization, and Drives

5.4 Buses

The physical connection that makes it possible to transfer data from one location in the

computer system to another

Group of electrical or optical conductors for carrying signals from one location to another

Wires or conductors printed on a circuit board

Line: each conductor in the bus

4 kinds of signals

Data

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Addressing

Control signals

Power (sometimes)

5.4.1 Bus Characteristics

Number of separate conductors

Data width in bits carried simultaneously

Addressing capacity

Lines on the bus are for a single type of signal or shared

Throughput - data transfer rate in bits per second

Distance between two endpoints

Number and type of attachments supported

Type of control required

Defined purpose

Features and capabilities

5.4.2 Bus Categories

Parallel vs. serial buses

Direction of transmission

Simplex unidirectional

Half duplex bidirectional, one direction at a time

Full duplex bidirectional simultaneously

Method of interconnection

Point-to-point single source to single destination

Cables point-to-point buses that connect to an external device

Multipoint bus also broadcast bus or multidrop bus

Connect multiple points to one another

5.4.3 Parallel vs Serial Bus

Parallel Serial

High throughput because all bits of a word

are transmitted simultaneously

Expensive and require a lot of space

1 bit transmitted at a timed

Single data line pair and a few control

lines

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Subject to radio-generated electrical

interference which limits their speed and

length

Generally used for short distances such

as CPU buses and on computer

motherboards

For many applications, throughput is

higher than for parallel because of the

lack of electrical interference

5.4.4 Bus Protocol and Arbitration

5.4.5 Direct Memory Access

Method for transferring data between main memory and a device that bypasses the CPU

Transferring large blocks of data

CPU not actively involved in transfer itself

Required conditions for DMA

The I/O interface and memory must be connected

The I/O module must be capable of reading and writing to memory

Conflicts between the CPU and the I/O module must be avoided

Interrupt required for completion

Application program requests I/O service from operating system

To initiate DMA, programmed I/O is used to send the following information:

Location of data on I/O device

Starting location in memory

Size of the block

Read/write

Interrupt to CPU upon completion of DMA

Advantages:

Release the CPU from doing data transfer

High speed disk transfer

5.5 Stack

During an interrupt routine, some or all of the microprocessor registers may be used. This

would destroy data previously in the registers if their contents were not saved in some way.

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Obviously, to return the microprocessor to its pre-interrupt status requires a procedure to

accomplish this.

5.5.1 What is stack?

The location where the contents of the registers in the microprocessor are temporary

stored.

5.5.2 Hardware stack

A number of registers set aside within the processor to serve as the stack location.

The advantages of hardware stack are rapid access and therefore, speed.

But the size of the stack is limited by the number of registers that can be provided.

Restrict the flexibility of a microprocessor.

5.5.3 Software stack

An area in RAM for temporary storage of data and registers contents.

Building this stack is an inherent part of the interrupt signal. However, stack can also be

built independently of an interrupt request. In fact, stacks are used just about any time a

subroutine is called.

The software stack is almost unlimited in size and can reside anywhere in memory.

This implementation causes the need for a special register in the microprocessor called

the stack pointer register.

5.5.4 Stack pointer

Holds the address of the stack.

Whenever a stack is required; the stack pointer register will track its location by holding

the 16-bit stack address.

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5.5.5 Function of stacks interrupt, subroutine

There are a lot of situations that need the used of interrupt:

When a subroutine is called.

Stack is an excellent method for storing the return address and arguments for

subroutine calls.

When interrupt occurs.

When stack instruction occurs.

To store data when the most recently used data will also be the first needed.

Efficient way of storing intermediate data values during complex calculations.

5.5.6 Stack operation push, pop

The stack address is built, one byte at a time, each entered or stacked on the last entry.

It is analogous to the way plates are stack at a salad bar.

Stack of plate illustrating First In Concept

Stack of Plate Last Out Concept

The first plate put on the stack is at the bottom. The last plate off the stack is the last

plate placed of the stack.

Stack operates by LIFO (Last In First Out)

The last byte put on the stack will be the first byte retrieved from the stack, when an

interrupt is completed, for instance.

Plate stacked

First plate in

First plate in will be last plate out

Plate taken off stacked

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Stack instructions use assembly language mnemonics like PUSH, to push byte onto the

stack and PULL or POP to take a byte off the stack.

The stack builds downward.

Directions of occupied address are moving toward lower address.