cs516 programming languages and compilers iizhang.zheng/cs516_spring2015/...r1 r2 r3 r4 r5 r6 r7 r8...

CS516 Programming Languages and Compilers II

Zheng Zhang Spring 2015

Feb 12 — Global Register Allocation

Rutgers University

2

Review: Dominance Frontier

Dominance Frontiers

• DF(n ) is fringe just beyond the region n dominates

• m ∈DF(n) : iff n ∉(Dom(m) - {m}) but n ∈ DOM(p) for some p ∈ preds(m).

B1

B2 B3

B4 B5

B6

B7

B0

0 1 2 3 4 5 6 7DOM 0 0,1 0,1,2 0,1,3 0,1,3,4 0,1,3,5 0,1,3,6 0,1,7DF – 1 7 7 6 6 7 1

i.e., n doesn’t strictly dominate m

i.e., n dominates p

Flow Graph

Review: Practice Example 1

• IDOM DF phi renaming reach deconstruct

3

a = 1 a = 2

b = a

A: B:

C:

Review: Practice Example 2

• IDOM DF phi renaming reach deconstruct

4

a = 1

a = a + 1B:

A:

Compiler Back-end

• Translate IR into target machine code

• Choose instruction to implement each IR operation

• Decide which value to keep in registers

• Ensure conformance with system interface

Errors

IR Register Allocation

Instruction Selection

Machine code

Instruction Scheduling

IR IR

Responsibilities

Many of the backend problems are NP-complete

Register Allocation• Produce correct code that uses k (or fewer) registers

• Minimize the cost of spilling: cycles due to added loads & stores

• Minimize space used to hold spilled values

Errors

IR Register Allocation

Instruction Selection

Machine code

Instruction Scheduling

m register IR

k register IR

An Example• Here is a sample code sequence in SSA form

1 loadI 1028 => r1 2 load r1 => r2 3 mult r1, r2 => r3 4 loadI 5 => r4 5 sub r4, r2 => r5 6 loadI 8 => r6 7 mult r5, r6 => r7 8 sub r7, r3 => r8 9 store r8 => r1


1 loadI 1028 => r1 // r1 2 load r1 => r2 // r1 r2 3 mult r1, r2 => r3 // r1 r2 r3 4 loadI 5 => r4 // r1 r2 r3 r4 5 sub r4, r2 => r5 // r1 r3 r5 6 loadI 8 => r6 // r1 r3 r5 r6 7 mult r5, r6 => r7 // r1 r3 r7 8 sub r7, r3 => r8 // r1 r8 9 store r8 => r1 //

Live-on-exit set: the set of variables that are live on the exit of an instruction Live-on-entry set: the set of variables that are live on the exit of an instruction



r1r2

r3

r4

r5r6

r7

r8

* Nodes in GI represent values, or live ranges * Edges in GI represent individual interferences

* A k-coloring of GI can be mapped to an allocation mapped to k registers

• Interference graph

“interference”: two variables interfere if there exists an operation where both are simultaneously live

Two interfering variables cannot occupy the same register

Graph Coloring

r1r2

r3

r4

r5r6

r7

r8

• Color the interference graph

“interference”: two variables interfere if there exists an operation where both are simultaneously live

Two interfering variables (node) cannot occupy the same register (color)

• Here is a sample code sequence in SSA form1 loadI 1028 => r1 // r1 2 load r1 => r2 // r1 r2 3 mult r1, r2 => r3 // r1 r2 r3 4 loadI 5 => r4 // r1 r2 r3 r4 5 sub r4, r2 => r5 // r1 r3 r5 6 loadI 8 => r6 // r1 r3 r5 r6 7 mult r5, r6 => r7 // r1 r3 r7 8 sub r7, r3 => r8 // r1 r8 9 store r8 => r1 //

* A graph G is said to be k‐colorable iff the nodes can be labeled with integers 1 … k so that no edge in G connects two nodes with the same label

* Each color can be mapped to a distinct physical register

r1r2

r3

r4

r5r6

r7

r8

In this case, the graph is 4-colorable

• Here is a sample code sequence in SSA form

Graph Coloring

• Color the interference graph


* A graph G is said to be k‐colorable iff the nodes can be labeled with integers 1 … k so that no edge in G connects two nodes with the same label

* Each color can be mapped to a distinct physical register

Building Interference Graph• Two values interfere if there exits an operation where both are simultaneously live

• To comput interference graph, we must know where values are “live”

1 loadI 1028 => r1 2 load r1 => r2 3 mult r1, r2 => r3 4 loadI 5 => r4 5 sub r4, r2 => r5 6 loadI 8 => r6 7 mult r5, r6 => r7 8 sub r7, r3 => r8 9 store r8 => r1

Let’s start from local interference graph within a basic block

backward traversal — instruction by instruction

// r1 r8// r1 r3 r7// r1 r3 r5 r6// r1 r3 r5// r1 r2 r3 r4// r1 r2 r3// r1 r2 // r1

• Discover live ranges * Construct the SSA form of the procedure * At each Φ-function, take the union of the arguments * Rename to reflect these new “live ranges”

• Compute LIVE sets over live ranges for each basic block * Solve equations for LIVE over domain of live range names * Use a simple iterative data-flow solver

• Iterate over each block, from bottom to top * Construct LIVENOW at each point in the block, in a backward traversal * At each operation, add appropriate edges to the graph & update LIVENOW

-> Add an edge from result to each value in LIVE -> Remove result from LIVE -> Add each operand to LIVE

Building Global Interference Graph

update the LIVENOW set}






update the LIVENOW set}

Computing LIVE sets• Iterative data flow analysis

* LIVE set definition (assuming we use SSA form) -> LIVE_beg(n): the set of values that are live at the beginning of basic block n -> USE(n): the set of values that are used in basic block n -> DEF(n): the set of values that are defined in basic block n-> LIVE_end(n): the set of values that are live at the end of basic block n

* Data flow equations -> LIVE_end(n) = ∪

s∈succ(n) LIVE_beg(s)

-> LIVE_beg(n) = { USE(n } ∪ LIVE_end(n)} ∩ DEF(n) * Initialization

-> LIVE_end(sleave) = {} * Convergence

-> Fixed point algorithm -> Convergence after a limited number of steps

Computing LIVE sets• Iterative data flow analysis

* LIVE set definition (assuming we use SSA form) -> LIVE_beg(n): the set of values that are live at the beginning of basic block n -> USE(n): the set of values that are used in basic block n -> DEF(n): the set of values that are defined in basic block n-> LIVE_end(n): the set of values that are live at the end of basic block n

* Data flow equations -> LIVE_end(n) = ∪

s∈succ(n) LIVE_beg(s)

-> LIVE_beg(n) = { USE(n } ∪ LIVE_end(n)} ∩ DEF(n) * Initialization

-> LIVE_end(sleave) = {} * Convergence

-> Fixed point algorithm -> Convergence after a limited number of steps

{x0,y1,z0}

{x0,y1}

{y0} {x0,y0,z0}

{x0,z0}

{ }






update the LIVENOW set}LIVE(n) is initialized as LIVE_end(n)

Chaitin’s Algorithm• Suppose we have k registers — a k-coloring problem

• Observation * Any vertex n that fewer than k neighbors in the interference graph can always be colored!

Pick any color not used by its neighbors — there must be one

• Chaitin’s algorithm * Step 1: Pick any vertex n such that deg(n) < k and put it on the stack * Step 2: Remove that vertex and all its incident edges from the interference graph -> This may make remaining nodes have fewer neighbors * Step 3: If there does not exist such vertex, pick one vertex m and spill. Remove the vertex m and all its incident edges from the graph. Go back to step 1. Repeat Step 1, 2 and 3 until no nodes are left in the graph. * Step 4: Successively pop vertices off the stack and color them in the lowest color not used by some neighbor

Chaitin-Briggs Algorithm• Improvement over Chaitin’s algorithm

• Observation * A node that has more than k-1 neighbors is not necessarily un-colorable -> It depends the number of colors of its neighbors

• Brigg’s idea * Take that node as spilling candidate and still push into stack * When you pop it off, a color might be available for it

Maximum degree is a loose upper bound on colorability

ComparisonChaitin’s Allocator Chaitin-Briggs Allocator

Get live range & rename

Build interference graph

Copy coalescing (Kun’s presentation)

Choose a live range to spill

Remove nodes from graph

spill decision made at the

removal phase

spill decision made at the

coloring phase

the difference

cs516 programming languages and compilers iizhang.zheng/cs516_spring2015/...r1 r2 r3 r4 r5 r6 r7 r8...

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