cs141-l3-1tarun soni, summer ‘03 more alus and floating point numbers today: the rest of chap 4: ...
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CS141-L3-1 Tarun Soni, Summer ‘03
More ALUs and floating point numbers
Today: The rest of chap 4: Multiplication, Division and Floating point numbers
CS141-L3-2 Tarun Soni, Summer ‘03
Instruction Set Architectures Performance issues 2s complement, Addition, Subtraction
The Story so far:
Basically ISA and some ALU stuff
CS141-L3-3 Tarun Soni, Summer ‘03
CPU: The big picture
Instruction
Fetch
Instruction
Decode
Operand
Fetch
Execute
Result
Store
Next
Instruction° Design hardware for each of these steps!!!
Execute anentire instruction
Fetc
h
Dec
ode
Fetc
h
Exe
cute
Stor
e
Nex
t
CS141-L3-4 Tarun Soni, Summer ‘03
CPU: Clocking
Clk
Don’t Care
Setup Hold
.
.
.
.
.
.
.
.
.
.
.
.
Setup Hold
• All storage elements are clocked by the same clock edge
CS141-L3-5 Tarun Soni, Summer ‘03
CPU: Big Picture: Control and Data Path
ALUctrRegDst ALUSrcExtOp MemtoRegMemWr Equal
Instruction<31:0>
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRsRt
nPC_sel
Adr
InstMemory
DATA PATH
Control
Op
<21:25>
Fun
RegWr
CS141-L3-6 Tarun Soni, Summer ‘03
CPU: The abstract version
• Logical vs. Physical Structure
DataOut
Clk
5
Rw Ra Rb
32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress
IdealData
Memory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
CS141-L3-7 Tarun Soni, Summer ‘03
Computer Performance
Multiplication and Division
CS141-L3-8 Tarun Soni, Summer ‘03
The 32 bit ALU-limited edition
• Bit-slice plus extra on the two ends
• Overflow means number too large for the representation
• Carry-look ahead and other adder tricks
A B
M
S
32 32
32
4
Ovflw
ALU0
a0 b0
cincos0
ALU31
a31 b31
cincos31
C/L toproduceselect,comp,c-in
signed-arithand cin xor co
CS141-L3-9 Tarun Soni, Summer ‘03
The Design Process
• Divide and Conquer (e.g., ALU)– Formulate a solution in terms of simpler components.– Design each of the components (subproblems)
• Generate and Test (e.g., ALU)– Given a collection of building blocks, look for ways of putting them
together that meets requirement• Successive Refinement (e.g., multiplier, divider)
– Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings.
• Formulate High-Level Alternatives (e.g., shifter)– Articulate many strategies to "keep in mind" while pursuing any one
approach.• Work on the Things you Know How to Do
– The unknown will become “obvious” as you make progress.
• Optimization Criteria: • Delay [Logic levels, Fan in/out], • Area [Gate count, Package count, Pin out]• Cost, Power, Design time
CS141-L3-10 Tarun Soni, Summer ‘03
The 32 bit ALU-limited edition
Seta31
0
Result0a0
Result1a1
0
Result2a2
0
Operation
b31
b0
b1
b2
Result31
Overflow
Bnegate
Zero
ALU0Less
CarryIn
CarryOut
ALU1Less
CarryIn
CarryOut
ALU2Less
CarryIn
CarryOut
ALU31Less
CarryIn
• Supported Operations000 = and001 = or010 = add110 = subtract111 = slt
• Tuned performance by using Carry-lookahead adders.
• What about other instructions ?
• multiply mult $2,$3 Hi, Lo = $2 x $3 64-bit signed product• multiply unsigned multu$2,$3 Hi, Lo = $2 x $3 64-bit unsigned product• divide div $2,$3 Lo = $2 ÷ $3, Lo = quotient, Hi = remainder • Hi = $2 mod $3 • divide unsigned divu $2,$3 Lo = $2 ÷ $3, Unsigned quotient &
remainder
CS141-L3-11 Tarun Soni, Summer ‘03
Grade school
• Paper and pencil example:
Multiplicand 1000Multiplier x 1001
1000 0000 0000 1000
Product 1001000• m bits x n bits = m+n bit product• Binary makes it easy:
– 0 => place 0 ( 0 x multiplicand)– 1 => place multiplicand ( 1 x multiplicand)
• we’ll look at a couple of versions of multiplication hardware
CS141-L3-12 Tarun Soni, Summer ‘03
Unsigned basic multiplier
B0
A0A1A2A3
A0A1A2A3
A0A1A2A3
A0A1A2A3
B1
B2
B3
P0P1P2P3P4P5P6P7
0 0 0 0
• Stage i accumulates A * 2 i if Bi == 1
CS141-L3-13 Tarun Soni, Summer ‘03
Unsigned basic multiplier
• at each stage shift A left ( x 2)
• use next bit of B to determine whether to add in shifted multiplicand
• accumulate 2n bit partial product at each stage
B0
A0A1A2A3
A0A1A2A3
A0A1A2A3
A0A1A2A3
B1
B2
B3
P0P1P2P3P4P5P6P7
0 0 0 00 0 0
CS141-L3-14 Tarun Soni, Summer ‘03
Unsigned basic multiplier
Done
1. TestMultiplier0
1a. Add multiplicand to product andplace the result in Product register
2. Shift the Multiplicand register left 1 bit
3. Shift the Multiplier register right 1 bit
32nd repetition?
Start
Multiplier0 = 0Multiplier0 = 1
No: < 32 repetitions
Yes: 32 repetitions
for(i=0; i<32; i++)
{
If ( mulitplier[0] == 1 )
// we could do multiplier[i] and skip the shift
{
product += multiplicand ;
// product is 64 bit register
// adder is 64 bit. !
}
multiplicand << 1;
// shift multiplicand to prepare for next add
// multiplicand is in a 64 bit register
mulitplier >> 1;
// position the i’th bit on lsb for test.
}
The algorithm
CS141-L3-15 Tarun Soni, Summer ‘03
Unsigned basic multiplier
• 64-bit Multiplicand reg, 64-bit ALU, 64-bit Product reg, 32-bit multiplier reg
Multiplier = datapath + control
Product
Multiplier
Multiplicand
64-bit ALU
Shift Left
Shift Right
WriteControl
32 bits
64 bits
64 bits
• Product Multiplier Multiplicand 0000 0000 0011 0000 0010
• 0000 0010 0001 0000 0100• 0000 0110 0000 0000 1000• 0000 0110
CS141-L3-16 Tarun Soni, Summer ‘03
Some observations
• 1 clock per cycle => 100 clocks per multiply– Ratio of multiply to add 5:1 to 100:1
• 1/2 the bits in multiplicand always 0=> 64-bit adder is wasted
• 0’s inserted in left of multiplicand as shifted=> least significant bits of product never changed once formed
• Instead of shifting multiplicand to left, shift product to right?
• Speed ? • Power/efficiency of the adder ? • Pattern of result on product register ?
CS141-L3-17 Tarun Soni, Summer ‘03
Multiplier 2.0
• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, 32-bit Multiplier reg
Product
Multiplier
Multiplicand
32-bit ALU
Shift Right
WriteControl
32 bits
32 bits
64 bits
Shift Right
CS141-L3-18 Tarun Soni, Summer ‘03
Multiplier 2.0
3. Shift the Multiplier register right 1 bit.
Done
Yes: 32 repetitions
2. Shift the Product register right 1 bit.
No: < 32 repetitions
1.TestMultiplier0
Multiplier0 = 0Multiplier0 = 1
1a. Add multiplicand to the left half of product & place the result in the left half of Product register
32nd repetition?
Start
for(i=0; i<32; i++)
{
If ( mulitplier[0] == 1 )
{
product[31:16] += multiplicand ;
// product is 64 bit register
// adder is 32 bit. !
}
product >> 1;
// shift product right
// saving product[i:0] for final result
mulitplier >> 1;
// position the i’th bit on lsb for test.
}
CS141-L3-19 Tarun Soni, Summer ‘03
Multiplier 2.0
Product
Multiplier
Multiplicand
32-bit ALU
Shift Right
Write
Control
32 bits
32 bits
64 bits
Shift Right
• Product Multiplier Multiplicand NextProduct• 0000 0000 0011 0010 0000+0010 = 0010 0000• 0001 0000 0001 0010 0001+0010 = 0011 0000• 0001 1000 0000 0010 0001+0000 = 0001 1000• 0000 1100 0000 0010 0000+0000 = 0000 1100• 0000 0110
CS141-L3-20 Tarun Soni, Summer ‘03
Multiplier 3.0
• Product register wastes space that exactly matches size of multiplier=> combine Multiplier register and Product register
• 32-bit Multiplicand reg, 32 -bit ALU, 64-bit Product reg, (0-bit Multiplier reg)
Product (Multiplier)
Multiplicand
32-bit ALU
WriteControl
32 bits
64 bits
Shift Right
CS141-L3-21 Tarun Soni, Summer ‘03
Multiplier 3.0
Done
Yes: 32 repetitions
2. Shift the Product register right 1 bit.
No: < 32 repetitions
1. TestProduct0
Product0 = 0Product0 = 1
1a. Add multiplicand to the left half of product & place the result in the left half of Product register
32nd repetition?
Start
for(i=0; i<32; i++)
{
If ( product[0] == 1 )
{
product[31:16] += multiplicand ;
// product is 64 bit register
// adder is 32 bit. !
}
product >> 1;
// shift product right
// saving product[i:0] for final result
}
CS141-L3-22 Tarun Soni, Summer ‘03
More observations ?
• 2 steps per bit because Multiplier & Product combined• MIPS registers Hi and Lo are left and right half of Product• Gives us MIPS instruction MultU• How can you make it faster?• What about signed multiplication?
– easiest solution is to make both positive & remember whether tocomplement product when done (leave out the sign bit, run for 31 steps)
– apply definition of 2’s complement • need to sign-extend partial products and subtract at the end
– Booth’s Algorithm is elegant way to multiply signed numbers using same hardware as before and save cycles
• can handle multiple bits at a time
CS141-L3-23 Tarun Soni, Summer ‘03
Booths algorithm
• Example 2 x 6 = 0010 x 0110: 0010
x 0110 + 0000 shift (0 in multiplier) + 0010 add (1 in multiplier) + 0100 add (1 in multiplier) + 0000 shift (0 in multiplier) 00001100
• ALU with add or subtract gets same result in more than one way: 6 = – 2 + 8
0110 = – 00010 + 01000 = 11110 + 01000• For example• 0010
x 0110 0000 shift (0 in
multiplier) – 0010 sub (first 1 in multpl.) . 0000 shift (mid string of 1s) . + 0010 add (prior step had last 1) 00001100
CS141-L3-24 Tarun Soni, Summer ‘03
Booths algorithm
Current Bit Bit to the Right Explanation Example Op
1 0 Begins run of 1s 0001111000 sub
1 1 Middle of run of 1s 0001111000 none
0 1 End of run of 1s 0001111000 add
0 0 Middle of run of 0s 0001111000 none
Originally for Speed (when shift was faster than add)
• Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one
0 1 1 1 1 0beginning of runend of run
middle of run
–1+ 10000
01111
CS141-L3-25 Tarun Soni, Summer ‘03
Booths algorithm
Booths Example (2 x 7)
1a. P = P - m 1110 + 11101110 0111 0 shift P (sign ext)
1b. 0010 1111 0011 1 11 -> nop, shift
2. 0010 1111 1001 1 11 -> nop, shift
3. 0010 1111 1100 1 01 -> add
4a. 0010 + 0010 0001 1100 1 shift
4b. 0010 0000 1110 0 done
Operation Multiplicand Product next?
0. initial value 0010 0000 0111 0 10 -> sub
CS141-L3-26 Tarun Soni, Summer ‘03
Booths algorithm
Booths Example (2 x -3)
1a. P = P - m 1110 + 11101110 1101 0 shift P (sign ext)
1b. 0010 1111 0110 1 01 -> add + 0010
2a. 0001 0110 1 shift P
2b. 0010 0000 1011 0 10 -> sub + 1110
3a. 0010 1110 1011 0 shift
3b. 0010 1111 0101 1 11 -> nop4a 1111 0101 1 shift
4b. 0010 1111 1010 1 done
Operation Multiplicand Product next?
0. initial value 0010 0000 1101 0 10 -> sub
CS141-L3-27 Tarun Soni, Summer ‘03
Division
1001 Quotient
Divisor 1000 1001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result)
See how big a number can be subtracted, creating quotient bit on each step
Binary => 1 * divisor or 0 * divisor
Dividend = Quotient x Divisor + Remainder=> sizeof( Dividend ) = sizeof( Quotient ) + sizeof( Divisor )
3 versions of divide, successive refinement
CS141-L3-28 Tarun Soni, Summer ‘03
Division 1.0
• 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Remainder
Quotient
Divisor
64-bit ALU
Shift Right
Shift Left
WriteControl
32 bits
64 bits
64 bits
CS141-L3-29 Tarun Soni, Summer ‘03
Division 1.0
1. Subtract the Divisor register from the Remainder register, and place the result in the
Remainder register.
Test RemainderRemainder < 0Remainder >= 0
2a. Shift the Quotient register to the left setting the new rightmost bit to 1.
2b. Restore the original value by adding the Divisor register to the Remainder register, and place the sum in the Remainder register. Also
shift the Quotient register to the left, setting the new least significant bit to 0.
3. Shift the Divisor register right 1 bit.
33rd repetition?No: < 33 repetitions
Done
Yes: 33 repetitions
Start
• Takes n+1 steps for n-bit Quotient & Rem.
Quotient Divisor Remainder0000 0010 0000 0000 0111
CS141-L3-30 Tarun Soni, Summer ‘03
Division 2.0
• 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of divisor is wasted
• Instead of shifting divisor to right, shift remainder to left?
• 1st step cannot produce a 1 in quotient bit (otherwise too big) => switch order to shift first and then subtract, can save 1 iteration
• 32-bit Divisor reg, 32-bit ALU, 64-bit Remainder reg, 32-bit Quotient reg
Remainder
Quotient
Divisor
32-bit ALU
Shift Left
WriteControl
32 bits
32 bits
64 bits
Shift Left
CS141-L3-31 Tarun Soni, Summer ‘03
Division 2.0
3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Quotient register to the left, setting the new least significant bit to 0.
Test Remainder
Remainder < 0Remainder >= 0
2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.
3a. Shift the Quotient register to the left setting the new rightmost bit to 1.
1. Shift the Remainder register left 1 bit.
Done
Yes: n repetitions
nthrepetition?
No: < n repetitions
Start: Place Dividend in Remainder
CS141-L3-32 Tarun Soni, Summer ‘03
Division 3.0
• Eliminate Quotient register by combining with Remainder as shifted left– Start by shifting the Remainder left as before. – Thereafter loop contains only two steps because the shifting of the Remainder
register shifts both the remainder in the left half and the quotient in the right half – The consequence of combining the two registers together and the new order of
the operations in the loop is that the remainder will shifted left one time too many.– Thus the final correction step must shift back only the remainder in the left half of
the register
• 32-bit Divisor reg, 32 -bit ALU, 64-bit Remainder reg, (0-bit Quotient reg)
Remainder (Quotient)
Divisor
32-bit ALU
WriteControl
32 bits
64 bits
Shift Left“HI” “LO”
CS141-L3-33 Tarun Soni, Summer ‘03
Division 3.0
Remainder Divisor0000 0111 0010
3b. Restore the original value by adding the Divisor register to the left half of the Remainderregister, &place the sum in the left half of the Remainder register. Also shift the Remainder register to the left, setting the new least significant bit to 0.
Test Remainder
Remainder < 0Remainder 0
2. Subtract the Divisor register from the left half of the Remainder register, & place the result in the left half of the Remainder register.
3a. Shift the Remainder register to the left setting the new rightmost bit to 1.
1. Shift the Remainder register left 1 bit.
Done. Shift left half of Remainder right 1 bit.
Yes: n repetitions (n = 4 here)
nthrepetition?
No: < n repetitions
Start: Place Dividend in Remainder
CS141-L3-34 Tarun Soni, Summer ‘03
Sign of remainder = ?
•7/4 = (Q=1, R=3) •7/4 = (Q=2, R=-1)
Which do you prefer?
Convention:
•a/b = (Q , R) •Sign(R) <= Sign(a)
Thus•7/4 = (Q=1, R=3) •-7/4 = (Q=-1,R=-3)
Division: some signed details
-a
0
a
Q*b + R
+ Q*bR
a =Q*b + R
CS141-L3-35 Tarun Soni, Summer ‘03
Floating Point
• What can be represented in N bits?
• Unsigned 0 to 2
• 2s Complement - 2 to 2 - 1
• 1s Complement -2 +1 to 2 -1
• But, what about?
– very large numbers? 9,349,398,989,787,762,244,859,087,678
– very small number? 0.0000000000000000000000045691
– rationals 2/3
– irrationals 2
– transcendentals e
NN-1 N-1
N-1 N-1
CS141-L3-36 Tarun Soni, Summer ‘03
Floating Point
6.02 x 10 1.673 x 1023 -24
exponent
radix (base)Mantissa
decimal point
IEEE F.P. ± 1.M x 2e - 127
Issues:
° Arithmetic (+, -, *, / )
° Representation, Normal form
° Range and Precision
° Rounding
° Exceptions (e.g., divide by zero, overflow, underflow)
° Errors
° Properties ( negation, inversion, if A ° B then A - B ° 0 )
CS141-L3-37 Tarun Soni, Summer ‘03
Floating Point
Binary Fractions
10112 = 1x23 + 0x22 + 1x21 + 1x20
so...
101.0112 = 1x22 + 0x21 + 1x20 + 0x2-1 + 1x2-2 + 1x2-3
e.g.,
.75 = 3/4 = 3/22 = 1/2 + 1/4 = .11
CS141-L3-38 Tarun Soni, Summer ‘03
Floating PointRepresentation of floating point numbers in IEEE 754 standard:
single precision1 8 23
sign
exponent:excess 127binary integer
mantissa:sign + magnitude, normalizedbinary significand w/ hiddeninteger bit: 1.Mactual exponent is
e = E - 127
S E M
N = (-1) 2 (1.M)S E-127
0 < E < 255
0 = 0 00000000 0 . . . 0 -1.5 = 1 01111111 10 . . . 0
Magnitude of numbers that can be represented is in the range:
2-126
(1.0) to 2127
(2 - 223 )
which is approximately:
1.8 x 10-38
to 3.40 x 10 38 integer comparison valid
on IEEE Fl.Pt. numbers of same sign!
CS141-L3-39 Tarun Soni, Summer ‘03
Floating Point
• Leading “1” bit of significand is implicit
• Exponent is “biased” to make sorting easier– all 0s is smallest exponent all 1s is largest– bias of 127 for single precision and 1023 for double precision– summary: (–1)sign ´ (1+significand) ´ 2exponent – bias
• Example:
– decimal: -.75 = -3/4 = -3/22
– binary: -.11 = -1.1 x 2-1
– floating point: exponent = 126 = 01111110
– IEEE single precision: 10111111010000000000000000000000
SignExponent
Significand
CS141-L3-40 Tarun Soni, Summer ‘03
Floating Point
Floating Point Addition
• How do you add in scientific notation?
9.962 x 104 + 5.231 x 102
• Basic Algorithm
1. Align
2. Add
3. Normalize
4. Round
Approximate algorithm.While (Exp(A) > Exp(B) ) {
shift Mantissa(B) right; Exp(B)++;
}Mantissa(Result) = Mantissa(A) +
Mantissa(B);Exp(Result) = Exp(A); // or Exp(B)While (Mantissa(Result)[msb] !
=1!) {
Exp(Result)--;}Round(Mantissa); Round(Exponent);
CS141-L3-41 Tarun Soni, Summer ‘03
Floating Point
0 10 1 0 1
Control
Small ALU
Big ALU
Sign Exponent Significand Sign Exponent Significand
Exponentdifference
Shift right
Shift left or right
Rounding hardware
Sign Exponent Significand
Increment ordecrement
0 10 1
Shift smallernumber right
Compareexponents
Add
Normalize
Round
CS141-L3-42 Tarun Soni, Summer ‘03
Floating Point Addition
2. Multiply the significands
4. Round the significand to the appropriatenumber of bits
Still normalized?
Start
Yes
No
No
YesOverflow orunderflow?
Exception
3. Normalize the product if necessary, shiftingit right and incrementing the exponent
1. Add the biased exponents of the twonumbers, subtracting the bias from the sum
to get the new biased exponent
Done
5. Set the sign of the product to positive if thesigns of the original operands are the same;
if they differ make the sign negative
CS141-L3-43 Tarun Soni, Summer ‘03
Floating Point
Floating Point Multiplication
• How do you multiply in scientific notation?
(9.9 x 104)(5.2 x 102) = 5.148 x 107
• Basic Algorithm
1. Add exponents
1a. Correct for bias in exponent representation (Exp -= 127);
2. Multiply
3. Normalize
4. Round
5. Set Sign
CS141-L3-44 Tarun Soni, Summer ‘03
Floating Point Accuracy Issues
FP Accuracy
• Extremely important in scientific calculations• Very tiny errors can accumulate over time• IEEE 754 FP standard has four rounding modes
– always round up– always round down– truncate– round to nearest
=> in case of tie, round to nearest even• Requires extra bits in intermediate representations
CS141-L3-45 Tarun Soni, Summer ‘03
Floating Point Accuracy Issues
• Guard bits -- bits to the right of the least significant bit of the significand computed for use in normalization (could become significant at that point) and rounding.
• IEEE 754 has three extra bits and calls them guard, round, and sticky.
How many extra bits?
IEEE Spec: As if computed the result exactly and rounded.
CS141-L3-46 Tarun Soni, Summer ‘03
Floating Point Overflows
Infinity and NaNs
result of operation overflows, i.e., is larger than the largest number that can be represented
overflow is not the same as divide by zero (raises a different exception)
+/- infinity S 1 . . . 1 0 . . . 0
It may make sense to do further computations with infinity e.g., X/0 > Y may be a valid comparison
Not a number, but not infinity (e.q. sqrt(-4)) invalid operation exception (unless operation is = or =)
NaN S 1 . . . 1 non-zero
NaNs propagate: f(NaN) = NaN
HW decides what goes here
CS141-L3-47 Tarun Soni, Summer ‘03
• Multiplication and division take much longer than addition, requiring multiple addition steps.
• Floating Point extends the range of numbers that can be represented, at the expense of precision (accuracy).
• FP operations are very similar to integer, but with pre- and post-processing.
• Rounding implementation is critical to accuracy over time.
Summary