cs137: electronic design automation
DESCRIPTION
CS137: Electronic Design Automation. Day 1: September 26, 2005 Introduction. Apple Pie Intro (1). How do we design modern computational systems? Millions billions of devices used in everything billion dollar businesses rapidly advancing technology more “effects” to address - PowerPoint PPT PresentationTRANSCRIPT
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CALTECH CS137 Fall2005 -- DeHon
CS137:Electronic Design Automation
Day 1: September 26, 2005
Introduction
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CALTECH CS137 Fall2005 -- DeHon
Apple Pie Intro (1)
• How do we design modern computational systems?– Millionsbillions of devices– used in everything– billion dollar businesses– rapidly advancing technology– more “effects” to address– rapidly developing applications and uses
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CALTECH CS137 Fall2005 -- DeHon
Apple Pie Intro (2)
• Options:– human handles all the details– human solves problem, machine checks – human defines something about the
solution and machine fills in the details
• Remember:– millions of devices, changing world, TTM
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CALTECH CS137 Fall2005 -- DeHon
Apple Pie Intro (3)
• Human brain power is the bottleneck– to producing new designs– to creating new things
• (applications of technology)
– (to making money)
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CALTECH CS137 Fall2005 -- DeHon
Apple Pie Intro (4)
• How do we unburden the human?– Take details away from him
• raise the level of abstraction at which he specifies computation
– Pick up the slack• machine take over the details
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CALTECH CS137 Fall2005 -- DeHon
Central Questions
• How do we make the machine fill in the details (elaborate the design)?
• How well can we make it solve this problem?
• How fast can it solve this problem?
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CALTECH CS137 Fall2005 -- DeHon
Outline
• Apple Pie Intro (done)
• Instructor
• The Problem
• Decomposition
• Costs
• Not Solved
• This Class
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CALTECH CS137 Fall2005 -- DeHon
Instructor
• VLSI/CAD user– Architect, Computer Designer
• Avoid tedium
• Analyze Architectures– necessary to explore– costs different
• Requirements of Computation
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CALTECH CS137 Fall2005 -- DeHon
Problem
• Map from a problem specification down to an efficient implementation on a particular computational substrate.
• What’s– a specification– a substrate– have to do during mapping
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CALTECH CS137 Fall2005 -- DeHon
Problem: Specification
• Recall: basic tenant of CS theory – we can specify computations precisely– Universal languages/building blocks exist
• Turing machines• nand gates
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CALTECH CS137 Fall2005 -- DeHon
Specifications
• netlist• logic gates• FSM• programming
language– C, C++, Lisp, Java
block diagram
• RTL– Register Transfer
Level– (e.g. subsets of
Verilog, VHDL)
• behavioral• dataflow graph• layout• SPICE netlist
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CALTECH CS137 Fall2005 -- DeHon
Substrate
• “full” custom VLSI• Standard cell• metal-only gate-array• FPGA• Processor (scalar, VLIW, Vector, MIMD)• billiard balls• Nanowire PLA• molecules• DNA
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CALTECH CS137 Fall2005 -- DeHon
Full Custom
• Get to define all layers
• Use any geometry you like
• Only rules are process design rules
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CALTECH CS137 Fall2005 -- DeHon
FPGA
K-LUT (typical k=4) Compute block w/ optional output Flip-Flop
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CALTECH CS137 Fall2005 -- DeHon
Standard Cell Area
inv nand3 AOI4inv nor3 Inv
All cellsuniformheight
Width ofchanneldeterminedby routing
Cell area Width of channelfairly constant?
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CALTECH CS137 Fall2005 -- DeHon
Nanowire PLA
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CALTECH CS137 Fall2005 -- DeHon
What are we throwing away?(what does mapping have to
recover?)
• layout• TR level circuits• logic gates / netlist• FSM
• RTL• behavioral• programming
language– C, C++, Lisp, Java
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CALTECH CS137 Fall2005 -- DeHon
Specification not Optimal
• Y = a*b*c + a*b*/c + /a*b*c
• Multiple representations with the same semantics (computational meaning)
• Only have to implement the semantics, not the “unimportant” detail
• Exploit to make smaller/faster/cooler
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CALTECH CS137 Fall2005 -- DeHon
Problem Revisited
• Map from some “higher” level down to substrate
• Fill in details:– device sizing, placement, wiring, circuits,
gate or functional-unit mapping, timing, encoding, data movement, scheduling, resource sharing
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CALTECH CS137 Fall2005 -- DeHon
DOMAIN SPECIFIC
RTL
GATE
TRANSISTOR
BEHAVIORAL
Design Productivity by Approach
a
b
s
q0
1
d
clk
GATES/WEEK(Dataquest)
100 - 200
1K - 2K
2K - 10K
8K - 12K
10 - 20
Source: Keutzer (UCB EE 244)
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CALTECH CS137 Fall2005 -- DeHon
To Design, Implement, Verify 10M transistors
a
b
s
q0
1
d
clk
62.5
125
625
6250
62,500
Power
Delay
Area
Beh
RTL
Implementations here are often not good enough
Because implementationshere are inferior/ unpredictable
Staff Months
Source: Keutzer (UCB EE 244)
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CALTECH CS137 Fall2005 -- DeHon
The Productivity Gap
Source: Newton (UCB/GSRC)
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CALTECH CS137 Fall2005 -- DeHon
Source: Payne (CTO Philips Semi) 2004
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CALTECH CS137 Fall2005 -- DeHon
Decomposition
• Conventionally, decompose into phases:– scheduling, assignment -> RTL– retiming, sequential opt. -> logic equations– logic opt., covering -> gates– placement-> placed gates– routing->mapped design
• Good abstraction, manage complexity
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CALTECH CS137 Fall2005 -- DeHon
Decomposition (easy?)
• All steps are (in general) NP-hard.– routing– placement– partitioning– covering– logic optimization– scheduling
• What do we do about NP-hard problems?– Return to this problem in a few slides…
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CALTECH CS137 Fall2005 -- DeHon
Decomposition
+Easier to solve – only worry about one problem at a time
+Less computational work– smaller problem size
- Abstraction hides important objectives– solving 2 problems optimally in sequence
often not give optimal result of simultaneous solution
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CALTECH CS137 Fall2005 -- DeHon
Mapping and Decomposition
• Two important things to get back to– disentangling problems– coping with NP-hardness
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CALTECH CS137 Fall2005 -- DeHon
Costs
• Once get (preserve) semantics, trying to minimize the cost of the implementation.– Otherwise this would be trivial – (none of the problems would be NP-hard)
• What costs?• Typically: EDA [:-)]
– Energy– Delay– Area
• Future: add yield (robustness to defects/faults)
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CALTECH CS137 Fall2005 -- DeHon
Costs
• Different cost critera (e.g. E,D,A) – behave differently under transformations– lead to tradeoffs among them
• [LUT cover example next slide]
– even have different optimality/hardness• e.g. optimally solve delay covering in poly time,
but not area mapping– (dig into on Wednesday)
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CALTECH CS137 Fall2005 -- DeHon
Costs: Area vs. Delay
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CALTECH CS137 Fall2005 -- DeHon
Costs
• Cannot, generally, solve a problem independent of costs– costs define what is “optimal”– e.g.
• (A+B)+C vs. A+(B+C)• [cost=pob. Gate output is high]• A,B,C independent• P(A)=P(B)=0.5, P(C)=0.01• P(A)=0.1, P(B)=P(C)=0.5
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CALTECH CS137 Fall2005 -- DeHon
Costs may also simplify problem
• Often one cost dominates– Allow/supports decomposition– Solve dominant problem/effect first (optimally)– Cost of other affects negligible
• total solution can’t be far from optimal
– e.g.• Delay (area) in gates, delay (area) in wires
– Require: formulate problem around relative costs
• Simplify problem at cost of generality
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CALTECH CS137 Fall2005 -- DeHon
Coping with NP-hard Problems
• simpler sub-problem based on dominate cost or special problem structure
• problems exhibit structure– optimal solutions found in reasonable time in
practice
• approximation algorithms– Can get within some bound of optimum
• heuristic solutions• high density of good/reasonable solutions?
– Try many … filter for good ones
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CALTECH CS137 Fall2005 -- DeHon
Not a solved problem
• NP-hard problems– almost always solved in suboptimal manner– or for particular special cases
• decomposed in suboptimal ways• quality of solution changes as dominant costs
change – …and relative costs are changing!
• new effects and mapping problems crop up with new architectures, substrates
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CALTECH CS137 Fall2005 -- DeHon
Big Challenge
• Rich, challenging, exciting space
• Great value– practical– theoretical
• Worth vigorous study– fundamental/academic– pragmatic/commercial
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CALTECH CS137 Fall2005 -- DeHon
This Class
• Toolkit of techniques at our disposal
• Common decomposition and subproblems
• Big ideas that give us leverage
• Formulating problems and analyze success
• Cost formulation
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CALTECH CS137 Fall2005 -- DeHon
This Class: Toolkit
• Dynamic Programming• Linear Programming (LP, ILP)• Graph Algorithms• Greedy Algorithms• Randomization• Search• Heuristics• Approximation Algorithms
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CALTECH CS137 Fall2005 -- DeHon
This Class: Decomposition
• Scheduling
• Logic Optimization
• Covering/gate-mapping
• Partitioning
• Placement
• Routing Select composition
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CALTECH CS137 Fall2005 -- DeHon
Student Requirements
• Reading • Class• Mini-Project
– month long, applying ideas from class– [ask about computers, access]
• Homework(2)/Exam• Essentially something due every 2 weeks• Spring Term: major, student-selected project
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CALTECH CS137 Fall2005 -- DeHon
Graduate Class
• Assume you are here to learn– Motivated– Mature– Not just doing minimal to get by and get a
grade
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CALTECH CS137 Fall2005 -- DeHon
Materials
• Reading– Handout or online– If online, linked to reading page on web;
I assume you will download/print/read.
• Lecture slides (after today)– I’ll try to link to web page by 10am (maybe
9am?); you can print
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CALTECH CS137 Fall2005 -- DeHon
Misc.
• Feedback sheets
• Web page
• Syllabus
• Reading
• Assignment 1
• Mini-Project
• [make sure get names/emails]
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CALTECH CS137 Fall2005 -- DeHon
Class Location
• Here
OR
• IC Lab, Jorgensen 84 ?
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CALTECH CS137 Fall2005 -- DeHon
Questions?
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CALTECH CS137 Fall2005 -- DeHon
Today’s Big Ideas• Human time limiter• Leverage: raise abstraction+fill in details• Problems complex (human, machine)• Decomposition necessary evil (?)• Implement semantics
– but may transform to reduce costs
• Dominating effects• Problem structure• Optimal solution depend on cost
(objective)