cs eee f241 microprocessor architecture jan 19th 2016

ELECTRICAL ELECTRONICS COMMUNICATION INSTRUMENTATION

8086 Microprocessor & its

Architecture

Topic-II

T1. Barry B Brey, The Intel Microprocessors .Pearson, Eight Ed. 2009. Chapter 2

R1. Douglas V Hall, Microprocessor and Interfacing, TMH, Second Edition. Chapter 2

Jan 21st 23rd 2016


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EVOLUTION OF MICROPROCESSOR


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16 bit Microprocessor


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32 bit Microprocessor


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Variations of 8086 - 8088


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Characteristics of the X86 family

CISC Instructions broken up into micro operations Complex instruction decoder


Binary data are stored as a byte (8 bits), word (16 bits),

or double word (32 bits) in a computer system.

These data may be unsigned or signed.

Signed negative data are always stored in the two's

complement form.

Data that are wider than 8 bits are always stored using

the little endian format.

The assembler directives DB or BYTE define bytes,

DW or WORD define words, DD or DWORD define

doublewords, and DQ or QWORD define quadwords.

Little Endian format


Little Endian & Big Endian

A word (16-bits) is formed with two bytes of data. The least significant byte always stored in the lowest-

numbered memory location.

Most significant byte is stored in the highest. This method of storing a number is called the little

endian format.

Alternate method is called the big endian format. Numbers are stored with the lowest location containing

the most significant data.

Not used with Intel microprocessors. The big endian format is used with the Motorola family

of microprocessors.


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8086 Microprocessor


Bus Interface Unit (BIU)

handles all transfers of data and addresses on the buses for the execution unit

Execution Unit (EU)

Actual function is performed here - instructs BIU from where to fetch an instruction

- decodes it,

- executes it


3-11

EU Operation

ALU Data bus

(16 bits)

AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

General purpose

register

ALU

Flag register

EU

control instruction

1011000101001010

1. Fetch an instruction from instruction

queue

2. According to the instruction, EU control

logic generates control signals.

(This process is also referred to as instruction

decoding)

3. Depending on the control signal,

EU performs one of the following

operations:

An arithmetic operation

A logic operation

Storing a data into a register

Moving a data from a register

Changing flag register


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8086 Microprocessor


3-13

Block diagram of 8086

AH AL

BH BL

CH CL

DH DL

SP

BP

SI

DI

ALU

Flag register

Execution Unit

(EU)

EU

control

CS

DS

SS

ES ALU Data bus

(16 bits)

Address bus (20 bits)

Instruction Queue

Bus

control External bus

IP

Data bus

(16 bits)

Bus Interface Unit (BIU)

General purpose

register

Segment

register


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X86 -ISA

Register Organisation


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8086 Register organization

General purpose Registers. - AX, BX, CX, DX

Segment Registers. - CS, DS, SS, ES

Pointer and Index Registers. - IP, BP, SP

-SI, DI

Flag Registers -FLAGS


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Multipurpose Registers. - AX, BX, CX, DX, BP, DI, SI

Special Purpose Registers. - IP, SP, FLAGS

Segment Registers. - CS, DS, SS, ES

Function wise 8086 Register

organization


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8086 Register organization

IP : INSTRUCTION POINTER


3-18

General Purpose Registers


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General Purpose Registers

BX : offset storage for

forming physical address

CX : default counter in case

of string and loop

instructions


3-20

SP

BP

SI

DI

Pointer and

Index Group

Stack Pointer

Base Pointer

Source Index

Destination Index

IP : INSTRUCTION POINTER

Pointer and Index Registers


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Pointer and Index Registers

Pointer (IP, BP, SP) : contain offset within a particular

segment for forming physical address.

IP contain offset within Code segment.

BP and SP contain offset with Stack segment.

Index (SI, DI) : used as general purpose as well as contain

offset with Data and Extra segment respectively.

Index registers are useful for string manipulation.


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Flag Register

FLAGS - Status Flag - Control Flag

FLAG Register


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16 bit Flag Register in 8086

OF DF IF TF ZF SF AF PF CF

0 15

Control Flags Status Flags

IF: Interrupt enable flag

DF: Direction flag

TF: Trap flag

CF: Carry flag

PF: Parity flag

AF: Auxiliary carry flag

ZF: Zero flag

SF: Sign flag

OF: Overflow flag

Flag register contains information reflecting the current status of a

microprocessor. It also contains information which controls the

operation of the microprocessor.


3-24

Flags

Conditional/ status Flags: They are set/reset by the processor to indicate

certain condition that arises during the execution of a program. (the lower

byte of 16 bit along with overflow flag.)

- Reflects the result of operation performed by CPU.

Control Flags: they are deliberately set/reset by the programmer to control

certain operations of the processor. (higher byte of excluding overflow)


3-25

Status Flags

Carry - unsigned arithmetic out of range (set or C=1)

Parity - no. of 1 s is an even number (set or P=1)

Auxiliary Carry - carry from bit D3 to D4. (set or AC=1)

Zero - result is zero (set or Z=1)

Sign - result is negative for signed computation. (set or S=1)

Overflow - signed arithmetic out of range (set or O =1)


3-26

Status Flags


3-27

Control Flags

IF: Interrupt enable flag (If IF is set, IF=1 CPU will

serve the interrupts from external device)

DF: Direction flag used for string manipulation of

instructions. (If DF is set, DF=1, string will process

from highest towards lowest address) (opposite of little

endian format)

TF: Trap flag (If TF is set, TF =1, processors enter

into single step execution ) This flag normally is used

for debugging of program.


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Segment Registers


Microprocessor System Design 3-29

Segment Registers:

Segment register stores upper 16 bits of its starting address. (base address)

code segment registers - holds base address from where instructions are coming (base address of memory location in code segment)

stack segment registers - stores base address of stack while a subprogram is executed. (base address of memory location in stack segment)

data segment registers - holds base address of memory location where data stored (base address of memory location in data segment)

extra segment registers - holds base address of memory location if extra data required (another data segment)


Microprocessor System Design 3-30

Stack Segment

The CPU use the stack for temporarily storing important data. For example the content of register that will be require at later stage.

The stack grows down i.e. the data is pushed onto the stack memory locations with decreasing address.

When the data is required by CPU in later stage they will be popped off from the stack.


The total addressable memory size is 1Mega Byte memory.

The complete 1MB memory is divided into 16 logical segments and each segment contains 64Kbytes of memory.

While addressing any location in the memory bank the physical address is calculated from two parts ; the first is segment address

and the second is offset address.

Physical address calculation


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8086 Memory Address Space


The segment register contains the 16 bit segment base address related to different segment.

Any of the pointer or index registers or BX may contains the offset of the location of the address.



Advantage of this is : instead of maintaining 20 bit register for a physical address the processor will maintain two 16 bit registers

which are within the word length capacity of machine.

All segments are like logical segments

They may or may not be physically separated .



At any given time the 8086 works with only four 64 KB segments within this 1MB range.

A 64 KB segment can be located anywhere within the 1 MB space, but the address will always start at an address with zeros in

the lowest 4 bits.



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8086 Memory Address Space


This constraint was put on the location of segments so that it is only necessary to store and manipulate 16- bit data .

The part of the segment starting address that is stored in segment registers is known as segment base address.



3-38

Programmers model of 8086


3-39

Segmentation

Physical memory address pointed by

segment (range: 0000H to F000H) and offset (range: 0000H to FFFFH) pair is calculated as:

Physical address = ( * 16) +

= Segment address will shift left bitwise 4 times

+ offset address


3-40

Segmentation


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Default 16-bit segment and offset

address combinations SEGMENT OFFSET SPECIAL

PURPOSE

CS IP INSTRUCTION

ADDRESS

SS SP (or) BP STACK ADDRESS

DS BX, DI, SI,

an 8-bit number,

16 bit number

DATA ADDRESS

ES DI

for string Instructions

STRING

DESTINATION

ADDRESS


3-42

Segmentation in 8086

(Physical address calculation)


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Programmers Model


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Segmentation


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Physical Address


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Advantage of Segmentation

Allows the memory capacity to be 1MBytes although the actual addresses to be handled are of 16-bit size.

Allow the placing of code , data and stack portions of the same program in different parts (segments) of memory, for

data and code protection

Relocation: Permits a program and/or its data to be put into different areas of memory each time the program is

executed.

Program - Specify only offset


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Arithmetic Logic Unit (ALU)

n bits n bits

A B

Y

F

Carry

Y= 0 ?

A > B ?

F Y

0 0 0 A + B

0 0 1 A - B

0 1 0 A - 1

0 1 1 A and B

1 0 0 A or B

1 0 1 not A

Signal F control which function will be conducted by ALU.

Signal F is generated according to the current instruction.

Basic arithmetic operations: addition, subtraction,

Basic logic operations: and, or, xor, shifting,


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X86 -ISA

8086-80486 Programmers Model

BIU


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Memory Addressing

Real - Access only 1MB of memory - Only 20 Address lines required.

Protected

- support multitasking - memory management protection enabled


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Programmers Model BIU


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Programmers Model- MPR


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80X86 Summary

BIU (Bus Interface Unit) - provides hardware function for generation of the memory and I/O addresses for the transfer of data between itself and the

outside world.

EU (Execution Unit) - receives program instructions code and data from the BIU, executes these instructions and store the results in the general

purpose registers.

cs eee f241 microprocessor architecture jan 19th 2016

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