cs 838: netfpga tutorial theophilus benson. outline background: what is the netfpga? life cycle of a...
TRANSCRIPT
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CS 838: NetFPGA Tutorial
Theophilus Benson
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Outline
• Background: What is the NetFPGA?• Life cycle of a packet through a NetFPGA• Demo
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FPGA
Memory
1GE
1GE
1GE
1GE
What is the NetFPGA?
PCI
CPU Memory
NetworkingSoftwarerunning on a standard PC
A hardware acceleratorbuilt with Field Programmable Gate Arraydriving Gigabit network links
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NetFPGA RouterFunction
– 4 Gigabit Ethernet ports
Fully programmable– FPGA hardware
Open-source FPGA hardware -- – Verilog base design
Open-source Software -- Linux user Level – Drivers in C and C++
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NetFPGA Platform
Major Components– Interfaces
• 4 Gigabit Ethernet Ports• PCI Host Interface
– Memories• 36Mbits Static RAM• 512Mbits DDR2 Dynamic RAM
– FPGA Resources• Block RAMs• Configurable Logic Block (CLBs)• Memory Mapped Registers
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NetFGPA: Router Design
• Pipeline of modules– FIFO queues between each module
• Inter module communication– CTRL: Send on ctrl bus (8 bits)
• Metadata about the data being send
– DATA: Send on data bus (64 bits)– RDY: Signifies ready to receive packet (1 bit)– WR: Signifies packet being send(1bit)
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NetFPGA
FGPA Modules 1
Softw
areH
ardware
Linux user-levelprocesses
Verilog on NetFPGA PCI board
Linux Processes
FGPA Modules 2
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Example: An IP Router on NetFPGA
SwitchingForwardingTable
Routing Table
Routing Protocols
Management& CLI
Softw
areH
ardware
Linux user-levelprocesses
Verilog on NetFPGA PCI board
ExceptionProcessing
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port0 port2
192.168.102.y
192.168.101.x
Life of a Packet through the hardware
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Router StagesMACRxQ
CPURxQ
MACRxQ
CPURxQ
MACRxQ
CPURxQ
MACRxQ
CPURxQ
Input Arbiter
Output Port Lookup
MACTxQ
CPUTxQ
MACTxQ
CPUTxQ
MACTxQ
CPUTxQ
MACTxQ
CPUTxQ
Output Queues
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Inter-module CommunicationUsing “Module Headers”:
IP Hdr
Eth Hdr
…
0
0
0
Last word of packet0x10
Last Module Hdry
……
Module Hdrx Contain information such as packet length, input port, output port, …
Data Word(64 bits)
Ctrl Word(8 bits)
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Module i+1
data
Inter-module Communication
ctrl
wr
rdy
Module i
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MAC Rx Queue
MAC Rx Queue
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Rx Queue
Rx QueueIP Hdr:IP Dst: 192.168.2.3, TTL:
64, Csum:0x3ab4
Eth Hdr:Dst MAC = port 0,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
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Input Arbiter
Input Arbiter
Rx Q 0
Rx Q 1
…
Rx Q 7
Pkt
Pkt
Pkt
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Output Port Lookup
Output Port Lookup
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Output Port Lookup
IP Hdr:IP Dst: 192.168.2.3, TTL:
64, Csum:0x3ab4
IP Hdr:IP Dst: 192.168.2.3, TTL:
63, Csum:0x3ac2
Output Port Lookup
EthHdr: Dst MAC = 0Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 40x04
1- Check input port matches Dst
MAC
2- Check TTL, checksum
3- Lookup next hop IP & output
port (LPM)
4- Lookup next hop MAC
address (ARP)
5- Add output port module
6- Modify MAC Dst and Src addresses
7-Decrement TTL and update checksum
EthHdr: Dst MAC = nextHop Src MAC = port 4,
Ethertype = IP
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Output Queues
Output Queues
OQ0
OQ4
OQ7
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MAC Tx Queue
MAC Tx Queue
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MAC Tx Queue
MAC Tx Queue
IP Hdr:IP Dst: 192.168.2.3, TTL:
64, Csum:0x3ab4
IP Hdr:IP Dst: 192.168.2.3, TTL:
63, Csum:0x3ac2
EthHdr: Dst MAC = nextHop Src MAC = port 4,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 40x04
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NetFPGA-Host Interaction
• Linux driver interfaces with hardware– Packet interface via standard Linux network stack
– Register reads/writes via ioctl system call (with convenience wrapper functions)
• readReg(nf2device *dev, int address, unsigned *rd_data)• writeReg(nf2device *dev, int address, unsigned *wr_data)
eg:readReg(&nf2, OQ_NUM_PKTS_STORED_0, &val);
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NetFPGA-Host InteractionRegister access
PCI Bus
1. Software makes ioctl call on network socket. ioctl passed to driver.
2. Driver performs PCI memory read/write
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NetFPGA-Host Interaction
• Packet transfers shown using DMA interface
• Alternative: use programmed IO to transfer packets via register reads/writes– slower but eliminates the need to deal with
network sockets
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port0 port2192.168.2.y192.168.1.x
DEMO: Life of a Packet through the hardware
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• Programming the FPGA with your code– nf2_download NF2/bitfiles/reference_router.bit
• Mirror linux arp– ./NF2/projects/router_kit/sw/rkd
• Helpful tool– ./NFlib/C/router/cli– Shows forwarding tables {arp table, ip table}– Allows to modify tables
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Useful Links
• NetFPGA Website• NetFPGA Wiki• NetFPGA Guide• Walkthrough the Reference Designs • The Verilog Golden Reference Guide
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Questions
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Verilog
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Hardware Description Languages• Concurrent– By Default, Verilog statements
evaluated concurrently
• Express fine grain parallelism– Allows gate-level parallelism
• Provides Precise Description– Eliminates ambiguity about operation
• Synthesizable– Generates hardware from description
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Verilog Data Types
reg [7:0] A; // 8-bit register, MSB to LSB // (Preferred bit order for NetFPGA)
reg [0:15] B; // 16-bit register, LSB to MSB
B = {A[7:0],A[0:7]}; // Assignment of bits
reg [31:0] Mem [0:1023]; // 1K Word Memory
integer Count; // simple signed 32-bit integerinteger K[1:64]; // an array of 64 integerstime Start, Stop; // Two 64-bit time variables
From: CSCI 320 Computer ArchitectureHandbook on Verilog HDL, by Dr. Daniel C. Hyde :
http://eesun.free.fr/DOC/VERILOG/verilog-manual.html
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Signal Multiplexers
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
Two input multiplexer (using if / else) reg y; always @*
if (select) y = a; else y = b;
Two input multiplexer (using ternary operator ?:)
wire t = (select ? a : b);
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Larger MultiplexersThree input multiplexer
reg s; always @* begin case (select2)
2'b00: s = a; 2'b01: s = b; default: s = c; endcase end
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
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Synchronous Storage Elements• Values change at times governed by clock
Clock Transition
t=0 t=1 t=201Clock
time
Clock Transition
S0Dout
t=0A B
A B CDin
t=0
Clock
Din DoutQD
– Clock• Input to circuit
– Clock Event• Example: Rising edge
– Flip/Flop• Transfers Value From Din to
Dout on Clock event
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Finite State MachinesCopyright 2001, John W. Lockwood, All Rights Reserved
Combinational Logic
Inputs (X)
S(t) S(t+1)=(X,S(t))
Outputs (Z)
StateNext
State Storage
...
[Moore](S(t))
[Mealy](X,S(t))
-or-
Q D
Q D
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Synthesizable Verilog : Delay Flip/Flops
From: http://eesun.free.fr/DOC/VERILOG/synvlg.html
D type flip flop with data enablereg q; always @ (posedge clk)
if (enable) q <= d;
D-type flip flop reg q; always @ (posedge clk)
q <= d;
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More on NetFPGA System
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NetFPGA System
User Space
Linux Kernel
NIC
GE
PCI-ePCI
Browser& Video
Client
MonitorSoftware
GE
GE
GE
GE
GE
CADTools
NetFPGA RouterHardware
VI VI VI VI
Packet Forwarding Table
(eth1 .. 2)(nf2c0 .. 3)
Web &VideoServer
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NetFPGA System Implementation• NetFPGA Blocks
– Virtex-2 Pro FPGA– 4.5MB ZBT SRAM– 64MB DDR2 DRAM – PCI Host Interface– 4 Gigabit Ethernet ports
• Intranet Test Ports – Dual or Quad Gigabit
Etherents on PCI-e
• Internet – Gigabit Ethernet
on Motherboard
• Processor – Dual-Core CPU
• Operating System– Linux CentOS 4.4
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NetFPGA Lab Setup
(eth1 .. 2)
Nf2c3 : Adj. ServerCPU x2 Net-FPGA
Dual NICGEPCI-e
PCI
Client
NetFPGAControl SW
GE
GE
GE
GE
GECAD Tools
InternetRouter
Hardware
Eth2 : Server
ServerEth1 : Local host
Nf2c1 : Adjacent
Nf2c2 : Local Host
Nf2c0 : Adjacent
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Exception Path
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Exception Packet
• Example: TTL = 0 or TTL = 1• Packet has to be sent to the CPU which will
generate an ICMP packet as a response• Difference starts at the Output Port lookup
stage
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Exception Packet PathSoftware
PCI Bus
NetFPGA
PW-OSPF Java GUI
Driver
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
nf2_reg_grp
user data path
DMA Registers
nf2c0 nf2c1 nf2c2 nf2c3 ioctl
MACTxQ
MACRxQ
MACTxQ
MACRxQ
MACTxQ
MACRxQ
MACTxQ
MACRxQ
Ethernet
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Output Port Lookup
IP Hdr:IP Dst: 192.168.2.3, TTL:
1, Csum:0x3ab4
Output Port Lookup
EthHdr: Dst MAC = 0,Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 10x04
1- Check input port matches Dst
MAC
2- Check TTL, checksum – EXCEPTION!
3- Add output port module
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Output Queues
Output Queues
OQ0
OQ1
OQ2
OQ7
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CPU Tx Queue
CPU Tx Queue
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CPU Tx Queue
CPU Tx Queue
IP Hdr:IP Dst: 192.168.2.3, TTL:
1, Csum:0x3ab4
EthHdr: Dst MAC = 0, Src MAC = x,
Ethertype = IP
Data
0
0
0
Pkt length,input port = 0
0xff
output port = 10x04
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ICMP Packet
• For the ICMP packet, the packet arrives at the CPU Rx Queue from the PCI Bus
• Follows the same path as a packet from the MAC until the Output Port Lookup.
• The OPL module seeing the packet is from the CPU Rx Queue 1, sets the output port directly to 0.
• The packet then continues on the same path as the non-exception packet to the Output Queues and then MAC Tx queue 0.
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ICMP Packet PathSoftware
PCI Bus
NetFPGA
PW-OSPF Java GUI
Driver
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
CPURxQ
CPUTxQ
nf2_reg_grp
user data path
DMA Registers
nf2c0 nf2c1 nf2c2 nf2c3 ioctl
MACTxQ
MACRxQ
MACTxQ
MACRxQ
MACTxQ
MACRxQ
MACTxQ
MACRxQ
Ethernet
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NetFPGA-Host InteractionNetFPGA to host packet transfer
PCI Bus
2. Interrupt notifies driver of packet arrival
3. Driver sets up and initiates DMA transfer
1. Packet arrives – forwarding table sends to CPU queue
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NetFPGA-Host InteractionNetFPGA to host packet transfer (cont)
PCI Bus
4. NetFPGA transfers packet via DMA
5. Interrupt signals completion of DMA
6. Driver passes packet to network stack
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NetFPGA-Host InteractionHost to NetFPGA packet transfers
PCI Bus
3. Interrupt signals completion of DMA
1. Software sends packet via network sockets. Packet delivered to driver.
2. Driver sets up and initiates DMA transfer