cs 61c l33 single cycle cpu datapath, with verilog ii (1) garcia, spring 2004 © ucb lecturer psoe...
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CS 61C L33 Single Cycle CPU Datapath, with Verilog II (1) Garcia, Spring 2004 © UCB
Lecturer PSOE Dan Garcia
www.cs.berkeley.edu/~ddgarcia
inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures
Lecture 33 – Single Cycle CPU Datapath, with Verilog II
2004-04-14
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CS 61C L33 Single Cycle CPU Datapath, with Verilog II (2) Garcia, Spring 2004 © UCB
Storage Element: Idealized Memory
• Memory (idealized)• One input bus: Data In• One output bus: Data Out
• Memory word is selected by:• Address selects the word to put on Data Out• Write Enable = 1: address selects the memory
word to be written via the Data In bus• Clock input (CLK)
• The CLK input is a factor ONLY during write operation• During read operation, behaves as a
combinational logic block:- Address valid => Data Out valid after “access time.”
Clk
Data In
Write Enable
32 32DataOut
Address
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (3) Garcia, Spring 2004 © UCB
Verilog Memory for MIPS Interpreter (1/3)//Behavioral modelof Random Access Memory:
// 32-bit wide, 256 words deep,// asynchronous read-port if RD=1,// synchronous write-port if WR=1,// initialize from hex file ("data.dat")// on positive edge of reset signal, // dump to binary file ("dump.dat") // on positive edge of dump signal.module mem (CLK,RST,DMP,WR,RD,address,writeD,readD); input CLK, RST, DMP, WR, RD; input [31:0] address, writeD; output [31:0] readD; reg [31:0] readD; parameter memSize=256; reg [31:0] memArray [0:memSize-1]; integer chann,i;
// Temp variables: for loops ...
// ~ Constant dec.
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (4) Garcia, Spring 2004 © UCB
Verilog Memory for MIPS Interpreter (2/3)integer chann,i;
always @ (posedge RST) $readmemh("data.dat", memArray); always @ (posedge CLK) if (WR) memArray[address[9:2]] =
writeD;
always @ (address or RD) if (RD) begin readD = memArray[address[9:2]]; $display("Getting address %h containing %h", address[9:2], readD); end
// write if WR & positive clock edge (synchronous)
// read if RD, independent of clock (asynchronous)
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (5) Garcia, Spring 2004 © UCB
Why is it “memArray[address[9:2]]”?
• Our memory is always byte-addressed•We can lb from 0x0, 0x1, 0x2, 0x3, …
•lw only reads word-aligned requests•We only call lw with 0x0, 0x4, 0x8, 0xC, …• I.e., the last two bits are always 0
• memArray is a word wide and 28 deep•reg [31:0] memArray [0:256-1];•Size = 4 Bytes/row * 256 rows = 1024 B• If we’re simulating lw/sw, we R/W words•What bits select the first 256 words? [9:2]!• 1st word = 0x0 = 0b000 = memArray[0]; 2nd word = 0x4 = 0b100 = memArray[1], etc.
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (6) Garcia, Spring 2004 © UCB
Verilog Memory for MIPS Interpreter (3/3) end;
always @ (posedge DMP) begin chann = $fopen("dump.dat"); if (chann==0) begin $display("$fopen of dump.dat failed."); $finish; end for (i=0; i<memSize; i=i+1) begin $fdisplay(chann, "%b", memArray[i]); end end // always @ (posedge DMP)endmodule // mem
// Temp variables chan, i
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (7) Garcia, Spring 2004 © UCB
Peer Instruction
A. We should use the main ALU to compute PC=PC+4
B. We’re going to be able to read 2 registers and write a 3rd in 1 cycle
C. Datapath is hard, Control is easy
ABC1: FFF2: FFT 3: FTF4: FTT5: TFF6: TFT7: TTF8: TTT
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (8) Garcia, Spring 2004 © UCB
How to Design a Processor: step-by-step• 1. Analyze instruction set architecture (ISA)
=> datapath requirements•meaning of each instruction is given by the register transfers• datapath must include storage element for ISA registers• datapath must support each register transfer
• 2. Select set of datapath components and establish clocking methodology
• 3. Assemble datapath meeting requirements• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.
• 5. Assemble the control logic (hard part!)
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (9) Garcia, Spring 2004 © UCB
Storage Element: Register (Building Block)
•Register•Similar to the D Flip Flop except- N-bit input and output
- Write Enable input
•Write Enable:- negated (or deasserted) (0):
Data Out will not change
- asserted (1): Data Out will become Data In
Clk
Data In
Write Enable
N N
Data Out
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (10) Garcia, Spring 2004 © UCB
Verilog 32-bit Register for MIPS Interpreter// Behavioral model of 32-bit Register:// positive edge-triggered,// synchronous active-high reset.module reg32 (CLK,Q,D,RST); input [31:0] D; input CLK, RST; output [31:0] Q; reg [31:0] Q; always @ (posedge CLK) if (RST) Q = 0; else Q = D;endmodule // reg32
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (11) Garcia, Spring 2004 © UCB
Storage Element: Register File• Register File consists of 32 registers:• Two 32-bit output busses: busA and busB• One 32-bit input bus: busW
• Register is selected by:• RA (number) selects the register to put on busA (data)• RB (number) selects the register to put on busB (data)• RW (number) selects the register to be written
via busW (data) when Write Enable is 1• Clock input (CLK)
• The CLK input is a factor ONLY during write operation• During read operation, behaves as a combinational
logic block:- RA or RB valid => busA or busB valid after “access time.”
Clk
busW
Write Enable
3232
busA
32busB
5 5 5RWRA RB
32 32-bitRegisters
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (12) Garcia, Spring 2004 © UCB
Verilog Register File for MIPS Interpreter (1/3)// Behavioral model of register file:// 32-bit wide, 32 words deep,// two asynchronous read-ports,// one synchronous write-port.// Dump register file contents to// console on pos edge of dump signal.
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (13) Garcia, Spring 2004 © UCB
module regFile (CLK, wEnb, DMP, writeReg, writeD, readReg1, readD1, readReg2, readD2); input CLK, wEnb, DMP; input [4:0] writeReg, readReg1,
readReg2; input [31:0] writeD; output [31:0] readD1, readD2; reg [31:0] readD1, readD2; reg [31:0] array [0:31]; reg dirty1, dirty2; integer i;• 3 5-bit fields to select registers: 1 write register, 2 read register
Verilog Register File for MIPS Interpreter (2/3)
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (14) Garcia, Spring 2004 © UCB
Verilog Register File for MIPS Interpreter (3/3)always @ (posedge CLK) if (wEnb) if (writeReg!=4'h0) // why? begin array[writeReg] = writeD; dirty1=1'b1; dirty2=1'b1; endalways @ (readReg1 or dirty1) begin
readD1 = array[readReg1];dirty1=0;
end
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (15) Garcia, Spring 2004 © UCB
Step 3: Assemble DataPath meeting requirements
• Register Transfer Requirements Datapath Assembly
• Instruction Fetch
• Read Operands and Execute Operation
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (16) Garcia, Spring 2004 © UCB
3a: Overview of the Instruction Fetch Unit
• The common RTL operations• Fetch the Instruction: mem[PC]•Update the program counter:- Sequential Code: PC = PC + 4 - Branch and Jump: PC = “something else”
32
Instruction WordAddress
InstructionMemory
PCClk
Next AddressLogic
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (17) Garcia, Spring 2004 © UCB
3b: Add & Subtract• R[rd] = R[rs] op R[rt] Ex.: addU rd, rs, rt
•Ra, Rb, and Rw come from instruction’s Rs, Rt, and Rd fields
•ALUctr and RegWr: control logic after decoding the instruction
32Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
op rs rt rd shamt funct061116212631
6 bits 6 bits5 bits5 bits5 bits5 bits
• Already defined register file, ALU
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (18) Garcia, Spring 2004 © UCB
Clocking Methodology
• Storage elements clocked by same edge• Being physical devices, flip-flops (FF) and combinational logic have some delays •Gates: delay from input change to output change •Signals at FF D input must be stable before active clock edge to allow signal to travel within the FF, and we have the usual clock-to-Q delay
• “Critical path” (longest path through logic) determines length of clock period
Clk
.
.
.
.
.
.
.
.
.
.
.
.
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (19) Garcia, Spring 2004 © UCB
Register-Register Timing: One complete cycle
32Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs RtRd
AL
U
Clk
PC
Rs, Rt, Rd,Op, Func
ALUctr
Instruction Memory Access Time
Old Value New Value
RegWr Old Value New Value
Delay through Control Logic
busA, BRegister File Access TimeOld Value New Value
busWALU Delay
Old Value New Value
Old Value New Value
New ValueOld Value
Register WriteOccurs Here
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (20) Garcia, Spring 2004 © UCB
3c: Logical Operations with Immediate• R[rt] = R[rs] op ZeroExt[imm16] ]
32
Result
ALUctr
Clk
busW
RegWr
3232
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs
ZeroE
xt
Mu
x
RtRdRegDst
Mux
3216imm16
ALUSrc
AL
U
11
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits rd?
immediate
016 1531
16 bits16 bits
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Rt?
• Already defined 32-bit MUX; Zero Ext?
What about Rt register read??
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (21) Garcia, Spring 2004 © UCB
3d: Load Operations• R[rt] = Mem[R[rs] + SignExt[imm16]]Example: lw rt, rs, imm16
op rs rt immediate
016212631
6 bits 16 bits5 bits5 bits
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5
Rw Ra Rb
32 32-bitRegisters
Rs
RtRd
RegDst
Exten
der
Mu
x
Mux
3216
imm16
ALUSrc
ExtOp
Clk
Data InWrEn
32
Adr
DataMemory
32
AL
U
MemWr Mu
x
W_Src
??
Rt?
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (22) Garcia, Spring 2004 © UCB
3e: Store Operations• Mem[ R[rs] + SignExt[imm16] ] = R[rt]
Ex.: sw rt, rs, imm16
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
Mux
3216imm16
ALUSrcExtOp
Clk
Data InWrEn
32Adr
DataMemory
MemWr
AL
U
32
Mu
x
W_Src
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (23) Garcia, Spring 2004 © UCB
3f: The Branch Instruction
• beq rs, rt, imm16•mem[PC]Fetch the instruction from memory
•Equal = R[rs] == R[rt] Calculate the branch condition
• if (Equal) Calculate the next instruction’s address- PC = PC + 4 + ( SignExt(imm16) x 4 )
else- PC = PC + 4
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (24) Garcia, Spring 2004 © UCB
Datapath for Branch Operations• beq rs, rt, imm16
Datapath generates condition (equal)
op rs rt immediate016212631
6 bits 16 bits5 bits5 bits
32
imm16
PC
Clk
00
Ad
der
Mu
x
Ad
der
4nPC_sel
Clk
busW
RegWr
32
busA
32busB
5 5 5
Rw Ra Rb32 32-bitRegisters
Rs Rt
Eq
ual
?
Cond
PC
Ext
Inst Address
• Already MUX, adder, sign extend, zero
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (25) Garcia, Spring 2004 © UCB
Putting it All Together:A Single Cycle Datapath
imm
16
32
ALUctr
Clk
busW
RegWr
3232
busA
32busB
55 5
Rw Ra Rb32 32-bitRegisters
Rs
Rt
Rt
RdRegDst
Exten
der
Mu
x
3216imm16
ALUSrcExtOp
Mu
x
MemtoReg
Clk
Data InWrEn32 Adr
DataMemory
MemWrA
LU
Equal
Instruction<31:0>
0
1
0
1
01
<21:25>
<16:20>
<11:15>
<0:15>
Imm16RdRtRs
=
Ad
der
Ad
der
PC
Clk
00Mu
x
4
nPC_sel
PC
Ext
Adr
InstMemory
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (26) Garcia, Spring 2004 © UCB
Peer Instruction
Suppose we’re writing a MIPS interpreter in Verilog. Which sequence below is best organization for the interpreter?
A. repeat loop that fetches instructionsB. while loop that fetches instructions C. Decodes instructions using case statementD. Decodes instr. using chained if statementsE. Executes each instructionF. Increments PC by 4
1: ACEF2: ADEF 3: AECF4: AEDF5: BCEF6: BDEF7: BECF8: BEDF9: EF0: FAE
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (27) Garcia, Spring 2004 © UCB
An Abstract View of the Implementation
DataOut
Clk
5
Rw Ra Rb32 32-bitRegisters
Rd
AL
U
Clk
Data In
DataAddress Ideal
DataMemory
Instruction
InstructionAddress
IdealInstruction
Memory
Clk
PC
5Rs
5Rt
32
323232
A
B
Nex
t A
dd
ress
Control
Datapath
Control Signals Conditions
CS 61C L33 Single Cycle CPU Datapath, with Verilog II (28) Garcia, Spring 2004 © UCB
°5 steps to design a processor• 1. Analyze instruction set => datapath requirements• 2. Select set of datapath components & establish clock
methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to
determine setting of control points that effects the register transfer.• 5. Assemble the control logic
°Control is the hard part°Next time!
Summary: Single cycle datapath
Control
Datapath
Memory
ProcessorInput
Output