CS61C:GreatIdeasinComputerArchitectureIntrotoAssemblyLanguage,MIPSIntro

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Instructors:VladimirStojanovic &NicholasWeaver

http://inst.eecs.Berkeley.edu/~cs61c/sp16

LevelsofRepresentation/Interpretation

lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)

HighLevelLanguageProgram(e.g.,C)

AssemblyLanguageProgram(e.g.,MIPS)

MachineLanguageProgram(MIPS)

HardwareArchitectureDescription(e.g.,blockdiagrams)

Compiler

Assembler

MachineInterpretation

temp=v[k];v[k]=v[k+1];v[k+1]=temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

ArchitectureImplementation

Anythingcanberepresentedasanumber,

i.e.,dataorinstructions

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LogicCircuitDescription(CircuitSchematicDiagrams)

AssemblyLanguage

• BasicjobofaCPU:executelotsofinstructions.• InstructionsaretheprimitiveoperationsthattheCPUmayexecute.• DifferentCPUsimplementdifferentsetsofinstructions.ThesetofinstructionsaparticularCPUimplementsisanInstructionSetArchitecture (ISA).– Examples:ARM,Intelx86,MIPS,RISC-V,IBM/MotorolaPowerPC(oldMac),IntelIA64(akaItanic),...

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InstructionSetArchitectures• EarlytrendwastoaddmoreandmoreinstructionstonewCPUstodoelaborateoperations– VAXarchitecturehadaninstructiontomultiplypolynomials!

• RISCphilosophy(Cocke IBM,Patterson,Hennessy,1980s)–ReducedInstructionSetComputing– Keeptheinstructionsetsmallandsimple,makesiteasiertobuildfasthardware.

– Letsoftwaredocomplicatedoperationsbycomposingsimplerones.

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BerkeleyAcknowledgeforthefirstRISCcomputer

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FromRISC-ItoRISC-V

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EECS151/251A,CS152,CS250,CS252useRISC-V

MIPSArchitecture•MIPS– semiconductorcompanythatbuiltoneofthefirstcommercialRISCarchitectures•WewillstudytheMIPSarchitectureinsomedetailinthisclass(alsousedinupperdivisioncourses.WhenanupperdivisioncourseusesRISC-Vinstead,theISAisverysimilar)•WhyMIPSinsteadofIntelx86?

– MIPSissimple,elegant.Don’twanttogetboggeddowningrittydetails.

– MIPSwidelyusedinembeddedapps,x86littleusedinembedded,andmoreembeded computersthanPCs

• WhyMIPSinsteadofARM?– Accidentofhistory:Patterson&Hennesey isinMIPS– MIPSalsodesignedmoreforperformancethanARM,ARMis

insteaddesignedforsmallcodesize

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AssemblyVariables:Registers

• UnlikeHLLlikeCorJava,assemblycannotusevariables–Whynot?KeepHardwareSimple

• AssemblyOperandsareregisters– Limitednumberofspeciallocationsbuiltdirectlyintothehardware

– Operationscanonlybeperformedonthese!• Benefit:Sinceregistersaredirectlyinhardware,theyareveryfast(fasterthan1ns- lighttravels30cmin1ns!!!)

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NumberofMIPSRegisters

• Drawback:Sinceregistersareinhardware,thereareapredeterminednumberofthem– Solution:MIPScodemustbeverycarefullyputtogethertoefficientlyuseregisters

• 32registersinMIPS–Why32?Smallerisfaster,buttoosmallisbad.Goldilocksproblem.

– X86hasmanyfewerregisters• EachMIPSregisteris32bitswide– Groupsof32bitscalledaword inMIPS

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NamesofMIPSRegisters

• Registersarenumberedfrom0to31• Eachregistercanbereferredtobynumberorname• Numberreferences:–$0,$1,$2,…$30,$31

• Fornow:– $16- $23è $s0- $s7 (correspondtoCvariables)– $8- $15 è $t0- $t7 (correspondtotemporaryvariables)– Laterwillexplainother16registernames

• Ingeneral,usenamestomakeyourcodemorereadable

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C,Javavariablesvs.registers

• InC(andmostHighLevelLanguages)variablesdeclaredfirstandgivenatype• Example: int fahr, celsius;

char a, b, c, d, e;

• EachvariablecanONLYrepresentavalueofthetypeitwasdeclaredas(cannotmixandmatchint andchar variables).• InAssemblyLanguage,registershavenotype;operation determineshowregistercontentsaretreated

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AdditionandSubtractionofIntegers

• AdditioninAssembly– Example: add $s0,$s1,$s2 (inMIPS)– Equivalentto: a=b+c (inC)whereCvariables⇔MIPSregistersare:

a⇔ $s0,b⇔ $s1,c⇔ $s2• SubtractioninAssembly– Example: sub $s3,$s4,$s5 (inMIPS)– Equivalentto: d=e- f (inC)whereCvariables⇔MIPSregistersare:

d⇔ $s3,e⇔ $s4,f⇔ $s5

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AdditionandSubtractionofIntegersExample1

• HowtodothefollowingCstatement?a=b+c+d- e;

• Breakintomultipleinstructionsadd $t0, $s1, $s2 # temp = b + cadd $t0, $t0, $s3 # temp = temp + dsub $s0, $t0, $s4 # a = temp - e

• AsinglelineofCmaybreakupintoseverallinesofMIPS.• Noticetheuseoftemporaryregisters– don’twanttomodifythevariableregisters$s• Everythingafterthehashmarkoneachlineisignored(comments)

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Immediates• Immediates arenumericalconstants• Theyappearoftenincode,sotherearespecialinstructionsforthem• AddImmediate:

addi $s0,$s1,-10 (inMIPS)f=g- 10 (inC)

whereMIPSregisters$s0,$s1 areassociatedwithCvariablesf,g

• Syntaxsimilartoadd instruction,exceptthatlastargumentisanumberinsteadofaregister

add $s0,$s1,$zero (inMIPS)f=g (inC)

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Overflow in Arithmetic• Reminder: Overflow occurs when there is a “mistake” in arithmetic due to the limited precision in computers.• Example (4-bit unsigned numbers):

15 1111+ 3 + 001118 10010

• But we don’t have room for 5-bit solution, so the solution would be 0010, which is +2, and “wrong”.

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Overflow handling in MIPS• Somelanguagesdetectoverflow(Ada),somedon’t(mostCimplementations)•MIPSsolutionis2kindsofarithmeticinstructions:– Thesecauseoverflowtobedetected

• add(add)• addimmediate(addi)• subtract(sub)

– Thesedonotcauseoverflowdetection• addunsigned(addu)• addimmediateunsigned(addiu)• subtractunsigned(subu)

• Compilerselectsappropriatearithmetic–MIPSCcompilersproduceaddu,addiu,subu

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Processor

Control

Datapath

DataTransfer:LoadfromandStoreto memory

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PC

Registers

Arithmetic&LogicUnit(ALU)

MemoryInput

Output

Bytes

Enable?Read/Write

Address

WriteData=Storetomemory

ReadData=Loadfrommemory

Processor-Memory Interface I/O-MemoryInterfaces

Program

Data

0123…

MemoryAddressesareinBytes

• Lotsofdataissmallerthan32bits,butrarelysmallerthan8bits– worksfineifeverythingisamultipleof8bits

• 8bitchunkiscalledabyte(1word=4bytes)

• Memoryaddressesarereallyinbytes,notwords

• Wordaddressesare4bytesapart– Wordaddressissameasaddressofleftmostbyte– mostsignificantbyte(i.e.Big-endianconvention)

04812…

15913…

261014…

371115…

Mostsignificantbyteinaword

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Transferfrom MemorytoRegister• Ccode

int A[100];g = h + A[3];

• UsingLoadWord(lw)inMIPS:lw $t0,12($s3) #Tempreg $t0getsA[3]add $s1,$s2,$t0 #g=h+A[3]

Note: $s3 – baseregister(pointer)12 – offsetinbytes

Offsetmustbeaconstantknownatassemblytime

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04812…

15913…

261014…

371115…

TransferfromRegisterto Memory• Ccode

int A[100];A[10] = h + A[3];

• UsingStoreWord(sw)inMIPS:lw $t0,12($s3) #Tempreg $t0getsA[3]add $t0,$s2,$t0 #Tempreg $t0getsh+A[3]sw $t0, 40($s3) #A[10]=h+A[3]

Note: $s3 – baseregister(pointer)12,40 – offsetsinbytes

$s3+12and$s3+40mustbemultiplesof4:Wordalignment!20

Loading and Storing bytes• Inadditiontoworddatatransfers(lw,sw),MIPShasbytedatatransfers:– loadbyte:lb– storebyte:sb

• Sameformataslw,sw• E.g.,lb $s0, 3($s1)– contentsofmemorylocationwithaddress=sumof“3”+contentsofregister$s1 iscopiedtothelowbytepositionofregister$s0.

byteloaded

zzz zzzzx

…is copied to “sign-extend”This bit

xxxx xxxx xxxx xxxx xxxx xxxx$s0:

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SpeedofRegistersvs.Memory

• Giventhat– Registers:32words(128Bytes)– Memory:Billionsofbytes(2GBto8GBonlaptop)

• andtheRISCprincipleis…– Smallerisfaster

• Howmuchfasterareregistersthanmemory??• About100-500timesfaster!– intermsoflatencyofoneaccess

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Administrivia• Hopefullyeveryoneturned-inHW0

• Project1out– due02/07@23:59:59– Makesureyoutestyourcodeonhivemachines,that’swhere

we’llgradethem!Thisiscritical: Your“lucky”not-crashduetoamemoryerroronyourmachinemaynotbe“luckynotcrash”onourgrading

• Bitbucket/edX forms– Fillout@http://goo.gl/forms/AiKsGIieIP– Due2/12/16

• Guerrillasectionsstarting soon– LookforPiazzapostandwebpagescheduleupdate

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HowmanyhourshonHomework0?

A:0≤h<5B:5≤h<10C:10≤h<15D:15≤h<20E:20≤h

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Clickers/Peer InstructionWe want to translate *x = *y +1 into MIPS(x, y pointers stored in: $s0 $s1)

A: addi $s0,$s1,1

B: lw $s0,1($s1)sw $s1,0($s0)

C: lw $t0,0($s1)addi $t0,$t0,1sw $t0,0($s0)

D: sw $t0,0($s1)addi $t0,$t0,1lw $t0,0($s0)

E: lw $s0,1($t0)sw $s1,0($t0)

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MIPSLogicalInstructions

Logical operations

Coperators

Java operators

MIPS instructions

Bit-by-bit AND & & andBit-by-bit OR | | orBit-by-bit NOT ~ ~ notShift left << << sllShift right >> >>> srl

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• Usefultooperateonfieldsofbitswithinaword− e.g.,characterswithinaword(8bits)

• Operationstopack/unpackbitsintowords• Calledlogicaloperations

Logic Shifting• ShiftLeft:sll $s1,$s2,2 #s1=s2<<2– Storein$s1 thevaluefrom$s2 shifted2bitstotheleft(theyfalloffend),inserting0’s onright;<<inC.Before:00000002hex00000000000000000000000000000010twoAfter: 00000008hex00000000000000000000000000001000two

Whatarithmeticeffectdoesshiftlefthave?

• ShiftRight:srl isoppositeshift;>>

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ArithmeticShifting• Shiftrightarithmeticmovesn bitstotheright(inserthighordersignbitintoemptybits)

• Forexample,ifregister$s0contained11111111111111111111111111100111two=-25ten

• Ifexecutedsra $s0,$s0,4,resultis:11111111111111111111111111111110two=-2ten

• Unfortunately,thisisNOTsameasdividingby2n− Failsforoddnegativenumbers− Carithmeticsemanticsisthatdivisionshouldroundtowards0

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AndInConclusion…• Computerwordsandvocabularyarecalledinstructionsandinstructionsetrespectively

• MIPSisexampleRISCinstructionsetinthisclass• Rigidformat:1operation,2sourceoperands,1destination– add,sub,mul,div,and,or,sll,srl,sra– lw,sw,lb,sb tomovedatato/fromregistersfrom/tomemory

– beq, bne, j, slt, slti fordecision/flowcontrol• Simplemappingsfromarithmeticexpressions,arrayaccess,if-then-elseinCtoMIPSinstructions

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