CS 3220:Compilation Techniques for Parallel Systems

Spring 2016

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Phases of A Modern Compiler

Lexical Analyzer

Syntax Analyzer

Semantic Analyzer

Code Optimizer

Code Generation

Source Program IF (a<b) THEN c=1*d;

Token Sequence

Syntax Tree

3-Address Code

Optimized 3-Addr. Code

Assembly Code

IF ( ID“a” < ID

“b”THEN

ID“c” = CONST

“1” * ID“d”

IF_stmt<

a

b

cond_expr

listassign_stmt

c

*

lhs

rhs 1

dGE a, b, L1MUlT 1, d, cL1:

GE a, b, L1MOV d, cL1: loadi R1,a

cmpi R1,bjge L1loadi R1,dstorei R1,cL1:

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Three-pass Compilation

Front End

Middle End

Back End

Sourceprogram

IR IR machinecode

CS 2210 CS 3220

Organization of CS 3220 Advanced compilation techniques

Dataflow analysis framework Selected compilation techniques

• Pointer analysis, software pipelining, SSA, and more Parallel architectures

Traditional parallel systems• Multiprocessor, vector machine, VLIW

Chip-multiprocessor systems• Challenges and opportunities

Student presentations

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Control Flow Graph (CFG)1. A=42. T1=A*B3. L1:

T2 = T1/C4. If T2<W goto L25. M=T1*K6. T3=M+17. L2:

H=I8. M=T3-H9. If T3>0 goto L310. GOTO L111. L3:

halt

1. A=42. T1=A*B

B1

3. L1: T2=T1/C4. If T2<W goto L2

B2

5. M=T1*K6. T3=M+1

B3

7. L2: H=I8. M=T3-H9. If T3>0 goto L3

B4

10. Goto L1B5

11. L3: haltB6

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Dominators and Postdominators Definition

Node a dominates b if and only if every possible execution path from the entry of the code to b include a.• For example, B1 dominates B2, B3, …

Node a postdominates b if and only if every possible execution path from b to exit include a.• For example, B4 postdominates B2

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Finding a Loop Back edge

A back edge is an edge ab and head b dominates its tail aThat is,

The edge B5B2 in the previous example

Natural loops A natural loop has

• Header: a single-entry node that dominates all nodes in the loop;• Back edge: a back edge that enter from the header.

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Global Dataflow Analysis Dataflow analysis framework

A standard technique for solving global analysis problems A formal approach

Definition: a DFA consists of the following components L: A set of partially ordered elements, the set can be infinite

Two special elements: top ┬ and bottom ┴ Two operators: meet

join Dataflow functions: F: L L

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Forward and Backward Analysis

Forward Analysis Backward Analysis

X_in

X_out

X_in

X_out

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Example: Liveness Analysis Once constants have been globally propagated, we would like

to eliminate dead code

After constant propagation, if x is not used elsewhere, “x:=3” is dead and can be removed

X:=3If B>0

Y:= Z+W Y:= 0

A:= 2 * 3

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Global analysis – livenessx:= …

(no other definition of x) x is live anywhere here… := x

Two names interfere when their values cannot reside in the same register

x:= …y:= …

x interfere with y … := x -- they are both live simultaneously… := y

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Dataflow Equations forLiveness Analysis X(i): dataflow property of basic block i

X_in(i): at the entry of basic block i X_out(i): at the exit of basic block i

Liveness: LV_in(i) = ( LV_out(i) – DEF(i) ) USE(i)LV_out(i) = LV_in(k) if k is successor basic block of i

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Using Liveness InformationRegister allocation

a:= b+cd:= -ae:= d+f

f:= 2*e b:= d+ee:= e -1

b:= f+c

{b}

{b}

{ b,c,e,f }

{ c,d,e,f }

{ c,f } { c,f }

{ c,e }

{ a,c,f }

{ c,d,e,f }

{ b,c,f }{ c,d,f }

{ c,f }

{ b,c,f }

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Register Interference Graph (RIG) For our example

a

f b

e c

d

b, c can NOT be in the same registera, b, d can be in the same register

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Register Allocation Result For our example

a

f b

e c

d

There is no coloring with less than 4 colorsThere are 4 colorings of this graph

R2

R1R3

R3

R4R2

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After Register Allocation Use this coloring the code becomes:

r2:= r3+r4r3:= -r2r2:= r3+r1

r1:= 2*r2 r3:= r3+r2r2:= r2 -1

r3:= r1+r4