CS152ComputerArchitectureandEngineeringCS252GraduateComputerArchitecture

Lecture2-SimpleMachineImplementa=ons

KrsteAsanovicElectricalEngineeringandComputerSciences

UniversityofCaliforniaatBerkeley

http://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs152

LastTimeinLecture1§ ComputerArchitecture>>ISAsandRTL

–  CS152isaboutinteracGonofhardwareandsoIware,anddesignofappropriateabstracGonlayers

§  TechnologyandApplicaGonsshapeComputerArchitecture–  Historyprovideslessonsforthefuture

§  First130yearsofCompArch,fromBabbagetoIBM360–  Movefromcalculators(nocondiGonals)tofullyprogrammablemachines–  RapidchangestartedinWWII(mid-1940s),movefromelectro-mechanicaltopureelectronicprocessors

§ CostofsoIwaredevelopmentbecomesalargeconstraintonarchitecture(needcompaGbility)

§  IBM360introducesnoGonof“familyofmachines”runningsameISAbutverydifferentimplementaGons–  Sixdifferentmachinesreleasedonsameday(April7,1964)–  “Future-proofing”forsubsequentgeneraGonsofmachine

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Instruc=onSetArchitecture(ISA)

§  ThecontractbetweensoIwareandhardware§  Typicallydescribedbygivingalltheprogrammer-visiblestate(registers+memory)plusthesemanGcsoftheinstrucGonsthatoperateonthatstate

§  IBM360wasfirstlineofmachinestoseparateISAfromimplementaGon(aka.microarchitecture)

§ ManyimplementaGonspossibleforagivenISA–  E.g.,Sovietsbuiltcode-compaGbleclonesoftheIBM360,asdidAmdahlaIerheleIIBM.

–  E.g.2.,AMD,Intel,VIAprocessorsruntheAMD64ISA–  E.g.3:manycellphonesusetheARMISAwithimplementaGonsfrommanydifferentcompaniesincludingApple,Qualcomm,Samsung,Huawei,etc.

§ WeuseRISC-VasstandardISAinclass(www.riscv.org)–  Manycompaniesandopen-sourceprojectsbuildRISC-VimplementaGons

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ISAtoMicroarchitectureMapping

§  ISAoIendesignedwithparGcularmicroarchitecturalstyleinmind,e.g.,Accumulator⇒hardwired,unpipelinedCISC ⇒microcodedRISC ⇒hardwired,pipelinedVLIW ⇒fixed-latencyin-orderparallelpipelinesJVM ⇒soIwareinterpretaGon

§ Butcanbeimplementedwithanymicroarchitecturalstyle–  IntelIvyBridge:hardwiredpipelinedCISC(x86)

machine(withsomemicrocodesupport)–  Spike:SoIware-interpretedRISC-Vmachine–  ARMJazelle:AhardwareJVMprocessor–  Thislecture:amicrocodedRISC-Vmachine

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WhyLearnMicroprogramming?

§ ToshowhowtobuildverysmallprocessorswithcomplexISAs§ TohelpyouunderstandwhereCISC*machinescamefrom§ BecausesGllusedincommonmachines(x86,IBM360,PowerPC)§ AsagentleintroducGonintomachinestructures§ TohelpunderstandhowtechnologydrovethemovetoRISC*

*“CISC”/”RISC”namesmuchnewerthanstyleofmachinestheyreferto.

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ControlversusDatapath

§  Processordesignscanbesplitbetweendatapath,wherenumbersarestoredandarithmeGcoperaGonscomputed,andcontrol,whichsequencesoperaGonsondatapath

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§  Biggestchallengeforearlycomputerdesignerswasgejngcontrolcircuitrycorrect

§  MauriceWilkesinventedtheideaofmicroprogrammingtodesignthecontrolunitofaprocessorforEDSAC-II,1958-  ForeshadowedbyBabbage’s“Barrel”andmechanismsinearlierprogrammablecalculators

CondiGon?

Control

MainMemory

Address Data

ControlLines

Datapath

PC

Inst.R

eg.

Registers

ALU

InstrucGon

Busy?

MicrocodedCPU

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Datapath

MainMemory(holdsuserprogramwri?eninmacroinstruc@ons,e.g.,x86,RISC-V)

Address Data

Decoder

µPCMicrocodeROM(holdsfixedµcodeinstruc@ons)

NextState

ControlLines

Opcod

e

Cond

iGon

Busy?

TechnologyInfluence

§ Whenmicrocodeappearedin1950s,differenttechnologiesfor:– Logic:VacuumTubes– MainMemory:MagneGccores– Read-OnlyMemory:Diodematrix,punchedmetalcards,…

§ LogicveryexpensivecomparedtoROMorRAM§ ROMcheaperthanRAM§ ROMmuchfasterthanRAM

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RISC-VISA

§ NewfiIh-generaGonRISCdesignfromUCBerkeley§ RealisGc&completeISA,butopen&small§ Notover-architectedforacertainimplementaGonstyle§ Both32-bit(RV32)and64-bit(RV64)address-spacevariants§ DesignedformulGprocessing§  EfficientinstrucGonencoding§  Easytosubset/extendforeducaGon/research§ RISC-VspecavailableonFoundaGonwebsiteandgithub§  IncreasingmomentumwithindustryadopGon

§  PleaseseeCS61CFall2017,Lectures5-7forRISC-VISAreview:http://inst.eecs.berkeley.edu/~cs61c/fa17/

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RV32ProcessorState

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Programcounter(pc)32x32-bitintegerregisters(x0-x31)• x0alwayscontainsa032floaGng-point(FP)registers(f0-f31)• eachcancontainasingle-ordouble-precisionFPvalue(32-bitor64-bitIEEEFP)

FPstatusregister(fcsr),usedforFProundingmode&excepGonreporGng

RISC-VInstruc=onEncoding

§ Cansupportvariable-lengthinstrucGons.§ BaseinstrucGonset(RV32)alwayshasfixed32-bitinstrucGonslowesttwobits=112

§ Allbranchesandjumpshavetargetsat16-bitgranularity(eveninbaseISAwhereallinstrucGonsarefixed32bits)

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RISC-VInstruc=onFormats

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DesGnaGonReg.

Reg.Source1

Reg.Source27-bitopcodefield(butlow2bits=112)

AddiGonalopcodebits/immediate

Single-BusDatapathforMicrocodedRISC-V

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MicroinstrucGonswrivenasregistertransfers:§ MA:=PCmeansRegSel=PC;RegW=0;RegEn=1;MALd=1§ B:=Reg[rs2]meansRegSel=rs2;RegW=0;RegEn=1;BLd=1§ Reg[rd]:=A+BmeansALUop=Add;ALUEn=1;RegSel=rd;RegW=1

CondiGon?

MainMemory

PC

Registers

ALU

32(P

C)

rd

rs1

rs2

RegisterRAM

Address

InDataOutInstrucGon

Reg.

Mem

.Add

ressB

AImmed

iate

ImmEn RegEn ALUEn MemEn

ALUOp

Mem

W

ImmSel

RegW

BLdInstLd

MALd

ALd

RegSel

Busy?Opcode

RISC-VInstruc=onExecu=onPhases

§  InstrucGonFetch§  InstrucGonDecode§ RegisterFetch§ ALUOperaGons§ Op@onalMemoryOperaGons§ Op@onalRegisterWriteback§ CalculateNextInstrucGonAddress

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MicrocodeSketches(1)

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InstrucGonFetch: MA,A:=PC PC:=A+4 waitformemory IR:=Mem dispatchonopcode

ALU: A:=Reg[rs1]

B:=Reg[rs2] Reg[rd]:=ALUOp(A,B) gotoinstruc@onfetch

ALUI: A:=Reg[rs1]

B:=ImmI//Sign-extend12bimmediate Reg[rd]:=ALUOp(A,B) gotoinstruc@onfetch

MicrocodeSketches(2)

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LW: A:=Reg[rs1] B:=ImmI//Sign-extend12bimmediate

MA:=A+B waitformemory Reg[rd]:=Mem gotoinstruc@onfetch

JAL: Reg[rd]:=A//Storereturnaddress A:=A-4//RecoveroriginalPC B:=ImmJ//Jump-styleimmediate PC:=A+B gotoinstruc@onfetch

Branch: A:=Reg[rs1] B:=Reg[rs2] if(!ALUOp(A,B))gotoinstruc@onfetch//Nottaken A:=PC//Microcodefallthroughifbranchtaken A:=A-4 B:=ImmB//Branch-styleimmediate PC:=A+B gotoinstruc@onfetch

PureROMImplementa=on

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§ Howmanyaddressbits?|µaddress|=|µPC|+|opcode|+1+1

§ Howmanydatabits?|data|=|µPC|+|controlsignals|=|µPC|+18

§  TotalROMsize=2|µaddress|x|data|

µPC

ROMAddress

Data

Opcode Cond? Busy?

NextµPC ControlSignals

PureROMContents

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Address | DataµPC OpcodeCond?Busy? |ControlLines NextµPCfetch0 X X X |MA,A:=PC fetch1fetch1 X X 1 | fetch1fetch1 X X 0 |IR:=Mem fetch2fetch2 ALU X X |PC:=A+4 ALU0fetch2 ALUI X X |PC:=A+4 ALUI0fetch2 LW X X |PC:=A+4 LW0….ALU0 X X X |A:=Reg[rs1] ALU1ALU1 X X X |B:=Reg[rs2] ALU2ALU2 X X X |Reg[rd]:=ALUOp(A,B) fetch0

Single-BusMicrocodeRISC-VROMSize

§ InstrucGonfetchsequence3commonsteps§ ~12instrucGongroups§ Eachgrouptakes~5steps(1fordispatch)§ Totalsteps3+12*5=63,needs6bitsforµPC

§ Opcodeis5bits,~18controlsignals

§ Totalsize=2(6+5+2)x(6+18)=213x24=~25KiB!

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ReducingControlStoreSize

§ ReduceROMheight(#addressbits)–  Useexternallogictocombineinputsignals–  Reduce#statesbygroupingopcodes

§ ReduceROMwidth(#databits)–  RestrictµPCencoding(next,dispatch,waitonmemory,…)–  Encodecontrolsignals(verGcalµcoding,nanocoding)

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Single-BusRISC-VMicrocodeEngine

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µPC

Decode

ROMAddress

Data

Opcode

Cond?Busy?

ControlSignals

+1

fetch0

µPCJumpLogic

µPCjump

µPCjump=next|spin|fetch|dispatch|Irue|ffalse

µPCJumpTypes

§  nextincrementsµPC§  spinwaitsformemory§  fetchjumpstostartofinstrucGonfetch§  dispatchjumpstostartofdecodedopcodegroup§ Krue/ffalsejumpstofetchifCond?true/false

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EncodedROMContents

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Address | DataµPC |ControlLines NextµPCfetch0 |MA,A:=PC nextfetch1 |IR:=Mem spinfetch2 |PC:=A+4 dispatchALU0 |A:=Reg[rs1] nextALU1 |B:=Reg[rs2] nextALU2 |Reg[rd]:=ALUOp(A,B) fetchBranch0 |A:=Reg[rs1] nextBranch1 |B:=Reg[rs2] nextBranch2 |A:=PC ffalseBranch3 |A:=A-4 nextBranch4 |B:=ImmB nextBranch5 |PC:=A+B fetch

CS152Administrivia

§ GradingclarificaGons–  Youmustcomplete3/5labsorgetanautomaGcFregardlessofothergrades

§  Slipdays–  Problemsetshavenoslipdays–  Labshavetwofreeextensions(maxoneperlab)unGlnextclassaIerduedate

–  Nootherextensionswithoutdocumentedemergency

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CS252Administrivia

§ CS252ReadingsonWebsite–  MustusePiazzatosendprivatenoteoneachperpaperthreadtoinstructorsbeforemidnightSundaybeforeMondaydiscussioncontainingpaperreport:•  Writeoneparagraphonmaincontentofpaperincludinggood/badpointsofpaper

•  Also,1-3quesGonsaboutpaperfordiscussion•  Firsttwo“360Architecture”,“B5000Architecture”

§ CS252ProjectTimeline–  ProposalduestartofclassWedFeb26th–  OnepageinPDFformatincluding:

•  projectGtle•  teammembers(2perproject)•  whatproblemareyoutryingtosolve?•  whatisyourapproach?•  infrastructuretobeused•  Gmeline/milestones

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Implemen=ngComplexInstruc=ons

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Memory-memoryadd:M[rd]=M[rs1]+M[rs2]

Address | DataµPC |ControlLines NextµPCMMA0 |MA:=Reg[rs1] nextMMA1 |A:=Mem spinMMA2 |MA:=Reg[rs2] nextMMA3 |B:=Mem spinMMA4 |MA:=Reg[rd] nextMMA5 |Mem:=ALUOp(A,B) spinMMA6 | fetchComplexinstrucGonsusuallydonotrequiredatapathmodificaGons,onlyextraspaceforcontrolprogramVerydifficulttoimplementtheseinstrucGonsusingahardwiredcontrollerwithoutsubstanGaldatapathmodificaGons

Single-BusDatapathforMicrocodedRISC-V

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DatapathunchangedforcomplexinstrucGons!

CondiGon?

MainMemory

PC

Registers

ALU

32(P

C)

rd

rs1

rs2

RegisterRAM

Address

InDataOutInstrucGon

Reg.

Mem

.Add

ressB

AImmed

iate

ImmEn RegEn ALUEn MemEn

ALUOp

Mem

W

ImmSel

RegW

BLdInstLd

MALd

ALd

RegSel

Busy?Opcode

HorizontalvsVer=calµCode

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§ HorizontalµcodehaswiderµinstrucGons–  MulGpleparalleloperaGonsperµinstrucGon–  FewermicrocodestepspermacroinstrucGon–  Sparserencoding⇒morebits

§ VerGcalµcodehasnarrowerµinstrucGons–  TypicallyasingledatapathoperaGonperµinstrucGon

§  separateµinstrucGonforbranches–  MoremicrocodestepspermacroinstrucGon–  Morecompact⇒lessbits

§ Nanocoding–  TriestocombinebestofhorizontalandverGcalµcode

#µInstrucGons

BitsperµInstrucGon

Nanocoding

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§ Motorola68000had17-bitµcodecontainingeither10-bitµjumpor9-bitnanoinstrucGonpointer– NanoinstrucGonswere68bitswide,decodedtogive196controlsignals

µcodeROM

nanoaddress

µcodenext-state

µaddress

µPC(state)

nanoinstrucGonROMdata

Exploitsrecurringcontrolsignalpavernsinµcode,e.g.,ALU0 A←Reg[rs1]...ALUI0 A←Reg[rs1]...

MicroprogramminginIBM360

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§  Onlythefastestmodels(75and95)werehardwired

M30 M40 M50 M65Datapathwidth(bits) 8 16 32 64

µinstwidth(bits) 50 52 85 87

µcodesize(Kµinsts) 4 4 2.75 2.75

µstoretechnology CCROS TCROS BCROS BCROS

µstorecycle(ns) 750 625 500 200

memorycycle(ns) 1500 2500 2000 750

Rentalfee($K/month) 4 7 15 35

IBMCard-CapacitorRead-OnlyStorage

31[IBMJournal,January1961]

PunchedCardwithmetalfilm

Fixedsensingplates

MicrocodeEmula=on

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§  IBMiniGallymiscalculatedtheimportanceofsoIwarecompaGbilitywithearliermodelswhenintroducingthe360series

§ HoneywellstolesomeIBM1401customersbyofferingtranslaGonsoIware(“Liberator”)forHoneywellH200seriesmachine

§  IBMretaliatedwithopGonaladdiGonalmicrocodefor360seriesthatcouldemulateIBM1401ISA,laterextendedforIBM7000series–  onepopularprogramon1401wasa650simulator,sosomecustomersranmany650programsonemulated1401s

–  i.e.,650simulatedon1401emulatedon360

Microprogrammingthrivedin‘60sand‘70s

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§  SignificantlyfasterROMsthanDRAMswereavailable§  ForcomplexinstrucGonsets,datapathandcontrollerwerecheaperandsimpler

§ NewinstrucGons,e.g.,floaGngpoint,couldbesupportedwithoutdatapathmodificaGons

§  Fixingbugsinthecontrollerwaseasier§  ISAcompaGbilityacrossvariousmodelscouldbeachievedeasilyandcheaply

Exceptforthecheapestandfastestmachines,allcomputersweremicroprogrammed

Microprogramming:early1980s

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§  EvoluGonbredmorecomplexmicro-machines–  ComplexinstrucGonsetsledtoneedforsubrouGneandcallstacksinµcode

–  Needforfixingbugsincontrolprogramswasinconflictwithread-onlynatureofµROM

– èWritableControlStore(WCS)(B1700,QMachine,Inteli432,…)

§ WiththeadventofVLSItechnologyassumpGonsaboutROM&RAMspeedbecameinvalidàmorecomplexity

§ BevercompilersmadecomplexinstrucGonslessimportant.§ Useofnumerousmicro-architecturalinnovaGons,e.g.,pipelining,cachesandbuffers,mademulGple-cycleexecuGonofreg-reginstrucGonsunavracGve

VAX11-780Microcode

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WritableControlStore(WCS)

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§  ImplementcontrolstoreinRAMnotROM–  MOSSRAMmemoriesnowalmostasfastascontrolstore(corememories/DRAMswere2-10xslower)

–  Bug-freemicroprogramsdifficulttowrite

§ User-WCSprovidedasopGononseveralminicomputers–  Alloweduserstochangemicrocodeforeachprocessor

§ User-WCSfailed–  Livleornoprogrammingtoolssupport–  DifficulttofitsoIwareintosmallspace–  MicrocodecontroltailoredtooriginalISA,lessusefulforothers–  LargeWCSpartofprocessorstate-expensivecontextswitches–  ProtecGondifficultifusercanchangemicrocode–  Virtualmemoryrequiredrestartablemicrocode

Microprogrammingisfarfromex=nct

§  PlayedacrucialroleinmicrosoftheEighGes•  DECuVAX,Motorola68Kseries,Intel286/386

§  PlaysanassisGngroleinmostmodernmicros–  e.g.,AMDZen,IntelSkyLake,IntelAtom,IBMPowerPC,…–  MostinstrucGonsexecuteddirectly,i.e.,withhard-wiredcontrol–  Infrequently-usedand/orcomplicatedinstrucGonsinvokemicrocode

§  Patchablemicrocodecommonforpost-fabricaGonbugfixes,e.g.Intelprocessorsloadµcodepatchesatbootup–  IntelhadtoscrambletoresurrectmicrocodetoolsandfindoriginalmicrocodeengineerstopatchMeltdown/Spectresecurityvulnerabilites

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Acknowledgements

§  Theseslidescontainmaterialdevelopedandcopyrightby:–  Arvind(MIT)–  KrsteAsanovic(MIT/UCB)–  JoelEmer(Intel/MIT)–  JamesHoe(CMU)–  JohnKubiatowicz(UCB)–  DavidPaverson(UCB)

§ MITmaterialderivedfromcourse6.823§ UCBmaterialderivedfromcourseCS252

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