Critical Design ReviewCritical Design Review27 February 200727 February 2007

Black Box Car System (BBCS)Black Box Car System (BBCS)ctrl + z:ctrl + z:

Benjamin Baker, Lisa Furnish,Benjamin Baker, Lisa Furnish,Chris Klepac, Benjamin Mauser,Chris Klepac, Benjamin Mauser,

Zachary MiersZachary Miers

Project OverviewProject Overview

Recording visual data outside of carRecording visual data outside of car Data constantly stored in RAMData constantly stored in RAM When a crash is detected, data is When a crash is detected, data is

written from RAM to more permanent written from RAM to more permanent Flash storageFlash storage

User is able to video of events leading User is able to video of events leading up to crash on personal computerup to crash on personal computer

Initial SetbacksInitial Setbacks

Cannot use PSRAMCannot use PSRAM ARM9ARM9

Code spaceCode space Learning curve (software)Learning curve (software)

Routing data from camera to RAMRouting data from camera to RAM

System Block DiagramSystem Block Diagram

Black Box

Accelerometer

Reset

Storage

User Interface

Camera

PCInterface

Black Box Block DiagramBlack Box Block Diagram

STR9

Microcontroller

Power

LED/LCD

ComputerFlashStorage

RAMCamera

Accelerometer

FPGA

Hardware:Hardware:MicrocontrollerMicrocontroller

STR9STR9 Working with STR910-Working with STR910-

EVAL and STR912 EVAL and STR912 development boardsdevelopment boards

Take input from Take input from accelerometer and resetaccelerometer and reset

Communicate with FPGA Communicate with FPGA via GPIOvia GPIO

MicrocontrollerMicrocontrollerSchematicSchematic

ARMARMProgramming BlockProgramming Block

Run bootup code Receive I2C input from accelerometer

Transfer I2C data to register Monitor register for

4G reading

Toggle GPIO high—tell FPGA accident

has occurredStop receiving input

Hardware:Hardware:CameraCamera

ST VS6524ST VS6524 Using x24 Using x24

development boarddevelopment board 320 x 240320 x 240 8 frames per second8 frames per second RGB 565RGB 565 Focal length of 30mm Focal length of 30mm

to infinityto infinity

CameraCameraHSYNCHSYNC

CameraCameraData TransmissionData Transmission

CameraCameraImage SizeImage Size

Memory: 2^20[addresses] * 16[bits/address] * 2 [memory chips] = 33554432 bits

Image: 320(width) * 240[height] * 16 [bits/pixel] = 1228800 bits

Storage amount: Memory / Image [# of frames] = 27.3067 frames

Length of recording time: 27 frames * (1 / 8 [frames per second]) = 3.375 seconds

CameraCameraSchematicSchematic

8 data lines 8 data lines (output)(output)

HSYNC (output)HSYNC (output) VSYNC (output)VSYNC (output) CLK (input)CLK (input) PCLK (output)PCLK (output) SDA & SLC (I2C)SDA & SLC (I2C)

Hardware:Hardware:AccelerometerAccelerometer

ST LIS3LV02DQST LIS3LV02DQ Working with Working with

EK3LV02DQ (ST) EK3LV02DQ (ST) development boarddevelopment board

Will communicate Will communicate with processor via with processor via I2CI2C

4G will trigger data 4G will trigger data storagestorage

AccelerometerAccelerometerII22C InterfaceC Interface

Using I2C to interface directly with the Using I2C to interface directly with the microcontrollermicrocontroller

Tie the CS pin high to select I2C instead of Tie the CS pin high to select I2C instead of SPISPI

LIS3LV02DQ is an I2C slaveLIS3LV02DQ is an I2C slave 2 lines of interest with I2C bus; Serial Clock 2 lines of interest with I2C bus; Serial Clock

Line (SCL) and Serial DAta Line (SDA)Line (SCL) and Serial DAta Line (SDA) SDA is bidirectionalSDA is bidirectional Both lines have built in pull up resistorsBoth lines have built in pull up resistors

AccelerometerAccelerometer SchematicSchematic

Hardware:Hardware:MemoryMemory

Cypress Cypress CY7C1061AV33CY7C1061AV33

1M x 16 SRAM1M x 16 SRAM AsynchronousAsynchronous 2 chips2 chips Implement circular Implement circular

bufferbuffer Will store 27 framesWill store 27 frames

At 8 frames per second At 8 frames per second this will be 3.37 seconds this will be 3.37 seconds of videoof video

MemoryMemoryChip SelectChip Select

MemoryMemoryBlock DiagramBlock Diagram

MemoryMemoryTiming Diagram WriteTiming Diagram Write

MemoryMemoryTiming Diagram ReadTiming Diagram Read

MemoryMemoryOutputs and InputsOutputs and Inputs

5 Vcc inputs (high)5 Vcc inputs (high) 5 Vss inputs (low)5 Vss inputs (low) BHE-bar (low)BHE-bar (low) BLE-bar (low)BLE-bar (low) DNU (do not use)DNU (do not use) NC (not connected)NC (not connected)

20 address lines 20 address lines (input)(input)

16 parallel data 16 parallel data lines (input / lines (input / output)output)

CE1 (input)CE1 (input) CE2 (input)CE2 (input) WE (input)WE (input) OE (input)OE (input)

MemoryMemorySchematicSchematic

Hardware:Hardware:Flash MemoryFlash Memory

Secure Digital flash Secure Digital flash memory cardmemory card

Breakout Board for Breakout Board for DOSonCHIP FAT16 DOSonCHIP FAT16 FAT32 Module FAT32 Module

Write to Write to DOSonCHIP using DOSonCHIP using UART from FPGAUART from FPGA

Flash MemoryFlash MemoryInformationInformation

UARTUART SPI (Not Using)SPI (Not Using) Two will be used Two will be used

Accelerometer dataAccelerometer data Long term storage of Long term storage of

videovideo Baud rates:Baud rates:

1200, 2400, 9600, 1200, 2400, 9600, 28800, 38400, 28800, 38400, 57600, 57600, 115200115200, , 230400 [bps]230400 [bps]

UART_TXUART_TX UART_RXUART_RX UART_RTSUART_RTS UART_CTSUART_CTS

At 115200 [bps] At 115200 [bps] transfer of video transfer of video will take 4:48 will take 4:48 [min:sec][min:sec]

Flash MemoryFlash MemorySchematicSchematic

Hardware Power Hardware Power Requirements:Requirements:

Camera: 2.8V @ <50mACamera: 2.8V @ <50mA ARM9: 3.3V @ 200mA Max (I/O’s) ARM9: 3.3V @ 200mA Max (I/O’s)

and a 1.8V Core supply @ <20mAand a 1.8V Core supply @ <20mA SRAM: 2.8V @ <35mA totalSRAM: 2.8V @ <35mA total Xilinx Spartan 3: 5V @ 2.5A max Xilinx Spartan 3: 5V @ 2.5A max

(should be well under 1A for our (should be well under 1A for our application).application).

Power Supply Block Power Supply Block DiagramDiagram

Car Battery(8V-16V)

5V-4A Converter

3.3V 300mA MaxLDO Linear Regulator

2.8V 200mA MaxLDO Linear Regulator

1.8V 100mA MaxLDO Linear Regulator

CPU I/O’sCamera Digital and

Analog Supply’sCPU Core

Xilinx Spartan 3 PCB

External 12V BackupBattery

SRAM Supply

The result for a 5V-4A The result for a 5V-4A Supply:Supply:

LDO Linear Regulators:LDO Linear Regulators:

3.3V Supply: STMicroelectronics 3.3V Supply: STMicroelectronics LD1117 can supply up to 1A with a LD1117 can supply up to 1A with a dropout voltage of 1.15V.dropout voltage of 1.15V.

2.8V and 1.8V Supply: 2.8V and 1.8V Supply: STMicroelectronics LK112 can supply STMicroelectronics LK112 can supply up to 200mA with a dropout voltage up to 200mA with a dropout voltage of 0.35V.of 0.35V.

Supply Locations:Supply Locations:

5V-4A Switching converter on eval 5V-4A Switching converter on eval board. Run power wires to the other board. Run power wires to the other PCB’s.PCB’s.

LDO Linear regulators on the PCB’s LDO Linear regulators on the PCB’s where required.where required.

Power supply backup:Power supply backup:

12V battery that cuts in when the 12V battery that cuts in when the main supply fails. main supply fails.

The only time the backup supply is The only time the backup supply is needed is when an accident actually needed is when an accident actually occurs.occurs.

Supply Transients, Load dump, Supply Transients, Load dump, and mutual coupling.and mutual coupling.

Could safeguard all of these but we Could safeguard all of these but we only really need transient protection only really need transient protection and supply reverse polarity and supply reverse polarity protection.protection.

Hardware:Hardware:FPGAFPGA

Digilent XC3S200 Digilent XC3S200 Spartan-3 development Spartan-3 development boardboard

Will route data from Will route data from camera to RAM via I/O camera to RAM via I/O lineslines

Store entire frame on Store entire frame on development board, then development board, then move entire frame from move entire frame from FPGA SRAM to our large FPGA SRAM to our large SRAMSRAM

Move images from SRAM Move images from SRAM to flash memoryto flash memory

FPGAFPGAI/O pin LayoutI/O pin Layout

FPGAFPGAProgramming Block Programming Block

DiagramDiagram

Video input

Single frame storage

Transfer from single frame to multiple frame

storage

Pointer to Write Location

(Addressing of multiple frame storage)

Interrupt to stop video

Image header

information

Multiple frame storage

Pointer to Start Frame

(Addressing of multiple frame read)

Video output to flash memory

Multiple Frame Dump

Video Capture

Multiple Frame StorageInterrupt Sequence

Long Term Storage

Milestone DeliverablesMilestone Deliverables

Milestone 1:Milestone 1: PCB design and BOM v0.1PCB design and BOM v0.1 Formatting for Bitmap imagesFormatting for Bitmap images Send data to RAMSend data to RAM Write to Flash via PCWrite to Flash via PC Main Power PCBMain Power PCB

Milestone 2:Milestone 2: PCB v0.1 fabricated and populatedPCB v0.1 fabricated and populated Camera data to RAMCamera data to RAM Write to Flash via FPGAWrite to Flash via FPGA ARM9 communication (IARM9 communication (I22C and FPGA)C and FPGA) On-board user interfaceOn-board user interface

TimelineTimeline

QuestionsQuestions

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