cpu archeticture

8/10/2019 CPU archeticture

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Design of Control UnitThe purpose of the control unit is to translate

or decode instructions and generateappropriate enable signals to accomplish thedesired operation.

INSTRUCTION REGISTER CONTRO! UNIT

The control unit dri"es the associated processinghard#are b$ generating a set of signals that ares$nchroni%ed #ith a master cloc&


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'asic Operations of CU(.) Instruction interpretationCU reads an instruction from the memor$

addressed b$ the contents of the programcounter into the instruction register.

CU inputs the contents of the instructionregister.

Instruction T$pe Operands functionalunit routing to e*ecution unit.


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+.) Instruction Se,uencingCU generates the address of the ne*t

instruction to be e*ecuted and loads it into theprogram counter.


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-ethods in CU design(.) ard#ired ControlS$nchronous se,uential circuit design

procedures are used in the design process.

Note that a CU is a cloc&ed se,uential circuit

/hard#ired0 e"ol"ed from the fact that the 1nalcircuit is built b$ ph$sicall$ connecting thecomponents such as gates and 2ip32ops.


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+.) -icroprogrammed control4ll control functions are stored in RO- inside

the control unit

This memor$ is called the /control memor$0

5ords in this memor$ are called /control#ords0

6the$ specif$ the control functions to be performed b$ theCU)

Instruction is e*ecuted #hen

Control #ords6mem) routing functionalunits to enable gates.

Often referred to as /1rm#are0


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Design of control units using /microprogrammingis more e*pensi"e than using /hardwired0 controls.

To e*ecute an instruction the contents of the

control memor$ in micro3programmed control mustbe read7 #hich reduces the o"erall speed of thecontrol unit.

The most important ad"antage ofmicroprogramming is its 2e*ibilit$8 man$ additions

are made b$ simpl$ changing the microprogram inthe control memor$.

4 small change in the hard#ired approach ma$lead to redesigning the entire s$stem

ard#ired "s. -icroprogrammed


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T$pes of microprocessor

architectures(.) CISC 3 Comple* Instruction Set ComputerContains a large number of instructions #ith

man$ addressing modes.

+.) RISC 3 Reduced Instruction Set Computer9e#er instruction set #ith fe# instruction

modes.4lmost all computations can be obtained b$ a

fe# simple operation.


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RISC basicall$ supports a small set of commonl$used instructions #hich are e*ecuted at a fastcloc& rate compared to CISC #hich contains a

large instruction set 6some of #hich are rarel$used) e*ecuted at a slo#er cloc& rate.

Cloc& rate for CISC is t$picall$ slo#er in order toimplement fetch:e*ecute c$cle for a its largeinstruction set.

In CISC most instructions can access memor$#hile RISC contains mostl$ load:store instructions

RISC "s CISC


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CISC instruction set

Comple* unit microprogrammedimplementation

Di;cult to /PIPELINE0

9e#er instructions #ith fe#er fetch c$cles

RISCSimpler hard#ired #hich is faster

Easier to pipeline

Re,uires a large number of instructions toaccomplish the same tas& #ith se"eral fetchc$cles.

o#e"er it can signi1cantl$ impro"e its

performance #ith a faster cloc&7 more e;cient


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!aundr$ E*ample

4nn7 'rian7 Cath$7 Da"eeach ha"e one load of

clothes to #ash7 dr$7 andfold

5asher ta&es ?@ minutes Dr$er ta&es A@ minutes

/9older0 ta&es +@ minutes

A B C D


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Se,uential !aundr$

Se,uential laundr$ ta&es B hours for A loads If the$ learned pipelining7 ho# long #ould laundr$

ta&e

A

B

C

D

30 40 20 30 40 20 30 40 20 30 40 20

6 PM 7 8 9 10 11 Midnight

T

a

sk

O

r

d

er

Time


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'asic conceptsRegister transfer notation is the fundamental

concept associated #ith the control unitdesign.

The symbol

is called the transfer operator


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R(R@

This notation does not indicate the number of bitsto be transferred. 4 declaration statement

specif$ing the si%e of each register is used for the

purpose.

Declare registers R@ (BH7 R( (BH

The register can also be used to mo"e a speci1c

bit from one register to a particular bit position inanother.

R((HR@(AH


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4n enable signal usuall$ controls transfer of

data from one register to another. In the 1gurebelo# (B3bit contents of register R@ aretransferred to register R( of Enable E is IGother#ise the contents of R@ and R( remains

the same. Such conditional transfer can berepresented as=

E= R(R@


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-ultiple*er for man$ input lines to a singleoutput line

Transparent latch for direct data transfer


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The simplest of all bus structures is the single3busorgani%ation sho#n in the 1gure

atan$ time7 data ma$ be transferred bet#een an$ t#oregisters or bet#een a register and the ALU.

If the ALU re,uires t#o operands such as in response toan ADD instruction7 the operands can onl$ be transferredone at a time.

In single3bus architecture7 the bus must be multiple*edamong "arious operands.

Also, the ALU must ha"e buer registers to hold thetransferred operand.


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First clock cycle:The contents of R, are mo"edto buer register B, of the ALU.

Second clock cycle:The contents of R, aremo"ed to buer register B, of the ALU.

hird clock cycle:The sum generated b$ theALU is loaded into R,!

4single3bus structure slo#s do#n the speed ofinstruction e*ecution e"en though data ma$alread$ be in the microprocessor registers.

The instructions e*ecution time is longer if the

operands are in memor$t#o cloc& c$cles ma$ be re,uired to retrie"e the

operands into the microprocessor registers frome*ternal memor$.


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Therefore7 a single3bus architecture re,uires alarge number of states in the control logic7 somore hard#are ma$ be needed to design the

control unit.

'ecause all data transfers ta&e place through

the same bus one at a time7 the design eort tobuild the control logic is greatl$ reduced.


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4ll general3purpose registers are connected to bothbuses 6bus"and

The t#o operands re,uired b$ the 4!U are7 therefore7

routed in one cloc& c$cle.

Instruction e*ecution is faster because the 4!U does notha"e to #ait for the second operand7 unli&e the single3bus architecture. bus B# to form a t#o3bus architecture.


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9irst clock cycle:The contents of R, and R, aremo"ed to the inputs of 4!U.

The 4!U then generates the sum inthe output register.

Second clock cycle:The sum from the outputregister is routed to R,!

The performance of a t#o3bus architecture canbe impro"ed b$ adding a third bus 6bus $#, atthe output of the 4!U.


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9irst c$cle = The contents of R, and R, are mo"ed to theinputs of the 4!U "ia bus A and bus B

respecti"el$. The sum generated b$ the 4!U is thentransferred to R, "ia bus $!

The addition of the third bus #ill increase the s$stemcost and also the comple*it$ of the control unit design.

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