cplds and fpgas - devi ahilya vishwavidyalaya€¦ · characteristics describing cpld or fpga ......
TRANSCRIPT
![Page 1: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/1.jpg)
Chapter 21
CPLDs and FPGAs
![Page 2: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/2.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 2
Lesson 2
Field Programmable Gate Arrays (FPGAs)
![Page 3: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/3.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 3
Field Programmable gate array (FPGA)
• No distinct input and output stages as in the AND-OR array and macro-cell, of a PAL and GAL, respectively.
![Page 4: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/4.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 4
Field Programmable gate array (FPGA)
• Logic cells • All the logic cells arranged in the form,
say, 12 x 8 or 24 x 32 matrix (array). A 12 x 8 FPGA possess total 96 logic cells. A 24 x 32 FPGA possess 768 logic cells.
• Uses CLBs (Configurable Logic Block)and LUTs (look-up based structure)
![Page 5: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/5.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 5
Characteristics Describing CPLD or FPGA
• Number of logic cells or macro-cells• Technology for programming
interconnects between inputs and outputs and between CLBs
• Whether long or single or both interconnects programmable
• Array structure
![Page 6: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/6.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 6
Logic Cells ArrayInput-Output Blocks A logic
cell
A singleinterconnect A long
interconnect
An FPGA sub-array
![Page 7: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/7.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 7
Interconnects
• Dotted lines are single interconnects with programmable switches
• Dashed lines are long interconnects with programmable switches
![Page 8: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/8.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 8
Inter-connect
Inter- connect Line
Inter- connect Line a cell output
From a SRAM cell
Inter- connect Line a MUX input
Programmable MOSFET
![Page 9: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/9.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 9
Inter-connect
Inter- connect Line
MUX Input
Logic Cell
From an SRAM CellFrom an SRAM Cell
AND array input
![Page 10: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/10.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 10
Anti-fuse Interconnect structure
Dielectric Layer
n+
Insulator-semiconductortransition
Poly-silicon
![Page 11: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/11.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 11
CLB (Configurable Logic Block)
• CLB is a matrix with single length inter connects
• Row based architecture with single length Interconnect
• Hierarchical Structures
![Page 12: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/12.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 12
IO Block Inter-connects
• Connect by long inter-connects• Connects the CLBs through single
inter-connects and long interconnects
![Page 13: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/13.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 13
Logic cell• A combination circuit input stage for
SOPs plus a macro-cell designed in a much more flexible way with (i) Feedback possibilities not only from a neighbouring IO stage but from other stages as well, and (ii) provision of multiple outputs from a macro-cell.
![Page 14: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/14.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 14
Logic cell
A logic cell consists of the followings:(i) Gates to implement SOP function, (ii) D- FF with preset and clear, and (iii) Data path selector —multiplexer
(MUX) at the input.
![Page 15: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/15.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 15
Array of Cells • 100 to 750 cells in a single EPLD IC for
implementing FPGA • (i) The number of IO (input and output) pins
could be 50 to 200 • (ii) Number of clock inputs can be 8,and• (iii) Number of gates (NANDs or NORs)
could be from 1000 to 50,000. [Note: Xilinx has done pioneering work. A
latest FPGA XC2VP125 has 125136 logic cells.]
![Page 16: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/16.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 16
Logic cell of an FPGAXN1- XN6 MUX-1 AND Arrays
D
Q
Q
clock
GND
MUX-3
8th term
XN1
XN2S
R
MUX-1
BN1- BN2
YN1- YN6
BO
AO
DOCO
![Page 17: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/17.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 17
A logic cell• (i) two number six inputs AND gates,
four number two input AND gates, three number 2 to 1 MUXs and a clock input edge triggered D FF with the preset and clear inputs, and
• (ii) three number outputs from the ANDs, one output from the MUX and one output from the D FF.
![Page 18: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/18.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 18
A logic cell• Per logic cell, the total number of
inputs are 21 and outputs are 5.We can not only obtain SOP functions on the inputs but also the multiplexing and decoding functions at the inputs at the logic cell
![Page 19: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/19.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 19
A logic cell design
• Each cell arranged as an element in a matrix inside
• FPGA facilitates implementation of a multiple bits (16 or 32) complex combinational or sequential circuits
![Page 20: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/20.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 20
A logic cell design• The examples are an adder or other
arithmetic unit, a state machine, a shift register or an auto re-loadable counter.
![Page 21: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/21.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 21
A logic cell design
• D-FF in a cell of the FPGA configurable as JK FF, RS FF or T FF, which facilitates an implementation of the 16 or 32 bit circuit for the various types of the shift registers and counters
![Page 22: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/22.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 22
LUTs for Programming the cells
• LUT (Lookup table)• A table of inputs and outputs • Inputs are for a key
![Page 23: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/23.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 23
LUTs for Programming the cells
• LUT in an FPGA — 2m× 1 bit memory unit
• Interconnect switches are programmed to connect cell inputs through the LUTs or directly to the MUXs and other gates of a cell
![Page 24: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/24.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 24
Example of applications• Data acquisition logic, plant automatic
operation controller, graphic or image or voice processor, mouse interface, disk cache controller or parallel processor controller or encryption device, decryption device, pattern recognizer, DNA sequence storage, signature recorder
![Page 25: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/25.jpg)
Summary
![Page 26: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/26.jpg)
• FPGA is an array of programmable CLBs (configurable logic blocks)
• Each CLB has IO blocks• Each IO block has logic cells• Logic cells have MUXs and D-FF with S
and R inputs (usable as T, RS and JK)• SRAM based inter-connects• Interconnects are programmable fusible
links
![Page 27: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/27.jpg)
• SRAM based inter-connects• Interconnects are programmable fusible
links
![Page 28: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/28.jpg)
End of Lesson 2
FPGAs
![Page 29: CPLDs and FPGAs - Devi Ahilya Vishwavidyalaya€¦ · Characteristics Describing CPLD or FPGA ... • Row based architecture with single ... • LUT in an FPGA — 2 m × 1 bit memory](https://reader031.vdocuments.site/reader031/viewer/2022021822/5b15c0267f8b9a45448defec/html5/thumbnails/29.jpg)
Ch21L2- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006 29
THANK YOU