cots bts testing and improved reliability test methodsneil/sic_workshop/presentations_2015/p… ·...

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land ForcesUNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

UNCLASSIFIED

COTS BTS Testing and Improved

Reliability Test Methods

Aivars Lelis, Ron Green, Dan Habersat, and Mooro El

2015 August

2015 SiC MOS Program Review

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land Forces

• Lelis (and Green) :

• COTS BTS results

• Standard measurements

• Habersat :

• COTS BTS results

• Fast VT measurements

• Test Method Comparisons

• Lelis (and Green) :

• Improved Reliability Test Methods

Outline

UNCLASSIFIED


Outline

I. COTS BTS results• dramatic improvements in past year

II. Improved Reliability Test Methods

UNCLASSIFIED

UNCLASSIFIED The Nation’s Premier Laboratory for Land Forces04/17/2015

4

• Stress-and-measure test

sequence used to investigate BTI

and underlying physical

mechanisms

• NBTS and PBTS effects are

studied independently on separate

devices

• A sweep technique was used to

characterize VT and VT-sub.

Electrical Measurement Conditions:

Vds = 50.0 mV;

For VGS stress < 0 V:

VGS: linear sweep from -10 V to +15 V

For VGS stress > 0 V:

VGS: linear sweep from +15 V to -10 V

–VGS

HT+VGS (DC)

100 s

100 s

Time

Ga

te V

olt

ag

e

pre

1

neg1

pos

2

pos2

neg

3

pos

RT

–VGS

+VGS

3

neg

+VGS+VGS

PBTS Test Sequence

NBTS Test Sequence

ARL BTI Test Procedure

Back-and-forth:

Oxide-trap

activation

Unipolar stress:

VT shift

UNCLASSIFIED


5

0.0E+00

5.0E-03

1.0E-02

1.5E-02

2.0E-02

2.5E-02

3.0E-02

3.5E-02

3 4 5 6

I D(A

)

VGS (V)

1.0

2.0

3.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7V

T(V

)Cumulative Stress Time (s)

NBTS: 175 °C, –15 V

Time Dependent VT Degradation

175 °C175 °C

• VT drift is a measure of gate-oxide charging that occurs during stress

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-8.0

-6.0

-4.0

-2.0

0.0

2.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT-s

ub

Sh

ift

(V)

Cumulative Stress Time (s)

Vendor A (2014–05)

Vendor A (2012–04)

Vendor A (2014–08)

-8.0

-6.0

-4.0

-2.0

0.0

2.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT

Sh

ift

(V)


Vendor A (2014–05)

Vendor A (2012–04)

Vendor A (2014–08)

04/17/2015

6

Experimental Results – VT Drift

• The observed VT shift is due to unipolar gate-stressing and charging of

oxide defects.

Subthreshold VT

175 °C

Linear VT

NBTS: 175 °C, –15 V

175 °C

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-1.25

-1.00

-0.75

-0.50

-0.25

0.00

0.25

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT-s

ub

Sh

ift

(V)


Vendor A (2014–08)

Vendor B (2014–09)

-8.0

-6.0

-4.0

-2.0

0.0

2.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT-s

ub

Sh

ift

(V)


Vendor A (2014–05)

Vendor A (2012–04)

Vendor A (2014–08)

04/17/2015

7



oxide defects.

NBTS: 175 °C, –15 V

Vendor A vs time

175 °C

175 °C

Vendor A vs Vendor B

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8



oxide defects.

Previous Results—NBTS: –10, –15 V

Vendor A (2013–04) vs Vendor B (2013–04)

150 °C, –10 V

200 °C, –15 V

Ronald Green, A. Lelis, M. El, and D. Habersat, “Bias-Temperature-Stress Response of Commercially-

Available SiC Power MOSFETs,” Mater. Sci. Forum Vols. 821-823, p. 677 (2015).

UNCLASSIFIED


9




mechanisms



devices




Vds = 50.0 mV;





–VGS

HT+VGS (DC)

100 s

100 s

Time

Ga

te V

olt

ag

e

pre

1

neg1

pos

2

pos2

neg

3

pos

RT

–VGS

+VGS

3

neg

+VGS+VGS

PBTS Test Sequence

NBTS Test Sequence


Back-and-forth:

Oxide-trap

activation

Unipolar stress:

VT shift

UNCLASSIFIED


0.5

0.6

0.7

0.8

0.9

1.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

ΔV

T-s

ub

(V)

Stress Time (s)Cumulative Stress Time (s)

04/17/2015

10

Measured VT Hysteresis

1.E-09

1.E-08

1.E-07

1.E-06

1.E-05

1.E-04

1.E-03

1.E-02

1.E-01

-1 0 1 2 3 4

I D(A

)

VGS (V)

ΔVT-sub

28 °C

NBTS: 175 °C, –15 V

28 °C

• ΔVT provides a measure of trap activation that occurs at HT

UNCLASSIFIED


0.0

0.2

0.4

0.6

0.8

1.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

ΔV

T-s

ub

(V)


Vendor A (2014–05)

Vendor A (2014–08)

0.0

0.2

0.4

0.6

0.8

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

ΔV

T-s

ub

(V)


Vendor A (2014–08)

Vendor B (2014–09)

04/17/2015

11

Experimental Results – VT Hysteresis

NBTS: 175 °C, –15 V

Vendor A vs time Vendor A vs Vendor B

Tmeas. = 25 °C

Tmeas. = 25 °C

• VT hysteresis is a measure of the voltage shift that occurs in response to

a short-duration bipolar gate-stress.

UNCLASSIFIED


12




mechanisms



devices




Vds = 50.0 mV;





–VGS

HT+VGS (DC)

100 s

100 s

Time

Ga

te V

olt

ag

e

pre

1

neg1

pos

2

pos2

neg

3

pos

RT

–VGS

+VGS

3

neg

+VGS+VGS

PBTS Test Sequence

NBTS Test Sequence


Back-and-forth:

Oxide-trap

activation

Unipolar stress:

VT shift

UNCLASSIFIED


13



oxide defects.

PBTS: 175 °C, +25 V

Subthreshold VT

0.0

2.0

4.0

6.0

8.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT-s

ub

Sh

ift

(V)


Vendor A (2014–05)

Vendor A (2012–04)

Vendor A (2014–08)

175 °C

Linear VT

0.0

2.0

4.0

6.0

8.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT

Sh

ift

(V)


Vendor A (2014–05)

Vendor A (2014–08)

175 °C

UNCLASSIFIED


14



oxide defects.

PBTS: 175 °C, +25 V

Vendor A vs time

0.0

2.0

4.0

6.0

8.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT

Sh

ift

(V)


Vendor A (2014–05)

Vendor A (2014–08)

175 °C

0.00

0.25

0.50

0.75

1.00

1.25

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT

Sh

ift

(V)


Vendor A (2014–08)

Vendor B (2014–09)

175 °C

Vendor A vs Vendor B

UNCLASSIFIED


15



oxide defects.

Previous Results—PBTS: +15 V

Vendor A (2013–04) vs Vendor B (2013–04)

150 °C

200 °C

Ronald Green, A. Lelis, M. El, and D. Habersat, “Bias-Temperature-Stress Response of Commercially-

Available SiC Power MOSFETs,” Mater. Sci. Forum Vols. 821-823, p. 677 (2015).

UNCLASSIFIED


16




mechanisms



devices




Vds = 50.0 mV;





–VGS

HT+VGS (DC)

100 s

100 s

Time

Ga

te V

olt

ag

e

pre

1

neg1

pos

2

pos2

neg

3

pos

RT

–VGS

+VGS

3

neg

+VGS+VGS

PBTS Test Sequence

NBTS Test Sequence


Back-and-forth:

Oxide-trap

activation

Unipolar stress:

VT shift

UNCLASSIFIED


17

Experimental Results – VT Hysteresis

PBTS: 175 °C, +25 V

Vendor A vs time Vendor A vs Vendor B

0.0

0.2

0.4

0.6

0.8

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

ΔV

T-s

ub

(V)


Vendor A (2014–08)

Vendor B (2014–09)

Tmeas. = 25 °C

0.0

1.0

2.0

3.0

4.0

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

ΔV

T-s

ub

(V)


Vendor A (2014–05)

Vendor A (2014–08)

Tmeas. = 25 °C

• VT hysteresis is a measure of the voltage shift that occurs in response to

a short-duration bipolar gate-stress.

UNCLASSIFIED


Outline

I. COTS BTS results• dramatic improvements in past year

II. Improved Reliability Test Methods

UNCLASSIFIED


Reliability Qualification Specifications

AEC – Q101 Stress Test Qualification for Automotive Grade Discrete

Semiconductors

JEDEC JESD-22 A108C Reliability Test Methods for Packaged Devices

MIL-STD-750 Test Methods for Semiconductors

AEC Q101 – Rev C

JESD-22 A108C “Electrical testing shall be

completed as soon as

possible and no longer than

96 hours after removal of

bias from devices.”

UNCLASSIFIED


Development of Improved Reliability Test Methods for SiC (and GaN)

Objectives:

• Identify potential issues in existing

performance and reliability verification test

methods in MIL-PRF-19500

JC-13.1: Provides technical support

and recommendations to DoD

concerning environmental and electrical

test methods and procedures for

discrete electronic components.

DLA: Controlling agency of military

performance specifications and test

methods for semiconductor devices:

MIL-PRF-19500 and MIL-STD-750

Collaborators

• Propose

improved

test method

(1042.3

Burn-in and

life test for

power

MOSFETs)

in MIL-STD-

750

UNCLASSIFIED


SiC MOSFET Key Test Issues

• Measurement delay time

– Most important factor to

properly assess VT stability

– Short delay times are

recommended (< 1 ms is ideal)

– Long delay times relax the

applied dc gate-stress and can

lead to significant recovery in

VT

• Bias removal (when measuring)

– Requires re-application of the

gate-bias stress for at least as

long as the unbiased period

1E-6 1E-3 1E+0 1E+3 1E+6

Delay Time [s]

fast sample

fast sweep

slow sample

slow sweep

96-hour delay

JESD-22 A108C

1 hr delay

UNCLASSIFIED


Summary of Improved Test Method

Improved Reliability Test Method

for VT Stability in SiC MOSFETs

• Delay Time

• Minimize

• Re-apply bias if interrupted

• Measurement Speed and Method

• Standard SMU, sweeping ID-VGS

• Use PMU, sampled at VGS = VT for high-sensitivity application

• Stress-and-Measurement Sequence

• immediate measurement following uni-polar bias-temperature stress

• followed at end by: back-and-forth bi-polar stress-and-measure sequence (100-s +VGS, 100-s −VGS)

• Measurement Temperature• measure at the stress temperature

• re-measure at room temperature as well for high-sensitivity application

Schematic for improved test method

-VGS (t)

HT

Stress Time (s)

Ga

te V

olt

ag

e (

V)

-VGS

+VGS

1E-6 1E-3 1E+0 1E+3 1E+6

Delay Time [s]

fast sample

fast sweep

slow sample

slow sweep

96-hour delay

JESD-22 A108C

1 hr delay

UNCLASSIFIED


-0.25

0.00

0.25

0.50

0.75

1.00

1.25

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT

Sh

ift

(V)


Vendor A (2014–08)

Vendor B (2014–09)

-1.25

-1.00

-0.75

-0.50

-0.25

0.00

0.25

1E+2 1E+3 1E+4 1E+5 1E+6 1E+7

VT-s

ub

Sh

ift

(V)


Vendor A (2014–08)

Vendor B (2014–09)

04/17/2015

23


oxide defects.

NBTS: 175 °C, –15 V

175 °C

PBTS: 175 °C, +25 V

175 °C

Summary of Commercial Results

Vendor A vs Vendor B: VT Shift

UNCLASSIFIED


Si

Si

HDL (ARL) Oxide Hole-Trap Model:

(Developed to explain VT instability in

irradiated Si MOS.)

Si

Si

Reduce O vacancies

Tie up dangling bonds

• Oxide-Trap Activation

• During device processing

• High-Temperature stress under bias (DC and AC)

• activation energy of 1.1 eV

• evidence of interface-trap generation as well

• Possible HT electron trap

• Oxide-Trap Charging

• Occurs via direct tunneling mechanism

• Strong dependence on measurement conditions

• speed, direction, delay time, temperature

• Significant effect only under DC stress

• Interface traps may play intermediary role

• Oxide-Trap Reduction

• Improved oxidation technique

• Reduce process-induced damage

• Permanently passivate oxide traps

Summary of Basic Mechanisms

UNCLASSIFIED


New Publication

A.J. Lelis, R. Green, D.B. Habersat, and M. El,

“Basic Mechanisms of Threshold-Voltage Instability

and Implications for Reliability Testing of SiC

MOSFETs,” IEEE Trans. Elec. Dev., vol. 62:2, p 316

(February 2015).

UNCLASSIFIED


End of Talk

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