Correlated electron Random Access Memory: Physical

Design, Realization, and Characterization

by

Christopher R. McWilliams

B.S. Electrical Engineering, University of Colorado

Colorado Springs, 2008

A thesis submitted to the

Faculty of the Graduate School of the

University of Colorado in partial fulfillment

of the requirements for the degree of

Master of Science in Electrical Engineering

Department of Electrical and Computer Engineering

2013

c©Copyright by Christopher R. McWilliams 2013

All Rights Reserved

This thesis entitled:Correlated electron Random Access Memory: Physical Design, Realization, and

Characterizationwritten by Christopher R. McWilliams

has been approved for the Department of Electrical and Computer Engineering

Carlos A. Paz de Araujo

Thottam S. Kalkur

Zbigniew Celinski

Date

The final copy of this thesis has been examined by the signatories, and we find that both thecontent and the form meet acceptable presentation standards of scholarly work in the above

mentioned discipline.

iv

McWilliams, Christopher R. (M.S., Electrical Engineering)

Correlated electron Random Access Memory: Physical Design, Realization, and Characteriza-

tion

Thesis directed by Prof. Carlos A. Paz de Araujo

The device fabrication process, switching properties and characterization of Correlated

Electron Random Access Memories (CeRAMs) are described herein. Film synthesis techniques,

test pattern process flows, High temperature retention, Cycle dispersion and optimization, Cy-

cle Fatigue, and switching parameter optimization have been investigated. CeRAM’s display

initially conductive or “Born-ON” behavior without the need for the high electroforming volt-

ages usually required for other TMO based resistive memories. Nonvolatile data retention at

elevated temperatures up to 300C in addition to a wide operating range from -269C to 150C

for CeRAM has been confirmed. CeRAMs also show exceptional read endurance with no evi-

dence of fatigue out to 1012 cycles. Desirable scaling characteristics for high density memory

application have also been shown for CeRAMs due to a widening of the read window and con-

sistent write window as devices are scaled down. Characterization of these device parameters

and device modeling, using the fundamental physics of Mott and charge transfer insulators, is

the central point of this thesis.

Dedication

I dedicate this work to my loving family.

vi

Acknowledgements

This research would not have been possible without the involvement and support of

many people. First and foremost, I am deeply indebted to my academic adviser and mentor

Dr. Carlos A. Paz de Araujo. I give you my heartfelt thanks for your guidance in this work

and countless hours of discussion on the topics included within this thesis and crucial to the

understanding of my research both academically and professionally.

I would like to express my sincerest gratitude to Ms. Jolanta Celinska. Without your

contributions in materials synthesis and our mutual research interests, this thesis would have

been impossible. I have greatly enjoyed the opportunity of working with you over the past

several years and look forward to a long and rewarding friendship.

I would like to thank Dr. Orlando Auciello and his teams of scientists both currently at

the University of Texas at Dallas, and formerly at Argonne National Laboratories. Throughout

this research you have graciously provided valuable resources and expertise necessary for the

understanding and improvement of materials and devices studied for the research included in

this thesis.

Contents

Chapter

1 Introduction 1

1.1 Non-volatile Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1.1 Floating Gate and Charge Trap Memories . . . . . . . . . . . . . . . . . 3

1.1.2 Ferroelectric Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.1.3 Resistive Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2 Scope of Thesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Review of The Current Status of Resistive Memory Technology 10

2.1 Material Properties and Device Performance . . . . . . . . . . . . . . . . . . . . 11

2.1.1 Chalcogenides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.1.2 Binary Metal Oxides . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.3 Perovskites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

2.1.4 Solid-State Electrolytes . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

2.1.5 Organic and Molecular Systems . . . . . . . . . . . . . . . . . . . . . . . 13

2.2 Mechanism for Switching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3 Challenges of RRAM Development . . . . . . . . . . . . . . . . . . . . . . . . . 16

2.3.1 Materials Issues of Resistive Memories . . . . . . . . . . . . . . . . . . . 16

2.3.2 Reliability Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

viii

3 Electronic Phase Transitions in Correlated Systems 20

3.1 Non-Interacting Electrons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

3.2 Mott Insulators and the Mott Transition . . . . . . . . . . . . . . . . . . . . . . 23

3.3 The Hubbard Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

3.4 Green’s Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

4 Transport in Nanoscale Oxide Devices 33

4.1 The MIM Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.1.1 Potential energy and Image force . . . . . . . . . . . . . . . . . . . . . . 33

4.1.2 MIM current equations . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 Transport During the Phase Transition . . . . . . . . . . . . . . . . . . . . . . . 37

5 CeRAM 41

5.1 The CeRAM Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

5.2 Device Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

5.3 Characterization and Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

5.3.1 Physical and Chemical Characterization . . . . . . . . . . . . . . . . . . 48

5.3.2 Experimental Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.3.3 Results and Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

5.4 Modeling and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.4.1 Circuit simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.4.2 device modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

6 Summary and Outlook 91

ix

Bibliography 94

Appendix

A Code for simulations 101

B Derivations 107

B.1 MIM Diode current simplification . . . . . . . . . . . . . . . . . . . . . . . . . . 107

B.2 Tunneling Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

B.3 LRS Current equatinon derivation . . . . . . . . . . . . . . . . . . . . . . . . . 108

x

Tables

Table

2.1 RRAM Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.1 SR Latch Truth Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

xi

Figures

Figure

1.1 Crystal structure unit cell of a cubic perovskite (ABO3) Ferroelectric material. 6

1.2 Typical ferroelectric Polarization vs. voltage hysteresis loop. . . . . . . . . . . . 7

2.1 Table with highlighted materials used for RRAM devices in the literature . . . 18

3.1 band diagram for NiO. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

3.2 Mott-Hubbard metal-insulator transition. . . . . . . . . . . . . . . . . . . . . . 27

3.3 Mott-Hubbard vs. charge transfer insulator energy band structure. . . . . . . . 28

4.1 Total Potential Energy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

4.2 MIM diode current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.3 Schematic of the system described within the Landauer approach . . . . . . . . 38

4.4 Diode current vs. applied bias for a symmetric diode with charge near the Fermi

level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

4.5 Total MIM current with Diode current, Thermionic, and Tunneling current con-

tributions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

5.1 3-D Crystallographic representation of the (a)NiO octahedral and (b)Ni(CO)4

structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

5.2 The CeRAM MIM-cap test structure. . . . . . . . . . . . . . . . . . . . . . . . 44

5.3 Illustration of process flow for CeRAM test structure. . . . . . . . . . . . . . . 45

xii

5.4 CeRAM test structures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

5.5 XPS Spectra for Ni 2p energy spectrum in carbonyl ligand doped NiO CeRAM 49

5.6 XPS Spectra for O 1s energy spectrum in carbonyl ligand doped NiO CeRAM 50

5.7 SEM image at 20,000x magnification of defect and surface morphology Nickle

Oxide based CeRAM CSD film. . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.8 AFM topography scans for NiO films deposited using different precursor molar-

ities (scan size: 2µm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

5.9 HRTEM image of CeRAM cross-section . . . . . . . . . . . . . . . . . . . . . . 52

5.10 STEM image of CeRAM cross-section . . . . . . . . . . . . . . . . . . . . . . . 53

5.11 Electron energy loss spectrum scans for CeRAM sample . . . . . . . . . . . . . 54

5.12 EELS line scan of CeRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

5.13 LabVIEW GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5.14 Pulse switching GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

5.15 CeRAM testing equivalent circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 59

5.16 Load resistor compliance circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

5.17 1T1R MOSFET compliance circuit . . . . . . . . . . . . . . . . . . . . . . . . . 62

5.18 Cascode current mirror compliance circuit . . . . . . . . . . . . . . . . . . . . . 64

5.19 Typical I-V characteristics for (a)bipolar and (b)unipolar switching by voltage

sweep. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

5.20 Reset current vs. Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.21 On resistance vs. compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.22 I-V curves for CeRAM cell programmed using a 50µA compliance limit showing

a max IReset of approximately 70µA. . . . . . . . . . . . . . . . . . . . . . . . . 69

5.23 200 ms Reset pulse, 50 cycles Switching Reliability: 98% . . . . . . . . . . . . . 70

5.24 MOSFET transistor curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

5.25 Average read voltage across a 50Ω sense resistor for reset pulse widths of (a)

200 ms, (b) 100 ms, and (c) 50 ms. . . . . . . . . . . . . . . . . . . . . . . . . . 72

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5.26 ROn and ROff resistance of 100 consecutive cycles at room temperature and

the corresponding read margin. . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

5.27 Read endurance for high(ROff ) and low(ROn) resistance states of a (10×10)µm2

cell at room temperature with 0.2V read voltage. . . . . . . . . . . . . . . . . . 74

5.28 Nonvolatile data retention of high and low resistance states at elevated temper-

atures up to 300C for 1 hour. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

5.29 Full I-V hysteresis measurement showing bi-stable behavior at operating tem-

peratures (a) -269 C (b) 25 C and (c) 150 C. . . . . . . . . . . . . . . . . . . 76

5.30 Circuit schematic representation for CeRAM SPICE model . . . . . . . . . . . 77

5.31 Pulse simulation of CeRAM cell . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

5.32 Circuit schematic representation of CeRAM memory array in standard and com-

mon source 1T1R configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 80

5.33 simulation input stimulus for simulation 4x4 array in 1T1R circuit configuration 80

5.34 Simulation output for 4x4 array in 1T1R circuit configuration . . . . . . . . . . 81

5.35 Schematic representation of the CeRAM I-V device model. . . . . . . . . . . . 82

5.36 Thermionic emission, Poole-Frenkel, and square root dependent plots of exper-

imental data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

5.37 Conductive state current of a CeRAM element vs. applied bias. . . . . . . . . . 88

5.38 CeRAM Device model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

5.39 Modeled and Experimental J-V characteristics for CeRAM . . . . . . . . . . . 89

Chapter 1

Introduction

Over the past 10 years, significant advancements have been made in the development

and research of devices based on resistance change in an effort to meet the requirements of

high density standalone memory for future technologies. Due to the potential benefits of these

devices from their simple operation, promising scaling potential, CMOS compatibility and

ultra high density arrays through the use of 3D architectures[1],[2] these devices have received

notable consideration from the research community.

Although more recent research has come a long way toward it’s application, the obser-

vation of thin films of metal-oxide materials undergoing a transition from an insulator to a

conductive state dates back more than 50 years. The first reports of this resistive switching

behavior were published in the 1960s and 70s [3, 4, 5, 6]. The phenomenon dates back even

further when considering the bulk material metal-insulator transition observations by Mott

1949 [7].

Resistance switching properties have been observed in a variety of materials [8, 9, 10, 11,

12, 13, 14, 15] for the last decade. The focus of this research was centered around NiO primarily

for it’s ease of integration due to the industry trend of using nickel silicide contacts in 65nm and

below technology nodes. For the realization of resistive memories often referred to as Resistive

Random Access Memories (RRAMs), two issues continue to delay their commercialization.

Firstly, high current in the conductive state and secondly, the high electroforming voltages

that produce random filaments across nanoscale thin films of these materials.

2

The starting point to force the charge transfer transition to be the dominant device

physics is to control the NiO stoichiometry with Ni(CO)4 (i.e., Nickel Carbonyl doping). Car-

bonyl complexes stabilize the oxygen vacancies resulting in a pure Mott (CT) transition system.

Thus, as the Metal-Insulator Transition (MIT) is exploited from the strong electron-electron

correlation formed in Mott insulators; the physics of CeRAM departs considerably from that

of RRAMs. Furthermore, RRAMs have thus far fallen into a device paradigm that depends

on the formation of “filaments,” i.e., metallic pathways that can be connected/disconnected

via an electrochemical process near the anode. In this work, a novel approach which uses the

Mott-like charge transfer (CT) properties of NiO is pursued.

As described above, CeRAMs are resistive random access memories that are based on

a Mott-like charge transfer metal-insulator transition in NiO, a well known TMO. Due to the

large area/thickness ratio, a large number of defects plague the stoichiometric balance. To

compensate for these defects, the Ni(CO)4 was developed.

It is well known that strong electron correlations exist in the bulk phase of such materials

as described by Mott and Hubbard [7], [16]. In the case of ultra thin films, compensation of

charge effects in the large surface to volume ratio is needed to achieve an electroforming free

device. In our case a large change in the device resistance between “On” and “Off” states

occurs. An appropriately configured device exhibits hysteresis and non-volatile characteristics,

for which stable memory switching can be controlled. Such stable systems based only on d-

orbital electron correlation and not charge trapping are central to the CeRAM concept, i.e.

absent of electroforming and defect compensation to isolate the Mott quantum phase transition.

Earlier work in this area is shown in refs. [17] and [18] respectively.

1.1 Non-volatile Memories

Non-volatile memory defines a class of computer memories that is able to maintain stored

data in the interruption or continued absence of a supplied power. Non-volatile memory,

like all traditional semiconductor memories, falls into one of four memory classifications or a

3

combination of two or more of them. These types of memories are described below:

I Random Access Memory (RAM)

which can be accessed very quickly and at any random memory location and contain sub-

classes of memories such as Dynamic RAM (DRAM), Static RAM (SRAM), and certain

types of read only memory (ROM).

II Sequential Access Memory (SAM)

in which memory cells are addressed and accessed in chronological order and the access

times are highly dependent on the address of the accessed memory cell. Modern technology

examples of SAM devices include magnetic memory such as hard disks and tape drives

and optical memories like CD-ROM’s.

III Content Addressable Memory (CAM)

in which memory cells are addressed and accessed by searching for specific data and

return the address(es) of that data. Access times are very fast, but the applications of

such a memory are limited and are typically used in microprocessors for cache memory

applications.

IV Read Only Memory (ROM)

which can either not be modified once initially written or can be modified slowly and with

some level of difficulty. Although most forms of ROM are considered randomly accessible

and therefore fall under the RAM classification, it is important to note that that ROM

memories are alternatively grouped by their ability or inability to be written and re-written

as opposed to their accessibility.

1.1.1 Floating Gate and Charge Trap Memories

Memories based on floating gate technology (FG) with charge trapping such as FLASH

are currently the leading edge for mass storage application. At present, NAND FLASH is the

state of the art in the Electrically Erasable Programmable Read-Only Memory (EEPROM)

4

class of memories due to its memory cell being smaller than conventional EEPROMs; this is

accomplished by eliminating the pasgate transistor of the conventional EEPROM cell. The

downside of this scheme is that even though they are state of the art at current 5V and

even 3.3V silicon logic levels, as the nodes shrink and the standard levels inevitably decrease

to 1.1V and even 0.5V over the next several years FLASH memories, which are based on

Fowler-Nordheim tunneling, will no longer function reliably. One fundamental cause for this

loss in reliability is simply due to the fact that as the technology node and thus the physical

dimensions of the FG decrease, the total number of electrons stored in that FG gets smaller

and smaller. Retention requirements must account for the loss of a few electrons each year

decreasing total data storage retention time and further, it is important that sufficient trapped

charge in the FG to ensure that small defects or even a single defect will not cause all charge

in the gate to be lost.

The best known FG technology is NAND FLASH in the form of a USB flash drive,

SD memory cards, and solid state drives. NAND flash presented huge advancements over

the existing technologies used for portable storage devices (think floppy disks and zip drives)

which is why it was such a disruptive technology. When compared to the alternatives, NAND

flash has faster erase and write times and a smaller cell area on chip allowing for more densely

packed arrays and thus larger data storage per unit area. However, FLASH memories have

several inadequacies that would make it a poor candidate for the future desire of a so called

universal memory.

• Slow erase and write times: NAND FLASH has programming speed on the order of a

couple milliseconds per 128KB block which is exceptionally slow when compared to,

lets say, SRAM which has programming speeds on the order of nanoseconds.

• Low programming endurance: The typical NAND flash can be written/re-written on

the order of 106 times which is insufficient for applications such as cache memory and

computer main memory which can be written and re-written many times per second

5

and also have fewer writing cycles and smaller storage density than state of the art

hard disk drives (HDD’s). Even more drastically, gigabyte class FLASH would have

much less endurance and the number of electrons in the gate is smaller.

• High voltage requirements: NAND FLASH requires higher voltage than the standard

chip supply voltage to erase the cell. To achieve the high voltages it is necessary to

provide multiple supply voltages which is typically not necessary, or include charge

pump circuits in the chip design which are big and use up valuable real-estate on the

silicon.

1.1.2 Ferroelectric Memories

Ferroelectric memories are based on the two stable electronic polarization states of fer-

roelectric material to store non-volatile data.[19] The ferroelectric memory element closely

resembles that of a conventional Metal-Insulator-Metal (MIM) capacitor where the insulator

portion that would typically be comprised of some sort of dielectric material which is replaced

with a ferroelectric material which is typically configured in a perovskite (ABO3) lattice struc-

ture. The memory architecture of a Ferroelectric Random Access Memory (FeRAM) is very

similar to that of a 2 transistor Dynamic Random Access Memory (DRAM) except that it is

truly random access and non-volatile as opposed to modern DRAM chips which are volatile

and data is read in bursts.

The operating principle of an FeRAM is that the B cation in the ABO3 perovskite

structure can occupy two stable positions in the lattice (Fig: 1.1). These lattice configurations

are referred to as polarization states, and when the B cation moves up in the lattice it is

considered to be in positive polarization or data “1”, alternatively when the B cation moves

down in the lattice it is considered negative polarization or data “0”[20]. The polarization

states of the Ferroelectric memory can be easily controlled by applying an external field across

the storage element. The macroscopic electrical behavior of the ferroelectric memory cell is

6

(a) (b)

Figure 1.1: Crystal structure unit cell of a cubic perovskite (ABO3) Ferroelectric material in(a) positive polarization state or Data “1” (b) negative polarization state or Data “0”.

represented in figure 1.2 as a polarization vs. voltage hysteresis loop. Remnant polarization

represents the level of stored charge in the cell when no external bias is present. For all intents

and purposes, a cell with a stored confrontational charge in the Pr position would correspond to

a logical “1” and similarly, stored charge in the P−r position would correspond to a logical “0”.

Coercive field (VC/thickness) corresponds to the threshold level of field that must be overcome

in order for the ferroelectric memory cell to change polarization states. Polarization states are

direction dependent and the storing mechanism depends on the B-O dipole configuration and

not trapped charge. Thus, in most cases, FeRAMS are destructively read as the opposing

polarization is needed to de-polarize (reverse) the dipole configuration.

Though the operating principle is the same for cubic perovskite based FeRAM’s such as

Pb[ZrTi]O3, it was not until the discovery of layered perovskites, such as SrBi2Ta2O9 (SBT),

that significant advancements in ferroelectric memories were made. Ferroelectric memories

based on SBT exhibit excellent retention characteristics, low leakage currents, and show nearly

fatigue free behavior beyond 1012 cycles [21]. However, Pb[ZrTi]O3 based memories have also

7

Figure 1.2: Typical ferroelectric Polarization vs. voltage hysteresis loop.Pr is remnant polarization and Vc is coercive voltage.

improved due to IrOx electrodes.

FeRAM technology has seen a long and fruitful existence with commercial applications

in smartcards and electronic metering to name a few. The primary advantage of FeRAM is

its low power consumption and stable nonvolatility. However, FeRAM has had significant dif-

ficulties breaking into large scale commercialization due to difficult process integration caused

by the high temperature requirements of crystallizing the ferroelectric materials. Addition-

ally, FeRAM has not been proven capable of accommodating high density applications in the

shrinking CMOS technology nodes.

1.1.3 Resistive Memories

Resistive memories are a class of memory that store a bit based on the resistance state of

the storage material. Resistive memories, as I have described them, are a broad classification

8

and therefor contain several emerging memory technologies such as Phase Change Memory

(PCM) which undergoes a structural phase change between the amorphous and crystalline

phase typically due to Joule heating.

Magnetoresistive Random-Access Memories (MRAMs) are devices in which the magnetic

state in one of two ferromagnetic plates separated by an insulating material can be switched.

In its current embodiment, the spin-torque transfer across the insulating barrier controls the

resistance. And, as described before, RRAMs for which the actual switching mechanism is

still not well understood, have an immense body of research in industrial laboratories and

academia.

Many materials have demonstrated resistive switching behavior resulting from elec-

tric field including binary transition metal oxides, complex transition metal oxides, such as

perovskites, paraelectric and magnetic perovskites, high-k dielectric materials, phase change

chalcogenides, and various organic and molecular compounds.

The primary appeal of RRAMs is their simplicity, scalability, ultra fast switching times,

and ease of integration into current and next generation semiconductor technology scaling

nodes. The memory cell can ideally be as simple as an MIM device sandwiched between

perpendicular metal lines essentially creating a cross-point array, or in a conventional 1T1R

type configuration in which the MIM capacitor structure serves as the storage element and the

Metal-Oxide-Semiconductor (MOS) transistor provides isolation from other elements in the

memory array as well as taking on a integral roll in the programing of the memory element by

limiting the current flow across such element.

Thus, resistive memories represent the most promising candidates thus far to fulfill the

requirements for a universal memory that would combine the cost benefits of DRAM and the

speed of an SRAM with the non-volatility of a FLASH memory.

9

1.2 Scope of Thesis

This thesis describes fundamental fabrication and characterization of a novel resistive

random access memory in which the Mott insulator transition common in TMOs is solely the

metal/insulator switching mechanism. Though CeRAM falls under the blanket category of

resistive RAMs, the underlying physics that control the memory function give CeRAM dis-

tinction from other resistive RAM’s, and it is the understanding of these underlying physical

mechanisms that have given this research a potential advantage in the pursuit of commercial-

izing this technology.

Chapter 2 contains a literature review of current resistive based memory technologies

including materials properties and a comprehensive comparison of the device performance

metrics which have been reported in the literature as of the date of this work. The conventional

filamentary mechanisms believed to be responsible for memory behavior in these materials

and devices is also covered in this chapter as well as the challenges already experienced and

facing RRAM development. Integration issues related to the materials as well as electrical and

reliability issues are all addressed in this section.

In chapter 3 a comprehensive review of the physical science necessary to the understand-

ing of CeRAM device performance is presented.

Once the background has been established the CeRAM technology can be thoroughly

presented in chapters 4 and 5 . Here, the concept behind the CeRAM development program

is established. In chapter 4 the fabrication process for proof of concept structures is presented

and the characterization and analysis techniques along with a review of compelling results

supporting CeRAM are discussed. In chapter 5 the device model of the CeRAM storage cell

is summarized, and a review of its capabilities to describe the CeRAM “diode” is included.

Finally, in chapter 6, conclusions and recommendations for future work are presented.

Appendices A and B show derivations of model equations and MATLAB codes for simula-

tion.

Chapter 2

Review of The Current Status of Resistive Memory Technology

Resistive switching based memories can be can be distinguished by their physical mecha-

nism which drives the resistive switching behavior. Throughout most of the literature, the resis-

tive switching is driven by Thermal, electronic, magnetic, and ionic effects.[22] These switching

mechanisms account for the vast majority of memory technologies structured around resistive

switching. Phase Change Memories (PCM) undergo a resistive change based on a physical

phase change from crystalline to amorphous and vice versa. This is induced by thermally

pulsing a phase change material with a resistive heating element. The resistive switching of

Conductive Bridge Memories (CBM) is based on ionic migration through a specific medium

such as metallic ions migrating through a solid-state electrolyte material to form a conductive

bridge through which current can flow easily. Resistive switching mechanisms categorized as

magnetic effects are the basis for spin-torque or Spin Transfer Torque (STT) where spin polar-

ized current is used to flip the magnetic polarization of a magnetic material. Though generally

outside the scope of this thesis, an excellent primer on STT materials and technologies can

be found in Ralph and Stiles [23]. Resistive switching memories based on electronic effects

such as those seen in binary metal oxides comprise the largest material set investigated in the

literature and this chapter.

Resistive random access memory, typically referred to in the literature as RRAM or

ReRAM such as those reviewed in these articles[24, 25, 26] as described in chapter 1, fall into

the “filamentary memory” paradigm. Thus, in order to become a resistive switch, the material

11

in the MIM sandwich has to be electroformed - that is, a process to create metal rich filaments

probably along the grain boundaries. The focus of this chapter is to summarize the latest

developments of resistive memory devices based solely in the filament paradigm. We start,

however with a broader review of other RRAMs and the materials used to derive them.

2.1 Material Properties and Device Performance

Many materials have been considered for use in resistive memories both organic and

inorganic. These materials have shown thermal and ionic resistive switching throughout the

literature and typically fall under several categories such as chalcogenides for PCM’s, binary

metal oxides, perovskites, solid-state electrolytes, and various organic and molecular systems.

Table 2.1 lists a representative sampling of devices and materials from the literature with

several of the more meaningful performance metrics. The data highlighted in RED represents

the best reported performance as of the time of this literature review.

2.1.1 Chalcogenides

Chalcogenide glasses, such as GeSbTeSe and AgInSbSeTe, have been investigated for

use in phase change memories. In these materials, the chalcogenide material can be switched

from the crystalline phase to the amorphous phase by heating the chalcogenide with a resistive

heater at one electrode.

There are several challenges plaguing the commercial integration of PCM’s. First, the

large current densities necessary to produce the necessary internal temperature of the storage

mechanism for a given technology node exceeds the capabilities of the standard processes. This

means that either the active switching region needs to be smaller than the transistor gate length

which can potentially be smaller than the typical resolution of the lithography. Second, and

most fundamentally to the switching mechanism itself, is the fact that a phase-change, that

is essentially thermally induced physical change in the crystalline structure of the switching

element, has the potential to cause the resistance of the material to drift over time as defects

12

are created and thus the threshold voltage used to sense the state of the active element must

also drift. An excellent review of the status of phase change memory can be found in Wong

et al. [27].

2.1.2 Binary Metal Oxides

Binary metal oxides represents the most promising and appropriately the most widely

studied group of resistive switching materials.[8, 13, 28, 29, 30, 31, 32] The vast majority of

these materials are based on oxides of transition metals due to their ability to undergo Mott

metal-insulator and charge transfer transition as a result their incomplete d-shells. The Binary

metal oxides are favored in many of these studies because of the advantage of integrating well

with current CMOS technology and the fact that scaling properties appear to fall within the

range of future CMOS scaling power capabilities. Because of their favor, a vast amount of

data has been collected for resistive memories based on Binary metal oxides, and the data is

quite promising for different material systems for different reasons. For instance, of the data

reported in table 2.1, these materials systems account for the majority of the best reported

data in the literature. Most of these materials demonstrate a unipolar or non-polar switching

behavior meaning they can be programmed using only positive biases or by using positive and

negative biases if the desired architecture should require making them a more versatile choice

than some other materials. Much more on the transition mechanism’s of these materials will

be covered in subsequent chapters of this thesis.

2.1.3 Perovskites

Perovskite materials, like SrTiO3 (STO), SrZrO3 as well as more complex structures like

the colossal magnetoresistive manganites Pr1-xCaxMnO3 (PCMO), La0.7Sr0.3MnO3 (LSMO),

and cuprate superconductors YBCO, and BSCCO [33], have been observed to exhibit bipolar

resistive switching behavior. PCMO films were first reported by researchers at Sharp Labora-

tories [34] to undergo a resistance change induced by electronic pulse and actually represents

13

the first reported RRAM device, although the phenomenon was observed much earlier than

this reporting. These materials have not been a focus of this research for the same reason

that ferroelectric memories are not likely candidates for sub-nm technologies because they are

more difficult to integrate into existing CMOS processes and dont have the supporting scaling

evidence to show they will meet the small size and low power requirements of future CMOS

devices.

2.1.4 Solid-State Electrolytes

Materials such as AgGeS and AgGeSe [35] have been studied for Conductive Bridge

Random Access Memories (CBRAM) in which the solid electrolyte is sandwiched between

an inert cathode and an anion rich anode. For the example of Ag-Ge-Se solid electrolyte,

when the stack structure is biased positively the Ag anions from the anode migrate through

the electrolyte creating a metallic bridge between the anode and cathode where current can

flow more freely. Reversing the bias the anions migrate back into the metal anode and the

conductive pathway is broken.

2.1.5 Organic and Molecular Systems

Organic materials have received much attention for their mechanical flexibility, light

weight, and low cost properties. These organic RRAMs use a polymer material as the active

or switching material sandwiched between two metal electrodes. Recently, it has been shown

that extremely low reset currents of ∼ 20nA can be achieved while maintaining excellent data

retention using a parylene-C based device[36].

Molecular systems are not necessarily mutually exclusive of other materials systems used

for RRAM devices; however, RRAM devices are a specific subset in which storage capacitors

are created using some structure containing monolayers of molecular materials as the stor-

age element typically sandwiched between metals and semiconductor grade materials.[37, 38].

These materials, though they could potentially meet all of the scaling requirements of next

14

generation MOS technology, still have a long way to go to prove that they exhibit the neces-

sary robustness to meet the stability, endurance, and performance metrics necessary to be a

disruptive force in the memory market.

2.2 Mechanism for Switching

The Mechanism responsible for the resistive switching behavior of RRAM devices, though

still largely debated and not fully understood, typically falls under two general classifications:

Filamentary conduction and interface type switching. The models used to represent these

classifications, however are not as few and contain such concepts as oxidation-reduction reaction

[29], random circuit breaker model [51], an electric faucet model [52], thermal dissolution [53],

and Mott transitions. The one thing that most of these switching mechanisms seem to have

in common is that the change in conductivity is highly localized in so called “filaments” that

create conduction paths between the two electrodes and that these filaments are not native

to the virgin state of the material but are created during an electroforming step in which a

higher power density than is required for switching is applied to the active element. Once the

filaments have been created, they can be dislocated from the electrodes and repaired and so

on by applying specific biases across the material which is dependent on the materials system.

In a bi-polar device, the material is positively biased in order to repair the filament

conductors and a negative bias is used to dislocate those filaments.

In a unipolar or non-polar system, the switching mechanism is more charge density

driven and a higher bias is used to connect the filaments between the electrodes but with the

same bias polarity at a lower amplitude the conductive filaments can be broken moving the

switching element back in the insulating state.

Additionally, with the silver bridge CBRAM we have the ion migration mechanism in

which positively charged anions move through an electrolyte to form conductive pathways

between the anode and cathode of the active device.

15

Table 2.1: A representative list of material systems used in RRAM devices and their charac-teristics arranged by year of publication. NS represents values that are “not specified” in theliterature

SwitchingMate-rial

BEMaterial

TEMaterial

CellArea(µm2)

Current Voltage Speed HRS/LRSRatio

Endurance Retention Year Ref

Sr(Zr)TiO3 Ti/Pt Ti/Pt 0.01 1.4mA ≤ 1 V 1 mS >2.5 500 24h @25 C

2001 [39]

PCMO Pt Pt 7854 200µA ≤ 5 V 20 ns 10X -1000X

120 >200C

2002 [34]

NiO NobleMetal

NobleMetal

0.2 2mA <3 V 5µ s >10 106 300h @150 C

2004 [8]

AgGeSe Ni Ag 0.001256 12µA <1.5 V 100 ns >1000 3.2x1010 NS 2005 [35]

CuxO Cu Ti/ TiN 0.03 45µA <3 V 50 ns >10 600 30h @90C

2005 [28]

Ti:NiO Pt Pt 0.25 100µA <3 V 5 ns >90 100 1000h @150 C

2007 [40]

FeOx Pt Pt .18-18 5mA <3 V 10 - 100 ns >10 3x104 1000h @85 C

2007 [13]

NiO SrRuO3 Pt 90 20mA <5 V DC >5 200 3000s @25 C

2007 [41]

TaOx Pt Pt 0.49 170µA <2 V 10 ns >10 109 3000h @150 C

2008 [29]

Ti/HfOx

TiN TiN 0.1 25µA <1.5 V 5 ns >10 106 10h @200 C

2008 [42]

MgO CoFeB CoFeB .1x.2 5mA <2 V DC >10 400 88h @85C

2008 [30]

NiO Pt Pt 0.49 20µA <2.5 V 100 ns >1000 100 1000h @150 C

2008 [43]

ZnO ITO ITO 196350 20mA <3.2 V DC >100 100 105s @25 C

2008 [31]

Ti/HfOx

TiN TiN 0.0009 200µA <2.5 V 0.3 ns >100 1010 28h @150 C

2009 [44]

MnO2 Pt Ti 11310 30mA ≤ 1 V 10 ms >10 105 104s @80C

2009 [45]

ZnO ITO/Ag/ITO

ITO NS 3mA <3.4 V DC >10 200 104s @85C

2009 [46]

WOx W TiN 0.0036 1mA <3 V 50 ns >10 106 2000h @150 C

2010 [32]

ZrOx/HfOx

TiN Pt 0.0025 50µA <2 V 40 ns >10 106 28h @125 C

2010 [47]

N:AlOx Al Al 1 50nA <2 V NS >100 105 28h @125 C

2011 [48]

TaOx/Ta2O5

Pt Pt 9000 30µA <2.5 V 10 ns >100 1012 3h @200C

2011 [49]

Hf/HfOx

TiN TiN 0.0001 50µA <1.5 V 10 ns >10 5x107 30h @250 C

2011 [50]

16

2.3 Challenges of RRAM Development

There are several challenges in the development of RRAM devices that need to be over-

come in order for the main market drivers to put these materials into production. I would say

first and foremost that cell performance metrics need to significantly exceed those of current

high density flash memory technologies. It is known and accepted that flash memories will fail

to perform as technology nodes scale, but right now they are a safe technology. But, going

deeper than the competitiveness of the technology, there are materials and reliability concerns

that need to be addressed before the technology can really take off.

2.3.1 Materials Issues of Resistive Memories

One of the first and most fundamental concerns with any new technology development is

the compatibility of the process materials necessary for that new development with materials

used in any underlying manufacturing process that would be needed to realize the new tech-

nology. For RRAM development to be realized, any material used in the storage element must

be compatible with materials and processes of current and next generation semiconductor fab-

rication technology. The development of resistive memories, especially in the academic world,

has examined a large range of materials as was evidenced in table 2.1, some of which can be

risky when introduced in a semiconductor fabrication facility. An example of these materials

can be seen in in the color coded periodic table of elements Figure 2.1, the elements highlighted

in green in particular are materials that have been studied for resistive memory development

but are not widely present if at all in current CMOS processes. Only those resistive memory

elements comprised of materials highlighted in magenta present the simplest integration with

CMOS because they are already compatible with most fab processes. In order to utilize many

of these materials they would need to be strictly isolated from front end of line processes (e.g.

Au,Pt,Cu) because of their known detrimental effects to CMOS flows, while with others, their

potential effects are simply too unknown to risk contamination of process flows used in other

17

established product lines. There are also some back end of line (post CMOS) contamination

concerns due to the fact that in many fabrication facilities there is processing equipment that

is not strictly limited to front end of line such as lithography steppers and certain etchers. Any

resistive memory that would be added integrated into an existing technology flow should be

consisting of those materials which are not foreign to the fabrication facility.

2.3.2 Reliability Issues

The primary failure mechanism for RRAM devices, including CeRAM devices, which

are the focus of this thesis, is that during write/re-write cycling the memory cell becomes irre-

versibly stuck in the LRS. However, as it will be described later, whilst this failure mechanism

is certainly defect driven in CeRAMs, doping control can be used to optimize the device. In

the case of filamentary RRAMs, doping control of the conductive filaments is unfortunately

not a viable solution.

Scalability is also a critical factor when considering a device for future technology where

memory cells must be able to reliably switch at nanometer device dimensions in order to meet

with the form factor requirements of future technologies. Scalability becomes an issue with

RRAM devices partially due to the mechanism which is attributed to the switching behavior

of the bulk of the devices presented in the literature. If the switching mechanism is considered

to be a random matrix of conductive filaments, which is largely agreed upon, the performance

of these resistive switching structures will very likely be quite different when the entire device

geometry shrinks down to a size smaller than that of a single conductive filament. Since it

has been shown that the maximum on state current of RRAM devices which occurs at the

onset of a RESET is dependent on the compliance current, i.e. the current allowed to flow

through the active region during a SET, and not the device dimensions themselves. There is

some concern that at a certain point in the dimensional scaling process the currents will cease

to decrease with area and create current requirements higher than the technology will allow.

Additionally, it is possible with this mechanism for the dimensions of the active cell to simply

18

1 1.0079

H

Hydrogen

3 6.941

Li

Lithium

11 22.990

Na

Sodium

19 39.098

K

Potassium

37 85.468

Rb

Rubidium

55 132.91

Cs

Caesium

87 223

Fr

Francium

4 9.0122

Be

Beryllium

12 24.305

Mg

Magnesium

20 40.078

Ca

Calcium

38 87.62

Sr

Strontium

56 137.33

Ba

Barium

88 226

Ra

Radium

21 44.956

Sc

Scandium

39 88.906

Y

Yttrium

57-71

La-Lu

Lanthanide

89-103

Ac-Lr

Actinide

22 47.867

Ti

Titanium

40 91.224

Zr

Zirconium

72 178.49

Hf

Halfnium

104 261

Rutherfordium

23 50.942

V

Vanadium

41 92.906

Nb

Niobium

73 180.95

Ta

Tantalum

105 262

Dubnium

24 51.996

Cr

Chromium

42 95.94

Mo

Molybdenum

74 183.84

W

Tungsten

106 266

Seaborgium

25 54.938

Mn

Manganese

43 96

Tc

Technetium

75 186.21

Re

Rhenium

107 264

Bohrium

26 55.845

Fe

Iron

44 101.07

Ru

Ruthenium

76 190.23

Os

Osmium

108 277

Hassium

27 58.933

Co

Cobalt

45 102.91

Rh

Rhodium

77 192.22

Ir

Iridium

109 268

Meitnerium

28 58.693

Ni

Nickel

46 106.42

Pd

Palladium

78 195.08

Pt

Platinum

110 281

Darmstadtium

29 63.546

Cu

Copper

47 107.87

Ag

Silver

79 196.97

Au

Gold

111 280

Roentgenium

30 65.39

Zn

Zinc

48 112.41

Cd

Cadmium

80 200.59

Hg

Mercury

112 285

Ununbium

31 69.723

Ga

Gallium

13 26.982

Al

Aluminium

5 10.811

B

Boron

49 114.82

In

Indium

81 204.38

Tl

Thallium

113 284

Ununtrium

6 12.011

C

Carbon

14 28.086

Si

Silicon

32 72.64

Ge

Germanium

50 118.71

Sn

Tin

82 207.2

Pb

Lead

114 289

Ununquadium

7 14.007

N

Nitrogen

15 30.974

P

Phosphorus

33 74.922

As

Arsenic

51 121.76

Sb

Antimony

83 208.98

Bi

Bismuth

115 288

Ununpentium

8 15.999

O

Oxygen

16 32.065

S

Sulphur

34 78.96

Se

Selenium

52 127.6

Te

Tellurium

84 209

Po

Polonium

116 293

Ununhexium

9 18.998

F

Flourine

17 35.453

Cl

Chlorine

35 79.904

Br

Bromine

53 126.9

I

Iodine

85 210

At

Astatine

117 292

Ununseptium

10 20.180

Ne

Neon

2 4.0025

He

Helium

18 39.948

Ar

Argon

36 83.8

Kr

Krypton

54 131.29

Xe

Xenon

86 222

Rn

Radon

118 294

Ununoctium

1

2

3

4

5

6

7

1 IA

2 IIA

3 IIIA 4 IVB 5 VB 6 VIB 7 VIIB 8 VIIIB 9 VIIIB 10 VIIIB 11 IB 12 IIB

13 IIIA 14 IVA 15 VA 16 VIA 17 VIIA

18 VIIIA

57 138.91

La

Lanthanum

58 140.12

Ce

Cerium

59 140.91

Pr

Praseodymium

60 144.24

Nd

Neodymium

61 145

Pm

Promethium

62 150.36

Sm

Samarium

63 151.96

Eu

Europium

64 157.25

Gd

Gadolinium

65 158.93

Tb

Terbium

66 162.50

Dy

Dysprosium

67 164.93

Ho

Holmium

68 167.26

Er

Erbium

69 168.93

Tm

Thulium

70 173.04

Yb

Ytterbium

71 174.97

Lu

Lutetium

89 227

Ac

Actinium

90 232.04

Th

Thorium

91 231.04

Pa

Protactinium

92 238.03

U

Uranium

93 237

Neptunium

94 244

Plutonium

95 243

Americium

96 247

Curium

97 247

Berkelium

98 251

Californium

99 252

Einsteinium

100 257

Fermium

101 258

Mendelevium

102 259

Nobelium

103 262

Lawrencium

Materials reported in RRAM literature

RRAM Materials in current fab processes

Z mass

Symbol

Name

Periodic Table of Chemical Elements

Figure 2.1: Table with highlighted materials used for RRAM devices in the literature

19

be smaller than would be necessary for a filament to form and the memory action of those

devices would no longer exist. Fortunately for CeRAM devices, though the RESET current

does scale with compliance, we have been able to demonstrate that the processing techniques

used for precisely controlling the material properties allow for the scaling of off state diode

current which drives the compliance requirements thereby allowing us to tune the compliance

requirements as a function of area. More on this later.

Electroforming requirements of the filament driven devices will also create issues due

to the high voltage and current requirements in the initial conditioning phase of the memory

element. Essentially what is happening here is that in order to create conductive filaments in

the material capable of being switched between the resistive and conductive states, a larger

voltage must first be applied to the anode (top electrode) of the device causing many conductive

filaments (often agreed upon to be oxygen vacancies in the grain boundaries of the semi-

amorphous material) to be created at the cathode (bottom electrode) eventually building

a complete path all the way to the top electrode. Once the filaments have been created the

switching mechanism is concentrated near the anode where the filament density is the smallest,

and the filaments can be destroyer by thermal breakdown in the case of unipolar switching

and potentially thermally assisted electron migration in bipolar switching devices.

Chapter 3

Electronic Phase Transitions in Correlated Systems

The goal of this chapter is to provide the necessary background information to build

an understanding of the underlying mechanisms of metal-insulator transitions (MITs). As it

is well known (Imada et al. [54]) electron density variations are responsible for the MIT and

its reversal. It is central to the CeRAM storage cell that electron tunneling and electron-hole

recombination induce these density variations and are responsible for the switching between

metal and insulator behavior observed in CeRAMs. It is thus implicit in the basic physics

of Mott-like MITs, that the Wigner-Seitz density parameter, Rs and the ensuing electron

screening length are first order parameters in controlling the electron-electron interaction.

Starting with a review of Hubbard-Mott theory, this chapter covers the physics of the

infinitely narrow Hubbard Hamiltonian and it’s application to quantum transport in CeRAMs.

3.1 Non-Interacting Electrons

Let us consider a simple system in which the Schrodinger equation represents the transfer

function. The most general form of the transfer function takes the form:

HΨ = i~∂Ψ

∂t(3.1)

where Ψ is the wave function and H is a Hamiltonian operator which represents the total

energy of the system for a given wave function. For a single particle non-interacting system

21

the Schrodinger equation becomes:

− ~2

2m

d2Ψ

dx2+ V (x)Ψ = EΨ = i~

∂Ψ∗

∂t. (3.2)

Multiplying both sides by the complex conjugate of the wave function yields

d2Ψ∗Ψ

dx2+Ψ∗V (x)Ψ = EΨ∗Ψ. (3.3)

By combining 3.2 and 3.3 the single particle current in an open boundary (device) is given by

∇ · J = −∂ρ

∂t. (3.4)

To illustrate the non-interactive electron current we start with a fundimental continuity equa-

tion

dJ

dx= −∂ρ

∂t(3.5)

where,

ρ = Ψ∗Ψ (3.6)

and re-write Schrodinger’s equations as

− ~2

2m

d2ρ

dx2+Ψ∗V (x)Ψ = i~

∂ρ

∂t(3.7a)

− ~2

2m

d2ρ

dx2+ΨV (x)Ψ∗ = i~

∂ρ

∂t(3.7b)

combining these two equations together yields

− ~2

2m

(

2d2Ψ

dx2

)

+ (Ψ∗V (x)Ψ−ΨV ∗(x)Ψ∗) = 2i~∂ρ

∂t. (3.8)

If V (x) = V ∗(x) then

− ~2

2m

(

Ψ∗ d2

dx2Ψ−Ψ

d2

dx2Ψ∗

)

+ V (x) (Ψ∗Ψ−ΨΨ∗) = 2i~∂ρ

∂t(3.9)

and since we know that Ψ∗Ψ = ΨΨ∗

− ~

i4m

(

Ψ∗ d2

dx2Ψ−Ψ

d2

dx2Ψ∗

)

=∂ρ

∂t(3.10)

22

which can be re-written as:

− ~

i4m

(

Ψ∗ d

dx

dΨ

dx−Ψ

d

dx

dΨ∗

dx

)

=∂ρ

∂t(3.11)

giving the equation for current by using the continuity equation from before as:

J = − ~

i4m(Ψ∗∇Ψ−Ψ∇Ψ∗) . (3.12)

At the mesoscopic scale, where the device dimensions (thickness) are of the order of the

electron coherent wave length, single particle currents can be generalized in a many body prob-

lem fermion field. As this will be the key to show the MIT in current-voltage characteristics,

the concept of a single non-interactive particle is readily seen in equation 3.12.

For the Many Body description, fermion field operators are necessary and they immedi-

ately need second quantization. this is briefly described below starting with,

Ψ(x) =∑

ciφi(x)

Ψ∗(x) =∑

c†iφ∗i (x)

Ψ∗Ψ =∑

c†ici

where ci and c†i are the annihilation and creation operators and φi(x), φ∗i (x) are the

fermion field operators.

As will be shown later, the current in mesoscopic devices is derived from:

i~q∂N

∂t=[

N ,H]

(3.13)

where

N =∑

k

c†kck (3.14)

which is the two particle operator and nk = c†kck is the electron density in the k-th state of the

band dispersion (E(k)).

23

As described above, the density parameter Rs, indicates how the density of free or nearly

free electrons screen the ion and core electrons. It is well known (Kittel [55]) that the volume

per free electron is

4

3π(RsaB)

3 =1

n(3.15)

and that R = Rsab which is nearly the lattice spacing, describes a metal like material (Rs = 1),

which Mott used to describe the insulator to metal transition to be

aBn1/3c

∼= 0.26. (3.16)

Thus, at the critical electron concentration (nc) a Mott insulator (or charge transfer Mott

insulator) behaves like a metal with Rs as large as 6. An insulator is achieved when Rs is large

enough to completely eliminate wave function overlap. A more sophisticated understanding of

the Mott transitions is given below.

3.2 Mott Insulators and the Mott Transition

The Mott transition, or even more fundamentally, Mott insulators are materials that, by

traditional band theory, should behave like metals but are instead insulators. This breakdown

in band theory is due to the the fact that traditionally it is assumed that electrons do not

interact with one another, i.e. that electrons and are essentially independent particles floating

in an infinite and static potential.

In the student Solid State Physics texts, such view of electrons has a long history. First,

the very successful Drude model based on kinetic theory of gasses (Classical electron gas).

Later, Sommerfeld introduced the quantum expansion of the drude model to include the wave

properties of electrons. And finally, using Bloch electrons, Wilson developed band theory.

By 1937, De Boer and Verwey [56] pointed out that NiO did not follow band theory because

theoretically it should be a metal, and yet behaved as an insulator. Sir Nevile Mott, circa 1957

explained this anomaly as caused by a “disproportionation” reaction (d8+d8 → d7+d9) which

yielded a coulomb repulsion in the 3d8 shell of NiO. By 1963, Hubbard and others explained

24

this now called “Mott transition” from first principles. In 1977 Mott and Hubbard received

the Nobel Prize for their work.

3.3 The Hubbard Model

The Hubbard model is based on the well known tight binding approximation as its

starting point. The general form of the Hamiltonian is of the form

H = H0 + V (3.17)

where V is the potential energy of the system and the tight binding Hamiltonian H0 in second

quantization is,

H0 = −t∑

〈i,j〉,σ

c†i,σcj,σ (3.18)

where t is the hopping integral representing the energy for electrons to hop from one atom

to the next and c†i,σcj,σ is the creation and annihilation operators representing the number of

particles occupying each state. Hubbard considered the intrasite potential and the electron

localization via a repulsive Coulombic force. Thus, Hubbard introduced the on-site repulsion

term U which is a result of coulomb interaction between electrons on the same atomic orbital

and is sometimes simply referred to as the Hubbard-U . Now 3.17 representing the total energy

of the system with the kinetic Hamiltonian H0 and the local intrasite potential energy now

becomes.

H = −t∑

〈i,j〉,σ

c†i,σcj,σ + UN∑

i=1

ni↑ni↓ (3.19)

where

U = I − E. (3.20)

I is the energy required to remove an electron from the lattice, and E represents the energy

gained when free electrons are added to the lattice. For Ni

I = E3d8→3d7 (3.21)

E = E3d8→3d9 . (3.22)

25

If we consider transition metal oxide systems, and more specifically 3d transition metals such

as in the NiO compound investigated here where the conduction mechanism is the dispropor-

tionation reaction

dn + dn → dn+1 + dn−1 (3.23)

we can re-write equation 3.20 in the form

U = E(dn+1) + E(dn−1)− 2E(dn). (3.24)

There is now some competition between the hopping integral t and the on-site coulomb repul-

sion U which is able to explain metal-insulator transitions in strongly correlated materials.

The average value of coulomb potential between electrons in two different locations is

V (i, j; k, l) =

⟨

ij

∣

∣

∣

∣

e2

4πE0|r1 − r2|

∣

∣

∣

∣

kl

⟩

(3.25)

and the Hubbard U is then

U =

⟨

ii

∣

∣

∣

∣

e2

4πE0r

∣

∣

∣

∣

ii

⟩

= V (ii, ii). (3.26)

Figure 3.1 shows the local crystal field configuration of NiO. It can be readily seen

that the crystal field (made of local oxygen and nickel electric fields), splits the gas phase

degenerate nickel orbitals into two degenerate sets of levels. The 2p oxygen orbitals interact

with the upper Hubbard band to create the interaction between electrons that become the

reason for the disproportionation and subsequently metal/insulator transition.

According to Hund’s rule one would expect that each of the 5 sub-bands in the 3d shell

would contain a single electron before any of them would be occupied by a second. If this were

the case, the last two sub-bands would contain 1 electron each in the 3d7 and 3d9 positions

meaning the Fermi level in the ground state would be located at the last filled, or lowest

energy sub-band having room for an electron to doubly occupy that level and thus conduction

occurs. However, since NiO does not adhere to non-interacting band theory for which Hund’s

rule describes the band filling, this is not the case. As shown in 3.1, for the ground state

26

6 Dq

-4 Dq

t2g

eg

Ligand Field

Splitting

Ni 3d

dxy, dyz, dzx

dx -y , dz2 2 2

Hubbard

subbands

Figure 3.1: band diagram for NiO. Reprinted with permission from Xueet al. [18]. Copyright 2011, AIP Publishing LLC

of a 3d transition metal, the 3dn state which should be empty contains an electron leaving

the sub-band containing the 3dn+1 and 3dn+2 positions empty. This non-typical band filling

creates an on-site coulomb repulsion causing these sub-bands to split into an empty upper

Hubbard sub-band (UHB) [3dn+1 and 3dn+2] and a doubly occupied lower Hubbard sub-band

(LHB) [3dn−1 and 3dn]. The double occupancy at the 3dn level creates the repulsion that is

responsible for the gap U . More on this mechanism will be discussed later.

Nickel oxide however is in actuality a charge transfer type Mott insulator which is shown

in figure 3.3b as opposed to the Mott-Hubbard model described in figures 3.2 and 3.3a. Though

these two transition types are fundamentally different in the band representation, the transfer

mechanism is largely the same and the Mott transition type mechanism satisfies both condi-

tions. In the Mott-Hubbard type insulator, the metal to insulator transition occurs as a result

of an electron being transferred from the lower Hubbard band 3dn to the upper Hubbard band

27

Oxygen 2p band

LHB

UHB

EF

DOS(E)

E

Nickel 3d t2g

(a) Insulating state

Oxygen 2p band

EF

DOS(E)

E

Nickel 3d t2g

(b) Conducting state

Figure 3.2: Mott-Hubbard metal-insulator transition. (a) Normal band splitting into FullLHB and empty UHB representing a non conducting insulator. (b) Dotted line representscontinuous band created when some electron states are excited into the UHB resulting inmetallic conductive behavior.

3dn+1 overcoming the charge gap U created by the strong coulomb repulsion between intra-site

electrons. Similarly, for the charge transfer Mott insulator, the lowest filled energy level is from

the Oxygen 2p band instead of the transition metal 3d band and the charge transfer gap ∆ is

between 3dn ↔ 3dn+1L where L represents a hole in the oxygen valence band.[57] For charge

transfer insulators, the transition is a result of an electron being transferred from the Oxygen 2p

into the upper Hubbard band thus overcoming the charge gap (∆). Because the two MIT mech-

anisms are functionally the same, that is, the central point is the electron-electron interaction

energy (U), the Mott-Hubbard type is primarily used in this thesis. Linking of the discussion

28

Oxygen 2p band

LHB

UHB

EF

DOS(E)

E

Nickel 3d t2g

(a) Mott-Hubbard MIT

Oxygen 2p

band

UHB

EF

DOS(E)

E

(b) Charge Transfer MIT

Figure 3.3: Two band representations of the insulating state of NiO representing the groundstate of the metal insulator transition for (a)Mott-Hubbard metal insulator transition and (b)Charge transfer metal insulator transition are are shown.

pertaining to the density parameters, it should be pointed out that for H = KE + PE,

Rs ∝PE

KE∝ 1

n(3.27)

thus, as the density varies, the MIT/IMT switching occurs.

3.4 Green’s Functions

The purpose of using Green’s functions is that it provides a means for determining

the expectation values of correlated functions such as those we are presented with in our

device problem. Much of this section follows the work of Nolting and Brewer [58] though not

necessarily in the order in which it was presented. Let us begin this section by re-writing the

29

Many Body form of Schrodinger’s equation (3.1) using the Hubbard Hamiltonian from the

previous section and Green’s functions.

(

i~∂

∂t−Hs

)

G±(t) = 1δ(t) (3.28)

where G+ and G− are the advanced and retarded Green’s functions respectively.

G+(E) =1

E + iE −Hs(3.29)

G−(E) =1

E − iE −Hs(3.30)

and,

G±(E) =1

[G±0 (E)]− 1− Σ± (E)

=1

E ± iE −H0 − Σ± (E)(3.31)

where

G0 =1

E − E(k) or G0 =1

E − (E(k)− µ)

and Σ is the electron-electron interaction self-energy. Thus, the Green’s function for the “quasi-

particle” (electrons plus interaction) is given by,

G = G0 +GΣG0 (3.32)

and the interaction term Σ is:

Σασ∼= eV (ii, ii) ∼ eU (3.33)

or as it will be later seen

Σ = U 〈n−σ〉 f(U). (3.34)

Here,

f(U) =E + µ− T0

E + µ = U(1− 〈n−σ〉)− T0(3.35)

and 〈n−σ〉 is the occupation number and is either “0” or “1” depending on if there is

a second electron occupying the site or not; −σ means that the second electron obeys Pauli

30

principle - flipped spin. Multiplying through we get the self-energy in terms of the Green’s

function as:

Σ = G−10 −G−1. (3.36)

(1) DOS for Non-Interacting electrons

Now lets introduce the Density of States (DOS) function for non-interacting fermions. The

generalized density of states is given by:

ρ0(E) =1

N

∑

k

δ(E − E(k)). (3.37)

If we consider only a single particle, the DOS would be ρ′0(E) = δ(E − E(k)) where k is

a fixed single state in the band diagram. Since we are in fact dealing with more than one

state in the band and we assume the lattice potential is negligible, the energy dispersion

is given as usual for a Bloch electron,

E(k) = ~2k2

2m. (3.38)

From this, (see Appendix B) we can start with 3.37 and arrive at the well known derivation

of DOS as,

ρ0(E) =V

4π2N

(

2m

~2

)3/2√E, E ≥ 0 (3.39)

where the work function µ = 0.

(2) DOS for interacting (Correlated) electrons

Starting with:

HGαkσ = 1 (or δ(E)) (3.40)

such that the interactive Hamiltonian is given by,

H = E − (H0 − µ+Σασ(k,E)) (3.41)

where

31

H0 =energy of a Free electron

µ =chemical potential

Σασ(k,E) =Interaction term= self-energy of the interaction

By using Dyson’s equation below, the Green’s function can be approximated.

Gkσ(E) = G(0)kσ (E) +

1

~G

(0)kσ (E)Σσ(k,E)Gkσ(E) (3.42)

We can find “G” including the interaction and model the material via the first order impact

of the self-energy and not all higher order Green’s functions. This is important because

we can use G in the density of states equation to find the DOS with electron-electron

interaction, thus, with G from the Hubbard Hamiltonian for interacting narrow bands,

ρσ =−1

πIm(G) (3.43)

and the density of states containing the electron-electron interaction is

ρσ =1

N

∑

k

δ[E − E(k)−Rσ(E − µ)] (3.44)

where the DOS without interactions is

ρ0 =−1

πIm(G0) (3.45)

or

ρ0 =1

N

∑

k

δ(E − E(k)). (3.46)

So, if we compare the DOS equation for interacting quasi-particles with the standard Bloch

density of states we see that:

ρσ = ρ0[E − Σσ(E − µ)]. (3.47)

This means that if Σ ∼= 0, we have a metal and for Σ ∼= U we have an insulator. As the

DOS inters the conductivity and often “susceptibility”, the MIT/IMT can be seen as a

transformation of the density of states as the function Σ is switched on and off.

32

(3) The Mott transition and the Density of States

The general form of the self energy is given by:

Σ = Rσ(k,E) + iIσ(k,E) (3.48)

with the imaginary part Iσ set to zero, as commonly done for Mott insulators in which,

Σ(r, E) = Σ(E), i.e. Σ(k,E) = Σ(E). (3.49)

This allows us to write the DOS equation in terms of only the real part of the self energy

as(Dobrosavljevic et al. [59]):

ρσ = ρ0[E −Rσ(E − µ)] (3.50)

where Rσ(Σ− µ) is the phase transition self-energy.

In the next chapter, we will show that the essential characteristics of the CeRAM stor-

age device, is such that a transition metal oxide (TMO) or perovskite, properly doped to

reduce oxygen vacancies, takes advantage of the MIT/IMT via the free electron density pa-

rameter. Thus, in the “Set” mode, in which the MIM structure reaches a critical tunneling

and thermionic current level, the injected electrons increase the electron concentration to the

level of the Mott criterion for IMT (i.e. aBn1/3c = 0.26). When this electron concentration

is annihilated by hole injection at the “Reset” voltage, the interaction U , switches on by the

double occupancy on the 3d9,10 orbital. Thus the two memory states are accomplished.

Chapter 4

Transport in Nanoscale Oxide Devices

4.1 The MIM Diode

A quantum mechanical representation of the MIM diode is the foundation for the model-

ing of the I-V characteristics of CeRAM devices. In this section I will describe the generalized

model used for representing the barrier potentials in an MIM diode, as well as the generalized

current equation used by Simmons [60] to show tunneling current through the barrier.

4.1.1 Potential energy and Image force

Let us first start with the simplest model for a rectangular potential barrier in two similar

metal electrodes separated by an insulating film. The intrinsic electric field of this system is

represented by

Fi =(Φ2 − Φ1)

es(4.1)

where Φ1 and Φ2 are the metal work functions of the electrodes, and s is the insulating film

thickness. The barrier height of the metal insulator interfaces ϕim is related to the metal work

function Φm and the electron affinity of the insulator χi by

ϕim = Φm − χi (4.2)

and are related to one another as

ϕ2 = ϕ1 + eFis

= ϕ1 −∆Φ (4.3)

34

where ∆Φ = Φ2 − Φ1. It is fairly straight forward to represent the potential barrier height

through the material as

ϕ(x) = ϕ1 +x∆Φ

s(4.4)

where x is the position in the insulating region between electrodes. When a bias is applied to

one electrode and the film is no longer at the ground state, 4.4 can be re-written as:

ϕ(x) = ϕ1 +x(∆Φ− eV )

s. (4.5)

The abrupt barrier edges represented by the rectangular model is in fact not a realistic

representation of real interfaces which are much smoother due to an image force between the

metal and the insulator. This image potential is found as [61]:

Vi =e2

8πKǫ0

1

2x+

∞∑

n=1

[

ns

(ns)2 − x2− 1

ns

]

(4.6)

which is quite bulky and difficult to work with. Thankfully, the image potential can be accu-

rately approximated as [60, 61]:

Vi =−2.88s

Kx(s− x)eV (4.7)

so the total potential energy in the insulator is now represented as:

ϕtot(x) = ϕ(x) + Vi

or more explicitly

ϕtot(x) = ϕ1 +x(∆Φ− eV )

s+

−2.88s

Kx(s− x)eV. (4.8)

Figure 4.1 shows a rectangular potential barrier for an MIM diode with similar electrodes. As

you can see, the image potential has a negative influence on the total potential of the barrier,

lowering the total maximum of the potential barrier, and smoothing out the abrupt nature

of the barrier edges. The total potential barrier equation 4.8 for a 1 V forward bias with

ϕ1 = ϕ2 = 1eV , K = 1, T = 300K is simulated in MATLAB and can be compared to the

rectangular potential barrier in figure 4.1 for different barrier thicknesses.

35

−2 0 2 4 6 8 10 12−5

−4

−3

−2

−1

0

1

2

x (nm)

Pot

entia

l (eV

)

ϕϕim

ϕtot

(a) total potential 10 nm barrier

−10 0 10 20 30 40 50 60 70 80 90 100−5

−4

−3

−2

−1

0

1

2

x (nm)

Pot

entia

l (eV

)

ϕϕim

ϕtot

(b) total potential 90 nm barrier

Figure 4.1: Image potential effect of total potential barrier given a rectangular potential barrierat 1 V forward bias for a symmetric MIM diode with (a) 10nm and (b)90nm barrier thickness.ϕ1 = ϕ2 = 1eV , K = 1, T = 300K. (Note: See Appendix A listing A.1 for MATLAB code.)

4.1.2 MIM current equations

The equation representing current flow between two similar electrodes can be found as

[61]:

Jth = AthT2e−ϕ′/kT (1− e−eV/kT ), (4.9)

where

Ath =4πmek2B

h3, (4.10)

and ϕ′ is the maximum barrier height. This equation represents the current due to thermionic

emission and is limited by thermal effects.

The generalized equation for tunneling current as presented by Simmons [60] is:

Jtun = J0

ϕ exp(−Atunϕ1/2)− (ϕ+ eV ) exp(−Atun(ϕ+ eV )1/2)

(4.11)

where

J0 =e

2πh(β∆s)2, (4.12)

36

and the Atun factor is

Atun =4πβ∆s

√2m

h. (4.13)

The mean barrier height ϕ is

ϕ =1

∆s

∫ s2

s1

ϕ(x)dx, (4.14)

where s1 and s2 are the point where the potential barrier, including image charge, intersect

the Fermi level and the tunneling distance ∆s = s2 − s1. The correction factor β is

β = 1− 1

8ϕ2∆s

∫ s2

s1

(ϕ(x)− ϕ)2dx ≈ 1. (4.15)

Figure 4.2a shows the thermionic and tunneling current densities for a MIM diode with an

average barrier height of 1eV versus applied bias. For low bias, thermal emission dominates

the current density through the barrier. As the applied bias increases to eVapplied ≈ ϕ, the

tunneling current increases rapidly and begins to dominate. Figure 4.2b shows how both

thermal and tunneling dominated currents contribute to the total current versus applied bias

characteristic.

0 0.2 0.4 0.6 0.8 1 1.210

−35

10−30

10−25

10−20

10−15

10−10

10−5

100

105

Applied Bias (V)

J ther

mal

(A

/cm

2 )

Jthermal

Jtunnel

(a) Thermionic emission and tunneling current den-sity

0 0.2 0.4 0.6 0.8 1 1.210

−5

10−4

10−3

10−2

10−1

100

101

102

103

104

105

Applied Bias (V)

J tota

l (A

/cm

2 )

(b) Total current density

Figure 4.2: Thermionic emission, tunneling current, and total current density vs. applied biasfor a symmetric MIM diode with ϕ = 1 eV, s = 90 nm, and T = 300 K. (Note: See AppendixA listing A.2 for MATLAB code.)

37

For much of our purposes, in the regions of operation that are valid for CeRAM devices,

the tunneling current equation 4.11 can be simplified to: (See Appendix B.1 for derivation)

Jtun = −J0eV

2exp

(

A(eV/2)1/2)

. (4.16)

4.2 Transport During the Phase Transition

Although the MIM structure is basic device architecture, Simmons model shows only an

independent electron approximation based on the semi-classical WKB approximation. From

this alone, it is not possible to show the MIT/IMT transitions from such a model. However,

Simmons model does show the electron density for free carriers that screen the ion cores and

form the IMT.

The system that best describes the devices in question, for the phase transition, is

graphically represented in figure 4.3. For this system we have a finitely restricted nanojunction

sandwiched between two ideal electrodes, or Leads, which are connected to two infinite potential

reservoirs. The flow of electrons through the system is represented as a function of electrons

moving into the junction from the left minus a function of electrons moving into the junction

from the right. These equations are shown as follows:

fL(E) =1

exp[(E − µL)/kB)] + 1, (4.17)

and

fR(E) =1

exp[(E − µR)/kB)] + 1. (4.18)

The total current of the system is the sum of all currents, and is thus the integral of the

energy distribution, shown in 4.3, multiplied by the density of states which is best represented

with the advanced and retarded greens functions:

I = 2ie

2~

∫

dE

2πTr

[ΓL(E)− ΓR(E)]G<(E)

+ [fL(E)ΓL(E)− fR(E)ΓR(E)][G+(E)−G−(E)]

. (4.19)

38

Figure 4.3: Schematic of the system described within the Landauer approach. The nano-junction is sandwiched between two ideal (scattering-free) leads. Particles are injected at theinfinite far left and infinite far right with two different local equilibrium distributions. Theinfinite far regions may be conceptually thought of as two “reservoirs”, even though these donot interact dynamically with the system. The (macroscopic-averaged) local electrochemicalpotential µ(x) varies along the whole structure. c©2008 Massimiliano Di Ventra. Reprintedwith the permission of Cambridge University Press.[62]

The total density of states can be reduced to a function A(E) which leads to:

I =2e

~

∫

dE[fL(E)− fR(E)]Tr ΓL(E)ΓR(E)

ΓL(E) + ΓR(E)A(E) (4.20)

where,

2πA(E) = −2G+(E)ImΣ+(E)G+(E). (4.21)

By introducing the transmission coefficient,

TLR(E) = −2TrΓLR(E)G+(E)ImΣ+(E)G−(E) (4.22)

the total current of the system now becomes:

I =e

π~

∫

dE[fL(E)− fR(E)]TLR(E). (4.23)

39

Converting to real current density will be more useful in the implementation of the transmission

current into the CeRAM model,

J =2q

h

∫

Γ0(fL(E)− fR(E − eV ))ρσdE. (4.24)

It is here that it can be shown that the interaction, i.e. Σ ≈ φU , enters the current via ρσ, the

DOS with interaction. An energy gap develops when ρσ 6= ρ0. Simmons model is a specific

situation when tunneling (and thermionic) current depends only on ρ0. which can be simplified

to:(See Appendix B.2 for derivation)

Jφ =∑

k

J0

(

eβ(E−E(kF ))(

1− eqV/kT)

. (4.25)

If we are only concerned with the current at the Fermi level which is centered in the U gap,

then E = E(kF ) and we can express this equation as

Jφ(fermi) = J0

(

eqV/kT − 1)

. (4.26)

Notice the change in sign here which is due to the fact that we are interested in modeling

electric current as opposed to electron flow which is opposite. The I-V characteristics of 4.26

are shown in figure 4.4 at room temperature. The reason this plot is represented as current

vs. voltage instead of current density is because J0, which would be dependent on device area,

was chosen arbitrarily to be 1×10−12 and is within range of the baseline current of an average

CeRAM device on the order of 10’s of micrometers.

As shown in figures 4.4 (without thermionic current) and 4.5 (with thermionic current),

the “set” current is nearly ballistic as Rs → 1 due to the electron interaction and the models

exhibit the same result, i.e. JMIM (V = Vset) ∼= Jφ(V = Vset). This will be used in the next

chapter to show the CeRAM storage cell.

In the insulating side of the Phase current equation, there is an experimentally derived

J0 which is simply the extrapolated 0-bias current of the device. By adjusting this J0 value

value in range with the thermionic emission current we are able to see the total effect of the

current mechanisms for the phase transition plus thermal and tunneling effects.

40

−2 −1.5 −1 −0.5 0 0.5 1 1.5 2−1

0

1

2

3

4

5x 10

−3

Applied Bias (V)

Cur

rent

(A

)

Idiode

Compliance

Figure 4.4: Diode current vs. applied bias for a symmetric diode withcharge near the Fermi level.(Note: See Appendix A listing A.3 for MAT-LAB code.)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.610

−45

10−40

10−35

10−30

10−25

10−20

10−15

10−10

10−5

100

105

Applied Bias (V)

J ther

mal

(A

/cm

2 )

Jthermal

Jtunnel

Jdiode

(a) Diode, Thermionic, and tunneling current den-sity

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.610

−12

10−11

10−10

10−9

10−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

101

102

103

104

105

Applied Bias (V)

J tota

l (A

/cm

2 )

(b) Total current density

Figure 4.5: Thermionic emission, tunneling current, phase transition Diode current, and totalcurrent density vs. applied bias for a symmetric MIM diode with ϕ = 1.5 eV, s = 90 nm, andT = 300 K. (Note: See Appendix A listings A.2 and A.3 for MATLAB code.)

Chapter 5

CeRAM

Last chapter showed the physical model of the CeRAM storage cell I-V characteristics.

In this chapter we will finally show the complete model, the actual device fabrication and

SPICE modeling for circuit applications.

5.1 The CeRAM Concept

The basic concept of CeRAM is that of a non-filamentary resistive RAM based on com-

pensation of disruptures in the co-ordination sphere of transition metals Mx caused by space-

charge and defects with (CO)x or Mz(CO)y ligands, where Mz represents a secondary tran-

sition metal. In other words, the switching properties of the transition metal oxide (TMO)

compounds that could otherwise be negatively affected by non-stoichiometry and defects in

the crystal structure are repaired through doping with natural ligands of carbonyl (CO)x and

metal-carbonyl’s Mz(CO)y. Once the TMO structure has been properly compensated, the

e–−e– interaction or repulsion can then be exploited for the switching and memory functions.

This interaction is also known as electron correlation and is thus the namesake of the device

i.e. Correlated electron RAM.

The crystal structure of NiO takes the form of a 6-coordinate octahedral which is shown

in figure 5.1a of a perfect crystal. Because, however, we know that the films deposited by CSD

are in fact amorphous films, the crystal structure is anything but perfect. The carbonyl ligand

in figure 5.1b is the Nickel Tetracarbonyl Ni(CO)4 that was chosen because of its preferential

42

triple bond between Carbon and Oxygen allowing carbon to easily substitute and repair any

defects present in the molecular structure. The primary embodiment of this compensation is

in the neutralization of excess Ni species by the following reaction:

4CO + Ni C4NiO4 (5.1)

which is the result of π-backbonding in which electrons are donated from the d-orbitals of the

transition metal to the anti-bonding orbitals of CO.

(a) Crystal structure of Nickel(II) Oxide (b) Nickel-tetracarbonyl ligand structure

Figure 5.1: 3-D Crystallographic representation of the (a)NiO octahedral and (b)Ni(CO)4structures.

The memory switching function of such a device is principally based on Metal to Insulator

Transitions (MIT’s) for which TMO’s are commonly known to exhibit based on their incomplete

3d shells. Conduction in TMO devices is the result of a disproportionation reaction that

changes the oxidation state of Ni. Disproportionation is known as a type of oxidation-reduction

reaction in which both the reduced and oxidized species coexist. Thus, This reaction takes the

form:

2Ni2+ Ni1+ +Ni3+ (5.2)

43

which means that the level 3d8 is split as d8 + d8 → d7 + d9, and the defect free materials only

contain this reaction such that

U ∝ −kT ln

(

CNi3+CNi1+

(CNi2+)2

)

(5.3)

or, as represented in an oxide compound the reaction is shown as

(Ni2+O2−)2 Ni1+O2− +Ni3+O2−. (5.4)

This reaction is called a disproportionation reaction when it occurs from left to right

and a comproportionation reaction when it occurs from right to left. In essence, Ni1+ gains an

electron, and Ni3+ loses an electron. Losing an electron is called ionization and has energy (I).

Gaining an electron is called affinity and has energy (A). The difference between the ionization

energy and the electron affinity energy creates an energy gap U which is the electrostatic energy

that repulses two electrons. Within crystal sites, Ni atoms, which when in their most common

2+ oxidation state deep inside the 3d shell are stable, are considered localized and do not allow

for electrical conduction. However, Mott demonstrated that these materials can be made to

conduct when a definite amount of energy, equal to the energy gap U , is provided to the system

(e.g. injected electrons, heat, pressure) thus creating the Ni1+ and Ni3+ states that are free to

move about the lattice by electron transfer.

The breakthrough of CeRAM comes with the defect compensation from metal-carbonyl

complexes M(CO)x where M represents all transition metals and more specifically in our case,

Ni(CO)4. As previously described, the COx bond with Ni contributes an electron in a π-bond

and compensates for any hole defects in the lattice. This allows the NiO lattice to be in its

conductive Ni1+ + Ni3+ oxidation states as deposited thus eliminating the requirement for

a high electroforming voltage before the device can transition from metal to insulator and

back again. Thus, NiO becomes mostly a d8 d9 + d7 material which can have a reversible

quantum phase transition (∼ 10’s of femtoseconds) in the application of a voltage such that

at high voltage (VSET ≈ 1.2V ) injects electrons from the electrode in quantity enough to

44

decrease the screening length around each Ni ion and allow electrons to overcome the charge

gap U moving some electrons to the upper Hubbard sub-band and creating holes in the lower

Hubbard sub-band. Thus, a metallic phase appears. In most cases, the VSET causes the

transition from semiconducting behavior to metallic behavior to occur ballistically following

Schottky or thermionic field emission leading up to the transition. Design of the interfaces to

achieve optimum low set currents ( i.e. ICOMPLIANCE) which effectually reduces the on state

current ION in the metallic phase of the device.

5.2 Device Fabrication

SiO2/Si

Substrate

Pt Bottom Electrode

NiO (Multi layer)

Pt Top Electrode

Figure 5.2: The CeRAM MIM-cap test structure.

CeRAMs are constructed in a Metal-Insulator-Metal (MIM) capacitor configuration

(shown in Figure 5.2) in which the insulator layer is replaced with a Transition Metal Ox-

ide (TMO). For research device fabrication, CeRAM structures are processed on 4” silicon

substrates with a thickness of 500µm and an 5000Alayer of thermally grown silicon dioxide.

The metal, in this case Platinum, is deposited using physical vapor deposition (PVD), or

more specifically, RF sputtering, to a thickness of 2000A. Thin films of NiO were deposited

on these Pt/SiO2/Si substrates using spin-on metal-organic-decomposition (MOD) of Octane

based precursor solution prepared by Kojundo Chemical Laboratory Corporation, Japan. The

45

precursor can then be further diluted with Octane to control molarity and subsequently, the

concentration of nickel-carbonyl complexes present in the films. The precursor is then applied

using a spin coater and subsequently dried and pyrolyzed through open air baking at temper-

atures ranging from 150C to 300C . This process is then repeated several times to achieve

the desired final thickness and to include any compositional variations on a per layer basis.

With this spin on MOD process, it is also important to note that very fine control of film

thickness and wafer uniformity can be controlled simply by adjusting the rotational speed of

the wafer, or other substrate for that matter, during the initial coating phase of the process.

The completed film stack is then annealed in a diffusion furnace with oxygen flow at a tem-

perature of ≤ 450C to crystallize the NiO layer. Final film thickness is then measured using

ellipsometry, and the top electrode Pt layer is deposited by RF sputtering. The test structures

are then defined using contact mask optical alignment with positive photo resist, and etched

using an ion milling process. Finally, the remaining photo resist is stripped from the patterned

devices using an oxygen plasma asher leaving the devices clean and ready for test. Figure 5.3

illustrates the CeRAM test structure process flow.

Start

SiO2/Si Substrate

Pt deposition (PVD)

Bottom Electrode

Precursor dilution

(Octane)

Pt electrode processed on different

day ?

Dehydration bake

Yes

No

Spin CoatingDryingPyrolizedPost Deposition Furnace Anneal

Repeat to desired final thickness and per layer composition variations

Photolithography

Pt deposition (PVD)Top Electrode

Stack EtchIon Milling

Photoresist Strip

End

CeRAM Test

Structures

Figure 5.3: Illustration of process flow for CeRAM test structure.

46

Figure 5.4: (a)Schematic diagram and (b)100× magnification top

view image of CeRAM test structures. Encapsulated structures withvarying dimensions and off resistor contact pads(upper) and direct probe(lower center) devices for I-V characterization of CeRAM.

For fabrication of these test structures for electrical characterization, a variety of photo-

47

mask sets were created and the most comprehensive of which is shown in 5.4. When processing

the full mask set, which contains a total of 4 mask steps, arrays of ratioed capacitor structures

are available that feature full dielectric encapsulation, off-device contact pads to eliminate

probe damage to the actual device, large and small via contacts to identify any issues presented

by contact resistance, and square vs. rectangular devices to analyze any performance variations

due to device dimensions. This mask set was designed in such a way that different device

structures can be processed simply by skipping over mask steps in the process sequence. For

example, if only the first two masks are used and the final metallization step is skipped then

longitudinal structures are made available (5.4 (a) lower left) to test the behavior of the material

for in-plane devices with varying electrode spacing. Similarly, if the first two masks are used

and the final metallization step is processed, structures for direct probing are made available

and are shown in 5.4 (a) bottom center. Additionally, a single photo-mask was developed

containing a variety of feature patterns and sizes to allow for analysis of size and edge effects

on the electrical performance of the test devices which include square, rectangular, and circular

structures with corresponding surface areas for each pattern to isolate edge effect variations in

the electrical behavior of the devices.

5.3 Characterization and Analysis

In order to properly understand the factors affecting device performance, a variety of

analysis techniques are used to determine the physical and chemical characteristics of the

materials used in that device. Things like surface, bulk, and interface microstructure play a

critical roll and can be analyzed through various forms of microscopy. Elemental compositions

impurity concentrations, chemical state identification in bulk materials and thin layers will

affect device performance and need to be analyzed if ultimately to be improved upon. Still,

electrical measurements provide some of the most sensitive techniques for measuring factors

that will fundamentally determine device performance.

48

5.3.1 Physical and Chemical Characterization

To understand the electrical properties of a CeRAM device it is first of critical importance

to understand the physical attributes of thin NiO films as well as the chemical composition of

these films.

X-ray photoelectron spectroscopy (XPS) was used to determine the chemical composition

at shallow depth of penetration of the grown NiO films for CeRAM. With this technique it

is possible to determine the oxidation states of Ni ions in the NiO bond. Figure 5.5 shows

the Ni 2p spectrum of the CeRAM NiO films which match very well with standard results

for stoichiometric NiO [63]. From the plot it is clear that the Ni2+ bond state for the NiO is

present from the Ni 2p3/2 peak at 854.5 eV as well as someNi3+ species which are present in the

Ni2O3 compound from the peak in the 855.8-856.6 eV energy range. This conformation of the

presence of the Ni2+ oxidation state is very significant in that the key to the Mott-like charge

transfer metal insulator transition, which is the basis for CeRAM, is reliant on a disproportion

reaction occurring in which the Ni2+ ion is both oxidized and reduced to form both Ni1+ and

Ni3+ are produced and there is no trapping, only Ni1+ and Ni3+ pair formations as described

by Mott.

Evidence of both the Ni2+ and Ni3+ oxidation states is also present in the Oxygen 1s

band which is shown in figure 5.6. As is evidenced by the plot the Oxygen peak at an energy

of 529.8 eV corresponds nicely with stoichiometric NiO while the hump at 531.6 eV shows the

existence of Ni2O3 species in the as deposited films as well. All XPS standard peaks were

referenced from the NIST X-ray Photoelectron Spectroscopy Database [64].

The surface topology of a prepared sample can be examined using a Scanning Electron

Microscope (SEM). Plane-view SEM imaging techniques were able to observe surface defects

on the CSD deposited NiO surface as well as any surface structural properties. The image

displayed in figure 5.7 shows a hole in the surface of the film ∼ 400 nm in diameter as well

as general surface roughness with features sizes in the 10’s of nanometers. Controlling the

49

890 880 870 860 850 840152025303540455055606570

Ni 2p1/2

Inte

nsity

[a.u

.]

Binding energy [eV]

x103

Ni 2p3/2

Ni2+

Ni3+

Figure 5.5: XPS Spectra for Ni 2p energy spectrum in carbonyl liganddoped NiO CeRAM

roughness of the film is critical for scaling down to nanometer sized technology nodes where

the desired total dimensions of the active device would be on the order of 50 nm. It would

not be possible to rely on structure uniformity in large arrays across an entire wafer if a single

grain were on the order of 20% of the total feature size. In order to improve the surface of the

CeRAM films, work was done to modify the grain size by altering the molarity concentration

of the precursor solution during spin on deposition.

To determine the effects on surface morphology observed in the SEM analysis of the

solution molarity and number of layers, films were grown of multiple layers with both high

and low molarity precursor solutions. Atomic Force Microscopy (AFM) scans were done to

determine surface roughness profiles of the films. As you can clearly see from the images in

fig. 5.8, the surface roughness of the film can be controlled simply by changing the molarity of

the precursor solution during film deposition. Standard film layers of higher molarity solution

50

540 538 536 534 532 530 528 5260

10

20

30

40

50

60

O 1sx103

Inte

nsity

[a.u

.]

Binding energy [eV]

NiO

Ni2O3

Figure 5.6: XPS Spectra for O 1s energy spectrum in carbonyl liganddoped NiO CeRAM

exhibit larger grains and thus rougher films where as layers deposited at a lower molarity

produce smaller grains resulting in smoother films.

In addition to the surface morphology that is observed by AFM type scans, and since our

ideal structures for switching and memory devices are not homogeneous through the thickness

of the film, Transmission Electron Microscopy (TEM) scans were taken so we could observe

the crystalline structure of the film through its thickness. Note the formation of large grain

type structures throughout the film and the roughness on the top surface (right side of the

images) propagated as the large grains are formed throughout the deposited layers all the way

up to the surface of the top Pt electrode (Fig. 5.9). At high magnification (Fig. 5.9d) it is

straight forward to see that there are many defects in the crystal structure and that multiple

different crystalline structures exist in the films. In certain areas it is obvious that cubic NiO is

dominant where in other areas of the film it appears that a distorted rhombohedral orientation

51

Figure 5.7: SEM image at 20,000x magnification of defect and surfacemorphology Nickle Oxide based CeRAM CSD film.

(a) Standard Layer (b) With surface modifying layer

Figure 5.8: AFM topography scans for NiO films deposited using different precursor molarities(scan size: 2µm)

exists.

Scanning Transmission Electron Microscopy (STEM), which is also a high-resolution

52

(a) (b)

(c) (d)

Figure 5.9: cross sectional HRTEM images of Pt/CSD deposited NiO/Pt CeRAM ii

scan but is different than the HRTEM technique used above, has the advantage of showing

the distinction in grain or dislocation sizes of the highly doped region and the lower doped

region of the CeRAM films (figure 5.10). Additionally, STEM is useful for generating Electron

Energy Loss Spectroscopy (EELS) line scan analysis which is useful for determining atomic

concentrations through a small cross-sectional scan allowing one to pinpoint concentrations

53

through the thickness of the film; I will present more on this later. As you can see in figure

5.10b, the film layers closer to the bottom Pt corresponding to the higher doped region have

larger grains than the lower doped layers closer to the top Pt.

(a) (b)

Figure 5.10: STEM image of CeRAM cross-sectionii

EELS analysis was used to study the composition and chemical bonding properties of

CeRAM samples prepared with both low and high ligand doping compositions. EELS was

chosen because it is ideally suited for measuring elements with relatively low atomic number

and is perhaps the best method for spectral analysis of carbon compounds. If you study the

subfigures in figure 5.11, in which EELS analysis was done on isolated layers with low carbonyl-

ligand doping concentrations (5.11b) and high carbonyl-ligand doping concentrations (5.11c),

it is exceptionally clear that the carbon content in the highly doped region is roughly double

that of the lower doped region which confirms the approach used for controlling this doping

concentration was successful.

As was previously mentioned the line scan EELS analysis results, shown in figure 5.12,

clearly show that the concentration of carbon through the first 25 nm’s of the film on the scan

line was nearly double that of the remaining thickness of the film.

54

(a)

(b) (c)

(d) (e)

(f) (g)

Figure 5.11: Electron energy loss spectrum scans for CeRAM sample with layered low carbondoping concentration layers (LD) on top of high carbon concentration layers (HD).ii

55

(a) (b)

Figure 5.12: EELS line scan through cross section of carbonyl doped NiO based CeRAM teststructureii

5.3.2 Experimental Setup

We constructed CeRAM devices of simple MIM-like capacitor structures that can be

directly probed from top to bottom as well as structures designed with off device contact pads.

These structures are illustrated in Figures 5.2, 5.4. For typical experimentation, devices are

constructed of n-type Si with a 500nm thermally grown oxide substrates, Pt bottom electrode,

NiO layer, and Pt top electrode. Electrical contact to devices is done using a micro-probing

station with probing accuracy down to 1µm. IV characterization was done using a Semicon-

ductor Parameter Analyzer (SPA), and to perform hysteresis cycling and low volume pulse

cycling on the devices, a graphic user interface (GUI) was created using LabVIEW for opera-

tion of the SPA and data collection (Fig.5.13). The LabVIEW GUI allows the user to perform

a variety of tests and plots the data in real time on the screen so the operator can make para-

metric adjustments on the fly as well as collect data in text files which can later be plotted and

analyzed. These tests include: Initial sweep, where the initial as deposited I-V characteristics

of the device can be characterized; Single Set/Reset, which performs a single set cycle in either

polarity followed by a reset also in either polarity; Full Hysteresis, which performs a set and

ii Images provided by Dr. Ning Lu, Dr. Ce Sun, Dr. Jinguo Wang, Dr. Moon J. Kim, Dr. Geunhee Lee,

and Dr. Orlando Auciello, The University of Texas at Dallas.

56

reset sweep in both positive and negative polarity to show any performance variation in bipolar

and nonpolar operation; and finally, cycling which performs repeated set/reset cycles for a user

defined number of cycles allowing the generation of repeatability and fatigue characteristics

of the DUT. CV measurements were performed using an LCR meter and Symetrix Othello

software which was specifically designed for testing automation of Ferroelectric capacitors in a

similar MIM configuration.

Figure 5.13: LabVIEW GUI

High volume pulse cycling is somewhat more involved than the DC sweep type charac-

terization that is used to generate the characteristic IV data though it is critical to ensure

reliable operation in non-volatile memory application. Where the SPA used for generating

IV data and sweep cycling data is equipped with an internal current compliance circuit the

pulse pattern generator that met the necessary power requirements is not. Because of this

57

lack of internal compliance control in the testing equipment it was necessary to create external

circuitry capable of limiting the current on a SET cycle while also being capable of allowing

sufficient current for a RESET to occur. This same type of external compliance circuitry is

what would need to be incorporated on silicon for memory arrays of CeRAM as well as other

forms of resistive memories.

High volume pulse cycling is currently performed using a Pulse pattern generator and

Oscilloscope to monitor the input and output and using discrete circuit solutions inline to

provide current compliance. A labVIEW GUI (Fig.5.14) was also created to perform pulse

cycling because of a need to perform many operations in rapid succession and collect data.

For example, consider a pulse testing sequence for the 1T1R compliance circuit if figure 5.17.

The sequence would be performed as follows all while collecting data to be analyzed in the

future: 1) The current state of the device needs to be read by applying a low amplitude read

pulse across the 1T1R circuit. A high amplitude pulse is applied to the gate of the transistor

to ensure that current can flow freely through the circuit and be sensed at the oscilloscope.

2) Assuming the device is in the off or high resistive state, a set operation is performed by

applying a very fast (on the order of 10’s of nanoseconds) high amplitude pulse is applied

across the 1T1R circuit while simultaneously pulsing the transistor gate with a precise voltage

so as to limit the amount of source to drain current IDS , providing current compliance to the

CeRAM. 3) The current state of the device is once again read to determine if the set operation

was successful of needs to be repeated. 4) Assuming the set operation was in fact successful,

a reset operation is performed by applying a medium amplitude pulse, typically a few orders

of magnitude slower than the set pulse for external compliance circuitry (the reason for which

will be discussed later), while simultaneously pulsing the transistor gate with a sufficiently high

voltage as to not impede current flow through the CeRAM so sufficient current is provided for a

successful reset. This entire sequence is then repeated for a specified number of cycles to collect

repeatability and fatigue data. Custom testing solutions are currently being investigated that

will ease in monitoring high speed switching as well as more accurately emulate real world

58

circuit solutions.

Figure 5.14: Pulse switching GUI

One issue that has had a significant impact on the on the performance of RRAM de-

vices due to their dynamic behavior with respect to current control is parasitic capacitance

and CeRAM is no exception. Because the basic operation of CeRAM relies heavily on how

accurately we control the current allowed to flow through the device, it is necessary to consider

all additional sources of charge when in the low resistance state, excess current can be sourced.

In a conventional testing setup for IV characterization for example, there are many sources

of excess charge even outside the device itself. Consider a CeRAM connected to an SPA in a

conventional manual probe station where bias is supplied to the top electrode of the device and

the bottom electrode of the device is grounded. Assume we are using prototypical BNC coaxial

cables with a 50Ω impedance and a length of 4’ to connect the top and bottom electrodes to

source and ground respectively. Considering that the typical cable in this configuration has

about 30pF of capacitance per foot the parasitic capacitance due to cabling alone can be esti-

mated at ∼ 240pF. Additionally, there is capacitance associated with the probe contacts and

59

the built in dielectric capacitance of the device itself. In order to calculate the total additional

charge contribution of the various sources of parasitic capacitance one would need to use the

following formula:

Q = CTotal ×∆V, (5.5)

where

CTotal = (Cp + Cd + · · · ).

If CTotal is large enough, the device could experience a hard breakdown destroying that cell for

any further operation. For smaller capacitances, the excess charge is not so catastrophic, but

can still contribute to a change in the LRS of the device since the LRS is proportional to the

total current through the device which is controlled by Icomp. An example of the equivalent

circuit with ideal current limiting is shown in Figure 5.15.

+

−

I=Icomp

Cd

CeRAMCp

Figure 5.15: Equivalent circuit for testing setup of CeRAM with exter-nal compliance circuitry including (a)parasitic capacitance from cables,probes, and contacts, (b)built in dielectric capacitance in off state whichcauses current “snapback” during set.

It is precisely because of this parasitic capacitance that great care must be taken when

implementing current compliance into the testing scheme. Several methods of controlling

the switching current of CeRAM devices have been employed to determine the best fit to

60

achieve as close to ideal current limiting as possible. These methods include instrument current

compliance provided by parametric analysis equipment (e.g. SPA), load resistor limiting (Fig.

5.16), a 1T1R circuit in which the BE of the CeRAM is connected to the drain side of a mosfet

transistor and IDS is controlled by the transistor gate voltage VGS (Fig. 5.17), and the most

controllable and consistent of the bunch, but also most complex circuitry, is the cascode current

mirror compliance circuit in which the current can be precisely limited for a large range of bias

voltages by using a constant current source on the reference leg of the mirror (Fig. 5.18).

The simplest method requiring no additional circuit components for parametric analysis

would, of course, be the instrument current compliance provided by the SPA, but, as is often

the case, the simplest method is also the least reliable. This lack of measurement reliability

primarily stems from the fact that the CeRAM switching times are so fast (on the order of

ns or smaller) where the instrument response time is relatively slow in comparison (on the

order of tens of µs). This means that for a set operation, for instance, the device has already

transitioned from the HRS to the LRS long before the instrumentation has time to catch up

and measure that the compliance limit has already been overshot.

IDUT

CeRAM

RLoad

(a)

I

V

(b)

Figure 5.16: Load resistor compliance circuit(a) and I-V response(b)

The next simplest current control method, though faster than the instrument current

61

compliance, would be the serial load resistor configuration and is not significantly better for

several reasons. This configuration is faster because the response time of a resistor is a function

of its RC time constant and for even a typical axial type resistor the parasitic capacitance Cp

is on the order of tenths of pF which for a 1kω resistor equates to a time constant on the order

of tenths of ns and is reasonably within range of the CeRAM switching time. The reason this

solution is not the most ideal comes from the input response of a resistor as well as the voltage

divider created by two resistors in series, which is essentially what we have with a load resistor

connected to the Bottom Electrode (BE) of a CeRAM element. The concept is that by utilizing

Ohm’s law V = IR, we can pick a resistor such that Icomp = Vin/RLoad (Fig. 5.16b). This

load resistor configuration creates several non-trivial problems by its implementation however.

First, because there is inevitably going to be some dispersion in the set and reset voltages, it

is impossible to pick a resistor that will give the same compliance current from cycle to cycle.

Also, if there happened to be any internal dispersion in the CeRAM resistance not due to

voltage dispersion, the same problem exists. The issue is that if we were to consider the node

between the CeRAM and RLoad as BE which, if we remember from the ideal case, would be

grounded until the point when the CeRAM switches from HRS to LRS, we actually have a

voltage divider in which

VBE = VinRLoad

RDUT +RLoad(5.6)

where RDUT is the series resistance of the CeRAM device. Secondly, a passive circuit element,

such as a resistor, allows for no consideration of the current state of the CeRAM device

which means that some additional means of allowing sufficient current to flow on a reset

cycle is necessary. One potential solution to this problem is to include a Schottky diode in

parallel with the load resistor enabling bipolar switching of the CeRAM device where the

set operation is performed in the positive polarity and current is limited by the load resistor

and the reset operation is performed in the negative polarity and sufficient current is allowed

62

to flow relatively unimpeded through the Schottky diode. This is certainly a viable solution

especially when considering crosspoint array structures for 3D architectures, but still fails to

address the first issue with the inconsistent current limiting. One additional issue that I have

not found discussed anywhere in the literature, but is still a very real issue, is the fact that in a

standard CMOS process resistors are an in-plane device and very susceptible to any variations

in lithography and etch. Because resistors are made based on knowledge of resistivity of the

metal layer material and certain resistances are obtained by creating metal lines of particular

widths and lengths, any variation in the line width or length due to etching variations will

cause a variation in resistance which changes the voltage needed to obtain a specific current

compliance.

IDUT

CeRAM

+

-

VGS

(a)

IDS

VDS

VGS

(b)

Figure 5.17: 1T1R MOSFET compliance circuit(a) and I-V response(b)

The next solution which is an improvement over the simple load resistor circuit is to use

a MOSFET in a 1T1R configuration to provide the current compliance. This solution more

so than the other solutions provided in this section is also the most likely implementation in a

large memory array circuit as well because not only can the MOSFET provide current limiting

it can also provide isolation to the individual memory cell element necessary for large arrays.

The concept of this particular compliance solution is that by placing an adequately sized

63

NMOS transistor between the CeRAM BE and ground, the current allowed to flow through

the circuit is controlled by holding a bias on the transistor gate which provides a constant

VGS and therefore a relatively constant IDS through the active region of the transistor I-V

response. Operationally the 1T1R works as follows: 1) When the memory element is not being

programmed or read, VGS = 0V and the transistor is off. 2) During a SET operation a small

bias is held on the transistor gate bringing VGS > Vth and operating in the active region of

the transistor where IDS ≤ Icomp. 3) During a RESET or read operation VGS >> Vth and

IDS ≥ Ireset allowing current to flow through the CeRAM essentially unimpeded.

The 1T1R configuration, though significantly better suited than a load resistor, still

comes with some implementation and design issues. The transistor must be designed with a

W/L ratio that provides sufficient IDS for the different modes of operation in the transistor ac-

tive region (see Eq. 5.7). It is also important to consider that to achieve consistent compliance

over the widest range of operating voltages which can be done by designing the transistor with

a larger width W which will increase the transconductance gm (see Eq. 5.8) thereby shortening

the triode region and and extending the active region closer to 0V . There are tradeoffs from

any of these design modifications and it is important to remember that increasing gm will also

increase IDS to changes in VGS and increase parasitic capacitance Cgs(see Eq. 5.9).

ID =µnCox

2

W

L(VGS − Vth)

2 (5.7)

gm = 2

√

W

LµnCoxID (5.8)

Cgs =εoxWL

tox= CoxWL (5.9)

The most elegant solution for providing a consistent current compliance over a larger

range of voltages is to implement a Cascode current mirror circuit (Figure 5.18). Because the

current through the mirror is provided through a current source on the reference side of the

64

Icomp IDUT

CeRAM

(a)

IDUT

VDUT

(b)

Figure 5.18: Cascode current mirror compliance circuit(a) and I-V response(b)

mirror circuit, a much more precise compliance current can be provided to the CeRAM and

with much finer adjustment control.

5.3.3 Results and Discussion

This section will provide experimental results for CeRAM devices covering both basic

parametric characteristics and functional characteristics for use in real world application. A

better understanding of the testing methodology described in the previous section will be gained

from an analysis of the experimental results provided by the various circuit configurations and

test implementations.

5.3.3.1 I-V Characteristics

CeRAM devices demonstrate a bi-stable switching behaviors and can be programmed

with either bipolar (Fig. 5.19(a)) or unipolar(Fig. 5.19(b)) switching methods. This type of

switching behavior has been observed by other groups and is referred to as “nonpolar” switching

[52, 65] meaning that bipolar and unipolar switching characteristics coexist creating a polarity

independent system. One advantageous characteristic unique to CeRAM devices is the initially

65

conductive or “born-ON” behavior exhibited by as deposited film structures leading to devices

that do not require electroforming and thus need only be supplied with Set and Reset voltages

for programing in integrated circuit application. By reducing the voltage levels required for

operation of the array, low power operation becomes possible and the necessary real-estate

required for peripheral circuitry decreases.

Figure 5.19: Typical I-V characteristics for (a)bipolar and (b)unipolar switching byvoltage sweep.

A strong correlation has been established between the level of overshoot current during

a Set operation (ISet) and the maximum current flow required for a Reset operation (IReset).

The “OFF-State” or high resistance state exhibits a strong dependence on device area which

directly effects the limit at which ISet must be clamped off. From these relationships we see

that there is in fact a strong defining relationship between IOFF and ION which defines the

current requirements for limiting and select circuitry which in turn effects the overall minimum

size of a memory circuit.

For sufficiently large programing current it can be shown that IReset∝ISet. However,

when the programing current is reduced below an arbitrary threshold, IReset begins to satu-

rate. To illustrate this, the mean IReset values of fifteen cycles at varying compliance levels

for 10x10µm2 and 20x20µm2 structures are shown in Fig. 5.20. The difference in saturation

66

levels can be explained by the reduction in OFF-State dielectric capacitance with the reduction

of device area. This means at low programing current the CeResistor sources current during

dielectric snapback at SET and the minimum IReset saturates. Therefore, scaling the device

minimizes dielectric capacitance, lowering the minimum IReset and maintaining ON-State re-

sistance. Additionally, it is believed that any external pads, cabling, and equipment are also

sources of stray capacitance from which current is sourced during the transition from high to

low resistance state “Set”. Refer to the equivalent circuit for a testing setup with external

compliance is shown in Fig. 5.15. These observations are consistent with K. Kinoshita et al.

[66] who observed that parasitic capacitances from the current limiting circuitry have an ad-

verse effect on the maximum IReset. Moreover, this suggests that the more ideally the current

limiting circuitry can be implemented, the closer IReset comes to IReset∝Icomp. This propor-

tionality can be explained by considering the ON-state of CeRAM as a correlated metal and

observing the Mott criterion which describes the critical point at which the metal-insulator

transition occurs as:

n1/3aB ≈ 0.26 , (5.10)

where n is the electron concentration and aB = 4πǫ~2/me2 is the effective Bohr radius. In the

Mott criterion, n should be referred to as the free electron concentration nf . If the localized

electron concentration is nl, then

nf + nl = n = const.

Though the insulator side always corresponds to

nf = 0

nl = n ,

the metal side is in fact variable. The SET current compliance determines how many electrons

become free when the SET occurs, and

nf = K1ICompliance.

67

On the other hand, the free electron concentration determines the ON-state resistance as

RON = K2/nf = K2/(K1ICompliance).

Our model predicts that the RESET voltage is stable which has also been confirmed experi-

mentally. Hence,

IReset = VReset/RON =K1VReset

K2ICompliance . (5.11)

Thus, the current at the Reset point is proportional to the SET compliance current because

K1, K2 and VReset are constants. Evidence of this is shown in figures 5.20 and 5.21. At the

point where saturation occurs, IReset is dominated by the parasitics in the system and the

above equation no longer holds true.

10-4 10-3 10-210-4

10-3

10-2

(20 m)2

I Res

et (A

)

IComp (A)

(10 m)2

ISet = IReset

Figure 5.20: IReset vs. Icomp at varying set compliance levels for 10 ×10µm2 and 20× 20µm2 structure.

By using techniques to reduce IOFF through process tailoring, and appropriately ad-

justing ISet(orcompliance)/IOFF , we have successfully achieved sub − 100µA reset currents for

68

10-4 10-3 10-210-4

10-3

10-2

102

103

104

I rese

t(A)

ICompliance(A)

IReset

Ron

()

RON

Figure 5.21: Ron vs. Icomp at varying set compliance levels for 10 ×10µm2 structure

externally current limited devices as large as 25µm2 for which the I-V characteristics are shown

in Fig. 5.22. From this example you can see that IReset does not exceed 70µA for ISet limited at

50µA. Taking into account the effect of stray capacitances on IReset and the already observed

result of sub− 100µA reset current, with the implementation of on-chip compliance circuitry,

the general concern of high currents in these types of devices becomes a non-issue.

Cell scaling results also give way to very favorable predictions as dimensions are scaled

to meet with deep sub-micron technology nodes. As devices are scaled down, the OFF-state

resistance increases at a much faster rate than the ON-state resistance which leads to a widening

of the read memory window with scaling. This is easily explained due to the area dependence

of the OFF-state resistance and the dependency of the “Reset” operation on Icomp. That is,

since the voltage required to perform both set (VSet) and reset (VReset) operations remains

relatively constant with respect to area and the OFF-state resistance increases as a function of

69

0.0 0.5 1.0 1.50.0

1.0x10-5

2.0x10-5

3.0x10-5

4.0x10-5

5.0x10-5

6.0x10-5

7.0x10-5

8.0x10-5

Set Reset

Cur

rent

(A)

Voltage (V)

Figure 5.22: I-V curves for CeRAM cell programmed using a 50µAcompliance limit showing a max IReset of approximately 70µA.

area, the compliance current can be reduced to maintain the appropriate ratio of ISet/IOFF .

Since IReset has been shown to be dependent of Icomp and VReset does not change, the ON-

state resistance must change as a function of Icomp which is a much more gradual change with

respect to area.

5.3.3.2 Pulse response

Using external compliance circuitry as was shown in figures 5.16, 5.17, 5.18, CeRAM

devices have shown very promising repeatability results from pulse cycling tests indicating

high, up to 98% switching repeatability in a 1T1R discrete external compliance configuration

5.23.

Consider a discrete 1T1R testing configuration using a Diodes incorporated DMN2004k

enhancement mode N-channel MOSFET mounted into a 3 terminal TO-5 package. The DC

70

Figure 5.23: 200 ms Reset pulse, 50 cycles Switching Reliability: 98%

I-V characteristics for a relevant range of gate voltages are shown in figure 5.24 as collected by

the HP-4155B semiconductor parameter analyzer. From these curves it was determined that

using a gate bias voltage of 0.85 V provided an ∼1 mA current compliance over the desired

programming voltage range.

The effects of input pulse width on the Set and Reset cycles have been carefully examined.

The results have shown that the pulse width on the set cycle is of minimal importance. As

long as the appropriate bias level is achieved, pulse widths in the 10’s of nanoseconds have no

trouble switching the device from the insulating to the metallic state. The main limitation in

this case is that of the pulse generator and from the experiments it has been determined that

programming pulse widths of less than 50 ns have a poor pulse shape in this configuration

when using an Agilent 81110A pulse pattern generator. Even though the generator is rated to

be able to provide pulses with smaller pulse width than this, to actually achieve these pulses

it is necessary to accurately program the load resistance into the generator so it can adjust

to a proper RC time constant. In our case, since the load resistance changes when the device

71

0 1 2 3 4 5 610-6

10-5

10-4

10-3

10-2

Dra

in C

urre

nt I D

[A]

Drain to Source voltage VDS

[V]

VGS=1.00V

VGS=0.95V

VGS=0.90V

VGS=0.85V

VGS=0.80V

VGS=0.70V

VGS=0.75V

DMN2004k: N-Channel enhancement mode MOSFET

Figure 5.24: MOSFET transistor curves

switches, it is not possible to accurately indicate the load which limits the achievable pulse

width.

For the reset case however, the pulse width is quite critical and is drastically affected by

the testing setup as well as device size. Figure 5.25 shows the effect of the reset pulse widths

on switching reliability of a 400 µm2 device over 50 cycles.

5.3.3.3 Reliability and Retention

Using only the external compliance provided by the SPA, we have observed a wide signal

margin of more than one order of magnitude for 100 write/read cycles, as shown in Fig. 5.26.

Additionally, the dispersion in the ON and OFF state resistance on average is less than one

order of magnitude. Since the ON state resistance is believed to be heavily reliant on the

accuracy at which the current is clamped off during a set operation, the dispersion in the ON-

state resistance is expected to show noticeable improvement with on-chip compliance. As a

72

(a) Switching reliability: 94% (b) Switching reliability: 64%

(c) Switching reliability: 32%

Figure 5.25: Average read voltage across a 50Ω sense resistor for reset pulse widths of (a) 200ms, (b) 100 ms, and (c) 50 ms.

result, as devices are scaled down and compliance circuitry is integrated on Si, the read margin

should increase while simultaneously the dispersion in ON and OFF state resistances decrease.

To read the state of the CeRAM cell a small voltage is applied to the top electrode such

that

VRead < VReset (5.12)

and sensing the output current to determine if the CeRAM in the low resistance ON state or

high resistance OFF state. In order to test reading endurance out to a high cycle count, two

CeRAM devices were programmed into known states and pulsed with a 0.2V square wave at

73

0 20 40 60 80 100100

101

102

103

104

105

106

Res

ista

nce

(Ohm

s)

Cycle Number

R OnR Off

Read Margin

Figure 5.26: ROn and ROff resistance of 100 consecutive cycles at roomtemperature and the corresponding read margin.

a frequency of 50MHz. The output is then sensed using a digital oscilloscope by reading the

voltage across a load resistor. The progression of this measurement is as follows: (1) An initial

measurement is taken of the Device Under Test (DUT). (2) The DUT is cycled for a given

number of cycles which is determined by measurement frequency, time, and total number of

fatigue cycles. (3) A subsequent measurement is taken of the DUT. This process repeats until

the total number of fatigue cycles has been reached based on total measurement time and a

final measurement is taken. The results of read endurance testing is shown in Fig. 5.27. These

results show no sigh of degradation in the ON or OFF state resistance after 1012 read cycles

at room temperature using a 0.2V read voltage.

CeRAM devices have been tested in a wide temperature range from 4K to 150C with

minimal observed effects on the I-V Characteristics in samples with external compliance cir-

74

10-1 101 103 105 107 109 1011 1013100

101

102

103

104

105

106

R O

n/R

Off

(Ohm

s)

Cycles

On State Off State

Figure 5.27: Read endurance for high(ROff ) and low(ROn) resistancestates of a (10×10)µm2 cell at room temperature with 0.2V read voltage.

cuitry (Fig. 5.29). Tested samples exhibited non-polar switching characteristics with stable

switching parameters throughout the entire range. To test the nonvolatile data retention at

high temperature, cells were programmed into known resistance states and baked at elevated

temperatures for 1 hour. At the completion of baking, the samples were removed from the hot

plate and tested at room temperature. The respective resistances are shown in Fig. 5.28. As

a result we have shown excellent data retention properties with no degradation of either ON

or OFF state resistance up to 300C for a period of 1 hour. As it is well known that the Mott

transition is a Quantum phase transition, Figure 5.29 shows this characteristic clearly since

the quantum phase transition is temperature independent and our devices exhibit switching

behavior over the temperature range of -269 C to +150 C.

75

0 50 100 150 200 250 300 350100

101

102

103

104

105

Res

ista

nce

(Ohm

s)

Hotplate Temperature (oC)

On State Off State

Figure 5.28: Nonvolatile data retention of high and low resistance statesat elevated temperatures up to 300C for 1 hour.

5.4 Modeling and Simulation

5.4.1 Circuit simulation

In a resistive memory, the resistance value tells if we have a logical “1” or “0”. When we

have a Logical “0” the resistance is very low and behaves as an electrical short circuit. When

we have a logical “1” the resistance is very high and behaves as an electrical open circuit. For

the purpose of simulating simple circuits and circuit arrays a SPICE model was created for

CeRAM that could provide a rough representation of the devices behavior as well as contain

some sort of state memory. In the model, an RS latch was used to remember the current storage

state of the device (Ron or Roff ); a voltage controlled switch with two different resistances is

used to model the different states of the CeRAM device; Op-amp comparator circuits are used

76

(a) (b)

(c)

Figure 5.29: Full I-V hysteresis measurement showing bi-stable behavior at operating temper-atures (a) -269 C (b) 25 C and (c) 150 C.

to provide the logic for the RS latch to determine if the next operation to be performed is

Set or Reset. The schematic representation of the part and simulation results of the CeRAM

model are shown in Figures 5.30 and 5.31 respectively.

The comparator circuit responsible for determining if a SET or RESET input was pro-

vided to the CeRAM and therefor indicate the current state of the CeRAM device needs to

detect if an input is within a particular range. For this one Op-amp is used to determine if

the input is above a particular level and the other Op-amp is used to determine if the input is

below a particular level. The tolerance range of these levels is controlled through the voltage

77

OA1

OA2

OA3

OA4

AND1

AND2

R1

R2

R3

R4

LTCH1

SW1

INPUT

Vreset

Vset

OUTPUT

Figure 5.30: Circuit schematic representation for CeRAM SPICE model

divider of resistors R1 and R2 using the following equation:

R2 =R1 (1−X)

X(5.13)

where

X =T

1.05(5.14)

and T is the percent tolerance. In order to provide sufficient voltage for the upper tolerance

level the source voltage must be set using the following equation:

VS = VREF

(

1 +T

2

)

(5.15)

where VREF is either VSET or VRESET and 0 < T < 1. Similarly the tolerance range for

the RESET comparator can be controlled through R3 and R4. Both the SET and RESET

comparator circuits output +5V signals when the input is in range and 0V otherwise. these

signals are compatible with the logic levels used for the AND gates and RS Latch used in

the CeRAM model. The truth table for the SR latch in table 5.1 shows that when the set

78

comparator outputs +5V, the SR latch is set and the output Q is +5V. However, if the input

voltage is at VRESET then the reset comparator output is at +5V which resets the latch and the

output Q is 0V. If the input is not within either threshold for set or reset then both comparators

are at 0V and the SR latch maintains the current state. There is potential for instability if

somehow both the S and R inputs of the latch were high however, since it is not possible for the

input to the circuit to be in the range of both VSET and VRESET simultaneously the unstable

case can never occur and can thus be ignored.

Table 5.1: SR Latch Truth Table

S R Q Q’

1 0 1 00 0 1 0 keep current state0 1 0 10 0 0 1 keep current state1 1 0 0 unstable

Up to this point we have described the comparison and state memory portion of the

CeRAM circuit but the actual resistance states are are implemented using a simple voltage-

controlled switch. The Q output from the SR latch controls the switch and the RON and

ROFF resistances are arbitrarily assigned to meet the specifications of current sample data.

The following excerpt from the spice model shows that the default values for RON and ROFF

are 1kΩ and 1MΩ respectively.

.MODEL SCERAM VSWITCH (VT =2.5 V RON =1k ROFF =1 MEG )

The threshold voltage VT of the switch is set at +2.5V because it falls at the midpoint of

the output from the SR latch which is either +5V for SET or 0V for RESET. The complete

SPICE model can be found in appendix A listing A.4.

The simulation results in figure 5.31 show the input signal and output response of the

CeRAM circuit model for a pulsed input. The sequence in the simulation is a SET pulse

followed by a read pulse followed by a RESET pulse and lastly another read pulse. As you can

79

Figure 5.31: Pulse simulation of CeRAM cell (Note: Spice Netlist forCeRAM Cell in Appendix A listing A.5 )

see in the simulation there appears to be some time delay between when the VSET value and

VRESET values are reached. This is an artifact of the Spice simulation and is due to the way

Spice compilers handle input stimulus. When a pulse signal is input using a piecewise linear

source, the signal is interpolated between indicated data points which requires some internal

calculations and thus time. There are several factors that can however be adjusted to speed

up the simulation time which are the tolerances for determining VSET and VRESET as well as

the set and reset reference voltages.

A schematic representation of two 4x4 array architectures is shown in figure 5.32 (a),

and (b). These figures represent a standard 1T1R configuration (a), and a common source

configuration (b) in which the footprint of the compliance/select transistors is reduced by

overlapping the source region of parallel transistors between bit rows. Figure 5.33 shows a

graphical representation of the input stimulus file used for simulating a 4x4 array of 1T1R

memory cells. The top plot is the actual programming pulse sequence which follows the Set

80

M1

CMOSN

U1

CERAM

M2

CMOSN

U2

CERAM

M3

CMOSN

U3

CERAM

M4

CMOSN

U4

CERAM

M5

CMOSN

U5

CERAM

M6

CMOSN

U6

CERAM

M7

CMOSN

U7

CERAM

M8

CMOSN

U8

CERAM

M9

CMOSN

U9

CERAM

M10

CMOSN

U10

CERAM

M11

CMOSN

U11

CERAM

M12

CMOSN

U12

CERAM

M13

CMOSN

U13

CERAM

M14

CMOSN

U14

CERAM

M15

CMOSN

U15

CERAM

M16

CMOSN

U16

CERAM

BL1

BL2

BL3

BL4

WL

1

WL

2

WL

3

WL

4

RL1

RL2

RL3

RL4

(a) standard 4x4 array in 1T1R configuration

M1

CMOSN

U1

CERAM

M2

CMOSN

U2

CERAM

M3

CMOSN

U3

CERAM

M4

CMOSN

U4

CERAM

M5

CMOSN

U5

CERAM

M6

CMOSN

U6

CERAM

M7

CMOSN

U7

CERAM

M8

CMOSN

U8

CERAM

M9

CMOSN

U9

CERAM

M10

CMOSN

U10

CERAM

M11

CMOSN

U11

CERAM

M12

CMOSN

U12

CERAM

M13

CMOSN

U13

CERAM

M14

CMOSN

U14

CERAM

M15

CMOSN

U15

CERAM

M16

CMOSN

U16

CERAM

BL

1

BL

2

BL

3

BL

4

WL1

WL2

WL2

WL4

Vref1

Vref2

(b) 4x4 array with common source 1T1R configura-tion

Figure 5.32: Circuit schematic representation of CeRAM memory array in standard and com-mon source 1T1R configurations

→ Read → Reset → Read programming sequence. The bottom plot shows the word line bias

input on the gate of the compliance/select transistors. The simulation results for the 1T1R

0µs 40µs 80µs 120µs 160µs 200µs 240µs 280µs 320µs 360µs 400µs0.0V

0.6V

1.2V

1.8V

2.4V

3.0V

0.0V

0.4V

0.8V

1.2V

1.6V

2.0V

V(wl1) V(wl2) V(wl3) V(wl4)

V(bl1)

Figure 5.33: simulation input stimulus for simulation 4x4 array in 1T1R circuit configuration

array are shown separated by word line in figure 5.34. Note the presence of a spike in current

at the rising edge of the set pulse output signal. This spike in current is due to the fact that

simulation of the CeRAM cell is essentially a switch with two linear resistors as the different

81

states of the device. When the switch transitions from high resistance to low resistance this

spike occurs in the simulation results. Observationally there is some overshoot of the drain

current when testing single 1T1R circuits in a discrete configuration as it was done in previous

sections due to the high resistance of the OFF state and the parasitic capacitance present in

such a testing configuration but the simulation results show much larger overshoot than is

actually observed in implementing such a circuit configuration. All of the SPICE simulation

netlist files can be found in Appendix A to replicate these results.

0µs 40µs 80µs 120µs 160µs 200µs 240µs 280µs 320µs 360µs 400µs-70µA

70µA

210µA

350µA

490µA

630µA

770µA

-70µA

70µA

210µA

350µA

490µA

630µA

770µA

-70µA

70µA

210µA

350µA

490µA

630µA

770µA

-70µA

70µA

210µA

350µA

490µA

630µA

770µA

Ix(U13:TE) Ix(U14:TE) Ix(U15:TE) Ix(U16:TE)

Ix(U9:TE) Ix(U10:TE) Ix(U11:TE) Ix(U12:TE)

Ix(U5:TE) Ix(U6:TE) Ix(U7:TE) Ix(U8:TE)

Ix(U1:TE) Ix(U2:TE) Ix(U3:TE) Ix(U4:TE)

Figure 5.34: Simulation output for 4x4 array in 1T1R circuit configuration (Note: Spice Netlistfor CeRAM 1T1R 4x4 array in Appendix A listing A.6)

5.4.2 device modeling

The CeRAM device structure in it’s essence is a simple two terminal MIM device which

mathematically can be represented as a transfer function with the solution of that transfer

function being a total device current or current density for design considerations. The compo-

nent parts of the current equation can be seen if figure 5.35. The total current is a combination

of the MIM diode current which represents the current in the insulating state and phase cur-

82

Figure 5.35: Schematic representation of the CeRAM I-V device model.

rents which are dependent on the Hubbard U and represent the current at the onset of a SET

and during the conductive state up to the point of a RESET.

Lets first start the modeling process by looking at some I-V curves of a CeRAM device

plotted specifically to fit within some standard MIM diode equations. Figure 5.36 shows

experimental I-V data collected for a 25µm2 CeRAM device plotted against the thermionic

emission dominated current plot, Poole-Frenkel tunneling dominated current plot, and√V

dependent current for both the LRS and HRS states. Thermionic emission is demonstrated

by a characteristic linearity in the semi-log plot of I vs. V 1/2 whereas Poole-Frenkel tunneling

is characterized by a linear behavior in the semi-log plot of I/V vs. V 1/2. both plots are quite

similar and need to be studied to find the best model that fits the I-V characteristics observed

during testing. as you can see from the plot in 5.36a, the HRS current is quite linear through

the curve just up to the point where a set occurs which indicates that thermionic emission is

the dominant mechanism controlling the CeRAM device in the off state. However, the LRS

current does not appear nearly as linear in the thermionic emission plot indicating a different

mechanism controlling the on state of CeRAM. Figure 5.36b shows that the LRS of CeRAM

is in fact quite linear in the Poole-Frenkel plot which would typically be a great indicator

that the on state current is dominated by Poole-Frenkel tunneling if not for the fact that the

slope tends toward negative and the plot is more ln(I/V ) ∝ −C√V + B dependent than it

is ln(I/V ) ∝ C√V . During analysis of the data, it was fairly quickly observed that the LRS

showed a rather strong square root dependence that fit better than the other two models and

can be observed by the linearity of the LRS in 5.36c.

83

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.410-6

10-5

10-4

10-3

10-2

Cur

rent

(A)

V1/2(V)1/2

LRS HRS

(a) Thermionic emission plot

0.0 0.2 0.4 0.6 0.8 1.0 1.210-5

10-4

10-3

10-2

10-1

Con

duct

ance

(I/V

)

V1/2(V)1/2

LRS HRS

(b) Poole-Frenkel tunneling plot

0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.40.0

2.0x10-4

4.0x10-4

6.0x10-4

8.0x10-4

1.0x10-3

1.2x10-3

1.4x10-3

1.6x10-3

1.8x10-3

2.0x10-3

Cur

rent

(A)

V1/2(V)1/2

LRS HRS

(c)√V dependent plot

Figure 5.36: (a) Thermionic emission limited diode current dominating the behavior in thehigh resistance state and (b) Poole-Frenkel limited tunneling current, and (c) a square rootdependence dominating the low resistance state.

Let us start with the equation for total current density:

JTotal = JMIM + Jφ [Θ(V − VReset)] , (5.16)

where JMIM is analogous to a leakage current in any MIM device and Jφ is the electronic phase

transition current. This equation utilizes a simple unit step function to incorporate both states

84

of the device.

Θ(x− y) =

1, if x = y

0, if x 6= y

The reason for Θ is we can not consider the current for both VReset and VSet simultaneously

but we need to account for both JMIM in the ON state and OFF state. Additionally, since

JMIM for VSet (i.e. the OFF state) is small, it can be neglected from the equation all together.

Now lets consider the possible cases for the phase change current:

Jφ =

JOhmic, if U = 0

0, if U 6= 0.

However, we never actually observe Jφ = 0 since Jφ << JMIM and thus JMIM dominates the

equation at that point. Therefor, 5.16 can be re-written as:

JTotal = Jφ + JMIM (5.17)

where:

JMIM = Jth + Jtun (5.18)

recalling from Chapter 4 that the thermal limited current is:

Jth = AthT2e−ϕ′/kT (1− e−eV/kT ) (5.19)

where

Ath =4πmek2B

h3(5.20)

and the tunneling limited current is:

Jtun = J0

ϕe−Atunϕ1/2 − (ϕ+ eV )e−Atun(ϕ+eV )1/2

(5.21)

where

J0 =e

2πh(β∆s)2(5.22)

85

and

Atun =4πβ∆s

√2m

h(5.23)

which leads to the general equation for the high resistance state of CeRAM to be

JMIM = AthT2e−ϕ′/kT (1− e−eV/kT ) + J0

ϕe−Atunϕ1/2 − (ϕ+ eV )e−Atun(ϕ+eV )1/2

. (5.24)

For the phase transition portion of the equation,

Jφ =2q

h

∫(

Γ1Γ2

Γ1 + Γ2

)

(f(E)− f(E − eV ))ρ−σ(E)dE (5.25)

is the current caused by screening derived phase transitions. In our case the coupling constant

Γ can be assumed the same for the left and right side of the MIM structure so:

Γ0 = Γ1 = Γ2

and

Γ1Γ2

Γ1 + Γ2=

Γ20

2Γ0=

Γ0

2

and the equation for Jφ can be simplified and re-written into:

Jφ =q

h

∫

Γ0(f(E)− f(E − eV ))ρ−σ(E)dE. (5.26)

Jφ ∝√

VApplied in the on state and so it follows that the maximum current in the CeRAM

device would be

JMax ≡ JOhmic = Jφ(U = 0) + JMIM ⇒ JMax = Jφ(U = 0) (5.27)

since JMIM ≈ 0 when the CeRAM is fully screened.

For the case where JMIM 6= 0 we consider the result from 4.1.2 (equation 4.16) for

reducing the tunneling current equation. This result gives us

JMIM = −J0eV

2exp

(

A(eV/2)1/2)

(5.28)

86

and if we take the natural log of both sides we get

ln(J) = − ln

(

J0eV

2exp

(

A(eV/2)1/2)

)

= − ln

(

J0eV

2

)

+A

(

eV

2

)1/2

. (5.29)

If we assume that

ln

(

J0eV

2

)

→ 0

then

ln(J) ∝ CV 1/2 (5.30)

where the constant C = A(e/2)1/2. This gives us the ln(J) vs.√V relationship that we see in

the I-V curves for the OFF state in figure 5.36a.

The key variable for the device model is Jφ, because in it is the Mott (or charge transfer)

model discussed here as the simple version of the Hubbard Hamiltonian for infinitely narrow

bands.

As described before, to get the current we need to use the DOS for electron-electron

interactions from the previous chapter

ρσ =−1

πIm(G) (5.31)

so that when U = 0, (〈nσ〉 = 0), Σ = 0, and if ρ = ρ0 we are in the ohmic regime and Jφ ∼= σE.

When Σ = U 〈nσ〉 f(U) = Uf(U) for U 6= 0, f(U) will have a pole at the point which the

transition occurs from the insulating state to the conductive state.Nolting and Brewer [58]

For the conductive region or on state current, the key point is to calculate the local

DOS (LDOS). LDOS only appears in very thin devices and is a local phenomenon at interface

surfaces and in thin structures. The current can be derived from LDOS equation:

ρ0(E) =1

N

∑

K

δ(E − (E(k)− µ)) (5.32)

and takes the form of

J = C(e−qV/kT − 1)√

E + qV . (5.33)

87

A complete derivation of 5.33 can be found in appendix B.3.

When the interaction is switched on adiabatically, the second electron occupying the

3d9 orbital is responsible for the Σ ≈ U , This new bound state can be used as the switch

off (switch U on) by letting Σ = PbU where Pb is the probability of a bound state where

Rc >> aB in terms of screening by the free electrons and can show (Nolting and Brewer [58])

that the Thomas-Fermi screening length is λTF = 0.44√Rs. The probability of a bound state

as Rs → aB can be described by

Ψ∗bΨb ∝ sin2 λTFKb. (5.34)

Where Kb is the state vector of the bound state. If Rs → 1, λTF → aB and the bound state is

destroyed. But, if λ >> aB the metal becomes an insulator as the bound state interacts with

the other electron in the 3d9,10 orbital via the repulsive interaction energy U . To incorporate

this into the conductive state current we use a step function with the knowledge that a critical

repulsive energy is achieved when the input voltage is equal to the interaction energy term U .

Now, 5.33 becomes

J = C(e−qV/kT − 1)√

E + qVΘ(Vreset − V ) (5.35)

where Vreset ∝ U/e.

At this point we can now combine all of the pieces of the CeRAM device model to

generate a quite familiar I-V behavior for a positive applied bias. To do this plot the equation

for the ON state current 5.35 with the OFF state current equations for JMIM 5.24 and the

simplified diode current at the Fermi-level 4.26 from chapter 4. Figure 5.38 shows the CeRAM

device model for both the On state square root dependent current and the Off state current

which is a combination of thermionic emission through the M-I contact, electron tunneling

through the MIM diode barrier, and the off state diode current at the Fermi-level.

It is clear that the simulated results agree with the empirical data and that the model

theorization that the set operation occurs just as the barrier is overcome and electron movement

88

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

1

2

3

4

5

6

7x 10

−3

Applied Bias (V)

Cur

rent

(A

)

Figure 5.37: Conductive state current of a CeRAM element vs. appliedbias.(Note: See Appendix A listings A.3 for MATLAB code.)

0 0.5 1 1.50

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Applied Bias (V)

Cur

rent

Den

sity

(A

/cm

2 )

J

OFF

JON

(a) Linear plot of the Total CeRAM Device model.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.610

−12

10−11

10−10

10−9

10−8

10−7

10−6

10−5

10−4

10−3

10−2

10−1

100

101

102

103

104

105

Applied Bias (V)

Cur

rent

Den

sity

(A

/cm

2 )

JOFF

JON

(b) Semilog plot of the Total CeRAM model.

Figure 5.38: CeRAM device model for both the ON state current density and the OFF statecurrent density models shown in both linear and semilog plots for a CeRAM device with barrierthickness s = 90nm barrier height ϕ = 1.5eV , and T = 300K. (Note: See Appendix A listingsA.2 and A.3 for MATLAB code.)

through the device becomes ballistic. This occurs when Vapplied = VSET where Vset = U/nce

89

and the simulated data agrees quite well with experimental data. In the ON state of the device

the square root dependence is also shown well in the plotted representation of equation 5.33.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.60

1000

2000

3000

4000

5000

6000

7000

8000

Applied Bias (V)

Cur

rent

Den

sity

(A

/cm

2 )

J

ON(exp)

JON

(model)

JOFF

(exp)

JOFF

(model)

(a)

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.610

1

102

103

104

105

Applied Bias (V)

Cur

rent

Den

sity

(A

/cm

2 )

JON

(exp)

JON

(model)

JOFF

(exp)

JOFF

(model)

(b)

Figure 5.39: Modeled and Experimental J-V characteristics for CeRAM plotted on a linearscale (a) and a semilog scale (b).

In order to make a direct comparison of experimental J-V data with the device model

characteristics, experimentally collected data was imported into MATLAB and the model

parameters were adjusted to fit the data curves. For the ON state current, the only parameter

that needed to be modified was the scaling factor C from equation 5.37 which was increased

to 7000 where as in previous plots, C was set to 1. This scaling factor comes from the fact

that JON ∝ JCompliance where JON in this case is larger than JCompliance due to parasitic

capacitance in the testing setup and the device itself which causes more current to flow across

the CeRAM device than was actually intended by the compliance level. In the OFF state, The

fitting process consisted of scaling the baseline current value J0 from the diode equation near

the Fermi level 4.26 as well as adding an ideality factor n to the equation which was previously

assumed to be 2 for a non-ideal diode. The new equation for the simplified diode current which

dominates the OFF state prior to SET is:

Jφ(fermi) = J0

(

eqV/nkT − 1)

. (5.36)

90

The results of the model fitting are shown in figure 5.39. These results clearly show an ex-

cellent fit of the device model proposed in this thesis to that of experimentally collected data

confirming validity of the model for CeRAM devices.

Chapter 6

Summary and Outlook

The basic concept of CeRAM has been presented in this thesis to be a non-filamentary

resistive RAM in which the switching properties of the transition metal oxide (TMO) com-

pounds that could otherwise be negatively affected by non-stoichiometry and defects in the

crystal structure are repaired through doping with natural ligands of carbonyl (CO)x and

metal-carbonyl’s Mz(CO)y. Once the TMO structure has been properly compensated the

e–−e– interaction or repulsion can then be exploited for the switching and memory functions.

The presence of carbonyl ligands in these NiO films as a result of the deposition method was

investigated using crystallographic and chemical analysis and has not only been confirmed in

the films but that carbon content can be easily tuned by simply changing the molarity of the

precursor solution and the total number of spun on layers (See figure 5.11).

The fabrication process for NiO based CeRAM devices using a chemical solution de-

position method commonly referred to a spin-on deposition, with metallization done by DC

sputtering and etching by dry ion bombardment or ion milling has been established. the ba-

sic switching characteristics of CeRAM structures and devices has been investigated. A wide

operating range from -269 C to 150 C and nonvolatile data retention at temperatures up

to 300 C has been demonstrated. Sub-100µA operation has been confirmed for relatively

large devices using external compliance circuitry and predictions have been made for switching

parameters down to a 32nm technology node.

In chapters 3 & 4 the necessary background information to build an understanding of the

92

metal-insulator transitions induced by electron density variations during quantum tunneling

of electrons and holes was provided. Starting with a review of Hubbard-Mott theory and the

physics of the infinitely narrow Hubbard Hamiltonian and it’s application to quantum transport

in CeRAMs. The MIM diode and transport current models that created the fundamental pieces

of the CeRAM model are presented and their relevancy in modeling such devices confirmed. It

his here that the electron density variations responsible for the MIT and it’s reversal have been

discussed and the Mott criteria in which the critical number of electrons necessary to induce

a IMT is established as aBn1/3c

∼= 0.26 which is necessary for the disproportionation reaction

(d8 + d8 → d7 + d9) to occur. The density of states equation that governs the CeRAM model

for systems with interacting electrons has been shown to be

ρσ = ρ0[E − Σσ(E − µ)].

where if Σ ∼= 0, we have a metal and for Σ ∼= U we have an insulator.

In chapter 4 we are able to use the mechanisms and density parameters established

in chapter 3 to derive the current equations that were later utilized in the CeRAM model.

In the MIM diode, the I-V characteristics are affected both by thermal effects through the

Metal Insulator interfaces and tunneling effects through the barrier. It was shown that up to

just before the point where the barrier is overcome by electron injection, the thermal affected

current dominates the diode behavior. However, at a critical point, tunneling effect takes over

and electron transfer becomes nearly ballistic. The total equation representing the MIM diode

is

JMIM = AthT2e−ϕ′/kT (1− e−eV/kT ) + J0

ϕe−Atunϕ1/2 − (ϕ+ eV )e−Atun(ϕ+eV )1/2

.

The phase limited tunneling current which is necessary to represent the resistive state of the

CeRAM element near the IMT energy level was shown to be

Jφ(fermi) = J0

(

eqV/kT − 1)

.

which is, the current density near fermi level.

93

Chapter 5 is where all of the previous concepts come together to describe CeRAM storage

device from concept to fabrication, modeling, and simulation. A. electrical testing methodology

has been established for both collecting I-V data using voltage sweeps in a more parametric

testing mode, as well as for pulse testing in more of a memory testing mode including potential

compliance circuitry which is critical to controlling the amount of current that flows through

a CeRAM during the SET operation and can affect fatiguing and power consumption in a

memory application.

The fabrication process for NiO based CeRAM devices using a chemical solution de-

position method commonly referred to a spin-on deposition, with metallization done by DC

sputtering and etching by dry ion bombardment or ion milling has been established. the ba-

sic switching characteristics of CeRAM structures and devices has been investigated. A wide

operating range from -269 C to 150 C and nonvolatile data retention at temperatures up

to 300 C has been demonstrated. Sub-100µA operation has been confirmed for relatively

large devices using external compliance circuitry and predictions have been made for switching

parameters down to a 32nm technology node.

A spice model that can be used for circuit simulation in which the fundamental behavior

of a CeRAM device is that it is a device capable of two distinct resistances was created by

combining an RS latch with supporting sense-amps and a voltage controlled switch. by looping

the output of the RS latch back to its input it is possible to create as simulated memory

effect and the remainder of the CeRAM memory elements can be tested against the different

resistance states and for different switching times.

A physical model has been presented that combines the generalized forms of thermionic

and tunneling limited current presented by Simmons [60, 61] with a phase limited current

model that utilizes the Meir-Wingreen formula for hole current in the conductive phase and

tunneling current in the resistive phase. The device model was compared to experimental data

and after the fitting process, and adjustments to the scaling constants, it was confirmed to be

an exceptional fit to the data confirming the validity of the presented model.

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Appendix A

Code for simulations

Listing A.1: MATLAB code for Potential barrier in MIM diode structure

1 %Physical Constants

2 e=1.60e-19;

3 kB =8.61733e-5;

4 h=4.1357e-15;

5 m=9.109e-31;

6 %##########################################################################

7 %Input Parameters

8 n=1000; %Step count

9 s=90; %Thickness (nm)

10 x=0:s/n:s; %Position (nm)

11 x2=0;

12 K=1; %Permittivity

13 B=1;

14 V=1;

15 T=300;

16 Phim1 =1; %Metal work function Left(eV)

17 Phim2 =1; %Metal work function Right(eV)

18 phi1 =1; %Barrier height left

19 phi2 =1; %Barrier height right

20 %##########################################################################

21 %Barrier equations

22 dPhi=Phim1 -Phim2; %Metal work function delta (eV)

23

24 phi=phi1+(dPhi -V).*(x./s); %Potential Energy (eV)

25 Vim = -2.88.*s./(K*x.*(s-x)); %Image Potential (eV)

26 Vtot=phi+Vim; %Total Potential

27

28 for K=1:4,

29 phi=phi1+(dPhi -V).*(x./s); %Potential Energy (eV)

30 Vim = -2.88.*s./(K*x.*(s-x)); %Image Potential (eV)

31 Vtot=phi+Vim; %Total Potential

32 end

Listing A.2: MATLAB code for Thermionic and tunneling current

1 clear all

2 %Physical Constants

102

3 e=1.60e-19;

4 kB=1.38e-23;

5 h=6.63e-34;

6 m=9.109e-31;

7 %##########################################################################

8

9 %Input Parameters

10

11 n=1000; %Step count

12 s=90; %Thickness (nm)

13 x=0:s/n:s; %Position (nm)

14 x2=0;

15 K=1; %Permittivity

16 B=1;

17 V=1.5;

18 Vapp =0:(1.5)/n:1.5;

19 T=300;

20 Phim1 =1.5; %Metal work function Left(eV)

21 Phim2 =1.5; %Metal work function Right(eV)

22 phi1 =1.5; %Barrier height left

23 phi2 =1.5; %Barrier height right

24 %##########################################################################

25

26 %Barrier equations

27 dPhi=Phim1 -Phim2; %Metal work function delta (eV)

28

29 phi=phi1+(dPhi -V).*(x./s); %Potential Energy (eV)

30 Vim = -2.88.*s./(K*x.*(s-x)); %Image Potential (eV)

31 Vtot=phi+Vim; %Total Potential

32

33 phip=phi1 -( realsqrt (14.4*(7+ Vapp*K*s)))/(K*s);

34 %##########################################################################

35

36 Ath =(4*pi*m*e*kB^2)/h^3;

37 Atun =(4*pi*B*s*10^ -10/h)*realsqrt (2*m);

38

39 J0=e/(2*pi*h*(B*s*10^ -9) ^2);

40

41 fun = @(x2) phi1+(dPhi -V).*(x2./s);

42 F=integral(fun ,0,s);

43 phibar =(1/s)*F;

44 %##########################################################################

45

46 %Current density due to thermionic emission

47 phip=phip*e; %convert barrier back to SI units

48

49 Jth=Ath*T^2* exp(-phip/(kB*T)).*(1-exp(-(e*Vapp)/(kB*T)));

50

51 %Current density due to tunneling

52 phibar=phibar*e*2.001; %convert to SI units + set average barrier

53 %height so phibar -eV is never negative.

54

55 Jtun=J0*(( phibar -(e*Vapp)).*exp(-Atun*realsqrt ((phibar -(e*Vapp))))...

56 -phibar*exp(-Atun*realsqrt(phibar)));

57

58

59

60 Jtot=Jth+Jtun;

103

Listing A.3: MATLAB code for phase current

1 clear all

2 %Physical Constants

3

4 e=1.60e-19;

5 kB=1.38e-23;

6 h=6.63e-34;

7 m=9.109e-31;

8 %##########################################################################

9 %Input Parameters

10

11 n=1000; %Step count

12 Vapp =0:(1.5)/n:1.5;

13 T=300;

14 Vt=kB*T/e; %Thermal Voltage

15 J_0=1e-13; %Baseline Diode current

16 %##########################################################################

17

18

19 %Simplified current density for the phase transition in the OFF state

20 J_Diode=J_0*(exp(Vapp /(2*Vt)) -1);

21

22 %Current density for the phase transitionin the ON state

23 J_ON=J_Diode+abs(exp(-Vapp /(2*Vt)) -1).* realsqrt(Vapp)...

24 .*(1- heaviside(Vapp -0.7));

Listing A.4: CeRAM SPICE model

1 .SUBCKT CERAM 5 10

2 *PINS INPUT OUTPUT

3 VCC 1 0 5.0V

4 VSET 2 0 2V ;original value 5.3V

5 VRESET 3 0 1V ;original value 2.2V

6

7 XCSET 1 2 5 6 COMPMARG

8 XCRESET 1 3 5 7 COMPMARG

9

10 XLSTATE 1 6 7 8 9 RSLATCH

11

12 SCERAM 5 10 8 0 SCERAM OFF

13

14 .ENDS

15

16 .SUBCKT COMPMARG 1 2 5 10

17 *PINS: VCC , VREF , VIN , STATE

18

19 R1 2 6 600 ;original value 1k

20 R2 6 0 4.7K ;original value 9.5k

21

22 XCOMP1 2 5 7 COMPARATOR

23 XCOMP2 5 6 8 COMPARATOR

24

25 XNAND1 7 8 9 1 NAND

26 XNOT 9 10 1 NOT

27

28 .ENDS

104

29

30 .SUBCKT RSLATCH 1 2 3 6 7

31 *TERMINALS VCC R S Q QNOT

32 XNOT1 2 4 1 NOT

33 XNOT2 3 5 1 NOT

34 XNAND1 4 7 6 1 NAND

35 XNAND2 5 6 7 1 NAND

36 .NODESET V(6)=0V V(7)=5V

37 .ENDS

38

39 .SUBCKT NAND 1 2 3 4

40 * TERMINALS A B OUT VCC

41 RL 3 4 500

42 CL 3 0 10PF

43 S1 3 5 1 0 SW

44 S2 5 0 2 0 SW

45 .ENDS

46

47 .SUBCKT NOT 1 3 4

48 * TERMINALS A OUT VCC

49 RL 3 4 500

50 CL 3 0 10PF

51 S1 3 0 1 0 SW

52 .ENDS

53

54 .SUBCKT COMPARATOR 2 4 6

55 *TERMINALS INPUT+, INPUT -, OUTPUT

56 * COMPARATOR

57 R1 2 3 1K

58 XOP2 3 4 5 OPAMP1

59 RLIM 5 6 1000

60 D1 0 6 DZ1

61 .ENDS

62

63 *OP -AMP

64 .SUBCKT OPAMP1 1 2 6

65 * INPUT IMPEDANCE

66 RIN 1 2 10MEG

67 * DC GAIN =100K AND POLE1 =100HZ

68 * UNITY GAIN = DCGAIN X POLE1 = 10MHZ

69 EGAIN 3 0 1 2 100K

70 RP1 3 4 100K

71 CP1 4 0 0.0159 UF

72 * ZENER LIMITER

73 D1 4 7 DZ0

74 D2 0 7 DZ0

75 * OUTPUT BUFFER AND RESISTANCE

76 EBUFFER 5 0 4 0 1

77 ROUT 5 6 10

78 *

79 * 15V ZENER DIODE MODEL

80 .MODEL DZ0 D(Is=0.05u Rs=0.1 Bv=15 Ibv =0.05u)

81 .ENDS

82

83

84 * ZENER DIODE MODEL

85 .MODEL DZ1 D(Is=0.05u Rs=0.1 Bv =4.685 Ibv =0.05u)

86 .MODEL DZ2 D(Is=0.05u Rs=0.1 Bv =4.685 Ibv =0.05u)

105

87

88 .MODEL SW VSWITCH(VON=3 VOFF=2 RON =10 ROFF =100K)

89

90 .MODEL SCERAM VSWITCH(VT=2.5V RON=1k ROFF=1MEG) ;original RON=1k

91

92 ****************** TRANSISTOR MODELS *******************

93

94 .MODEL MOD1 NMOS(LEVEL =3 VTO =0.5 LD=0.1u TOX=80E-10 NSUB=1E16)

Listing A.5: Spice Netlist for CeRAM Cell

1 * C:\ Documents and Settings\Chris.SYMETRIXCORP\My Documents\CeRAM\Spice\

LTspice\CeRAM_Cell.asc

2 XU1 VT 0 CERAM

3 V1 VT 0 PWL(0 0 10u 0 11u 2V 20u 2V 21u 0V

4 + 30u 0V 31u 0.5V 40u 0.5V 41u 0V

5 + 50u 0V 51u 1V 60u 1V 61u 0V 70u 0V

6 + 71u 0.5V 80u 0.5V 81u 0V 90u 0V)

7 .lib CeRAM.lib

8 .tran 100US

9 .backanno

10 .end

Listing A.6: Spice Netlist for CeRAM 1T1R 4x4 array

1 * C:\ Documents and Settings\chris\My Documents\CeRAM\Spice\LTspice \1T1R\

CeRAM_1T1R_4x4.asc

2 M1 0 WL1 P001 0 CMOSN l=1.6u w=16u m=5

3 XU1 BL1 P001 CERAM

4 M2 0 WL2 P002 0 CMOSN l=1.6u w=16u m=5

5 XU2 BL1 P002 CERAM

6 M3 0 WL3 P003 0 CMOSN l=1.6u w=16u m=5

7 XU3 BL1 P003 CERAM

8 M4 0 WL4 P004 0 CMOSN l=1.6u w=16u m=5

9 XU4 BL1 P004 CERAM

10 M5 0 WL1 P005 0 CMOSN l=1.6u w=16u m=5

11 XU5 BL2 P005 CERAM

12 M6 0 WL2 P006 0 CMOSN l=1.6u w=16u m=5

13 XU6 BL2 P006 CERAM

14 M7 0 WL3 P007 0 CMOSN l=1.6u w=16u m=5

15 XU7 BL2 P007 CERAM

16 M8 0 WL4 P008 0 CMOSN l=1.6u w=16u m=5

17 XU8 BL2 P008 CERAM

18 M9 0 WL1 P009 0 CMOSN l=1.6u w=16u m=5

19 XU9 BL3 P009 CERAM

20 M10 0 WL2 P010 0 CMOSN l=1.6u w=16u m=5

21 XU10 BL3 P010 CERAM

22 M11 0 WL3 P011 0 CMOSN l=1.6u w=16u m=5

23 XU11 BL3 P011 CERAM

24 M12 0 WL4 P012 0 CMOSN l=1.6u w=16u m=5

25 XU12 BL3 P012 CERAM

26 M13 0 WL1 P013 0 CMOSN l=1.6u w=16u m=5

27 XU13 BL4 P013 CERAM

28 M14 0 WL2 P014 0 CMOSN l=1.6u w=16u m=5

29 XU14 BL4 P014 CERAM

30 M15 0 WL3 P015 0 CMOSN l=1.6u w=16u m=5

106

31 XU15 BL4 P015 CERAM

32 M16 0 WL4 P016 0 CMOSN l=1.6u w=16u m=5

33 XU16 BL4 P016 CERAM

34 .model NMOS NMOS

35 .model PMOS PMOS

36 .lib C:\ Program Files\LTC\LTspiceIV\lib\cmp\standard.mos

37 * Johns and Martin models for 0.8 micron process jl feb 2008

38 .MODEL CMOSN NMOS LEVEL=3,TOX =1.8E-8,LD=0.08U,UO=500, VMAX =2.0E5 ,PHI=0.6,

39 +GAMMA =0.5, NSUB =2.5E16 ,VTO=0.7,NFS =8.2E11 ,CGSO =2.5E-10,CGBO =2.5E-10,

40 +CJSW =2.5E-10,CGDO =2.5E-10,MJ=0.5,CJ=2.5E-4,PB=0.9,IS=1.0E-16,

41 +JS=1.0E-4,KF=600E-27, AF=0.8, NLEV=2,RS=600,RD=600,

42 +ETA =0.05 , KAPPA =0.007 , THETA =0.06 , XJ=2.7E-7, DELTA =0.7

43 .MODEL CMOSP PMOS LEVEL=3,TOX =1.8E-8,LD=0.08U,UO=165, VMAX =2.7E5 ,PHI =0.80 ,

44 +GAMMA =0.75 , NSUB =5.5E16 ,VTO=-0.7,NFS =7.6E11 ,CGSO =2.5E-10,CGBO =2.75E-10,

45 +CJSW =3.4E-10,CGDO =2.5E-10,MJ=0.5,CJ=3.7E-4,PB=0.8, IS=1.0E-16,

46 +JS=1.0E-4,KF=400E-27,AF=1.0, NLEV=2,RS=1200 ,RD=1200 , ETA =0.12 , KAPPA =1.5,

47 +THETA =0.135 , XJ=2.3E-7, DELTA =0.3

48 .include PWL2.txt

49 .lib CeRAM.lib

50 .tran 0 400u 0 1u startup uic

51 .backanno

52 .end

Appendix B

Derivations

B.1 MIM Diode current simplification

Jtun = J0

ϕ exp(−Atunϕ1/2)− (ϕ+ eV ) exp(−Atun(ϕ+ eV )1/2)

Assume as Simmons [60] did for intermediate voltages,

ϕ ∼= ϕ0 −eV

2

then

Jtun = J0

(

ϕ0 −eV

2

)

exp

[

−Atun

(

ϕ0 −eV

2

)1/2]

−(

ϕ0 +eV

2

)

exp

[

−Atun

(

ϕ0 +eV

2

)1/2]

Jtun = J0ϕ0

(

1− eV

2ϕ0

)

exp

[

−Atunϕ1/20

(

1− eV

2ϕ0

)1/2]

−(

1 +eV

2ϕ0

)

exp

[

−Atunϕ1/20

(

1 +eV

2ϕ0

)1/2]

. (B.1)

Assume eV/2 >> 1.

Jtun = J0ϕ0

− eV

2ϕ0exp

[

Atunϕ1/20

(

eV

2ϕ0

)1/2]

− eV

2ϕ0exp

[

−Atunϕ1/20

(

eV

2ϕ0

)1/2]

= −J0eV

2

exp

[

Atunϕ1/20

(

eV

2ϕ0

)1/2]

+ exp

[

−Atunϕ1/20

(

eV

2ϕ0

)1/2]

= −J0eV

2

exp

[

Atun

(

eV

2

)1/2]

+ exp

[

−Atun

(

eV

2

)1/2]

(B.2)

which readily reduces to:

Jtun = −J0eV

2exp

[

Atun

(

eV

2

)1/2]

(B.3)

108

B.2 Tunneling Current

J =2q

h

∫(

Γ1Γ2

Γ1 + Γ2

)

(f(E)− f(E − eV ))ρσdE. (B.4)

If we assume that the coupling constants Γ0 = Γ1 = Γ2 which is true for a system with similarelectrodes, then:

Γ1Γ2

Γ1 + Γ2=

Γ20

2Γ0=

Γ0

2(B.5)

and the equation for tunneling current reduces to:

J =2q

h

∫

Γ0

2(fL(E)− fR(E − eV ))ρσdE. (B.6)

J =q

h

∫

Γ0(∆f)

N

∑

k

δ(E − ε(k)− Σ)dE

=qΓ0

hN

∫

∆f∑

k

δ(E − ε(k)− Σ)dE

=qΓ0

hN

∫

(fL(E)− fR(E − eV ))∑

k

δ(E − ε(k)− µ− Σ)dE

=qΓ0

hN

∑

k

J0 [fL(E − ε(k)− µ− Σ)− fR(E − ε(k)− µ− Σ− qV )]

=∑

k

J0

[

1

exp (E − ε(k)− µ− Σ) + 1− 1

exp (E − ε(k)− µ− Σ− qV ) + 1

]

=∑

k

J0

[

e−β(E−ε(k)−µ−Σ) − e−β(E−ε(k)−µ−Σ−qV )]

=∑

k

J0

(

e−(E−E(k))/kT)(

1− eqV/kT)

(B.7)

B.3 LRS Current equatinon derivation

ρ0(E) =1

N

∑

k

δ(E − (E(k)− µ)) (B.8)

lets set µ = 0 since we are at the Fermi-level.

ρ0(E) =1

N

∑

K

δ(E − E(k)) with E(k) =~2k2

2m+

0V (x) (B.9)

now we change to integration with the knowledge that∑

k →∫

•dk3

109

ρ0(E) =1

N

∑

K

δ(E − E(k))

=1

N

(

V

(2π)3

)∫

δ

(

E − ~2k2

2m

)

dk3

=1

N

(

V

(2π)3

)∫ ∫ ∫

δ

(

E − ~2k2

2m

)

(k cos θ)(k sinφ)dk

=1

N

(

V

(2π)3

)∫ ∞

0K2δ

(

E − ~2k2

2m

)

dk. (B.10)

Now, the trick is to go from

δ(x2 − α2) to1

2|α|(δ(x− α) + δ(x+ α))

δ

(

E − ~2k2

2m

)

= δ

(

~2

2m

(

2mE

~2− k2

))

(B.11)

if we use

δ(αx) =1

|α|δ(x)

then

δ

(

E − ~2k2

2m

)

=2m

~2δ

(

2mE

~2− k2

)

(B.12)

now,2m

~2δ(x2 − k2) =

(

2m

~2

)

1

2|k| δ(x− k) + δ(x+ k) (B.13)

so,

ρ0(E) =1

N

(

V

(2π)3

)∫ ∞

0k2δ

(

E − ~2k2

2m

)

dk

=1

N

(

V

(2π)3

)(

2m

~2

)∫ ∞

0

k

2

δ

(

√

2mE

~2− k

)

+ δ

(

√

2mE

~2+ k

)

dk

ρ0(E) =1

N

(

V

(2π)3

)(

2m

~2

)

1

2

∫ ∞

0kδ

(

√

2mE

~2− k

)

dk (B.14)

using δ(x) = δ(−x)

ρ0(E) =1

N

(

V

(2π)3

)(

2m

~2

)

1

2

∫ ∞

0kδ

(

k −√

2mE

~2

)

dk (B.15)

and finally

ρ0(E) =1

2N

(

V

(2π)3

)(

2m

~2

)

√

2mE

~2(B.16)

which is ρ0(E) = C√E as expected.

110

now for the current equation up to the phase transition in the on state.

σp = q2Dp(ρ0)(E) (B.17)

Jφp =2q

h

∫

((1− fL(E))− (1− fR(E − qV ))) ρ0(E)dE

= −2q

h

∫

(fL(E)− fR(E − qV )) ρ0(E)dE

= −2q

h(fL(E)− fR(E − qV )) ρ0(E)∆E

= −C (fL(E)− fR(E − qV ))√

Ev − E

= −Ce−β(E−EF )(

1− eβqV) [

√

Ev − E(k) + qV]

(B.18)