copyright 2001, agrawal & bushnellvlsi test: lecture 11alt1 lecture 11alt advances in...
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![Page 1: Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 11alt1 Lecture 11alt Advances in Combinational ATPG Algorithms Branch and Bound Search FAN – Multiple](https://reader036.vdocuments.site/reader036/viewer/2022062313/56649d485503460f94a23d40/html5/thumbnails/1.jpg)
Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 1
Lecture 11altAdvances in Combinational
ATPG Algorithms
Lecture 11altAdvances in Combinational
ATPG Algorithms
Branch and Bound Search FAN – Multiple Backtrace, head lines (1983) TOPS – Dominators (1987) SOCRATES – Learning (1988) EST – Search space learning (1991) ATPG Performance improvements Summary
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 2
ATPG: A Boolean Satisfiability Problem
ATPG: A Boolean Satisfiability Problem
CUT
CUTwith fault
f(a,b,c) = 1TestVector(a,b,c)
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 3
SAT is NP-CompleteSAT is NP-Complete
a
cc
bb
1110000 0
cc
0 1
f a b c
fBinary DecisionDiagram (BDD)
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 4
Search for a SolutionSearch for a Solution
Problem: Given a value of a Boolean function of binary variables, find values of the variables.
Solution: Starting at the root, enumerative traversal of the binary decision diagram (BDD) until a solution is found.
BDD is a search tree – search consists of Branch: Set an untried value for a variable
– Backtrack to previous branching point if there is no untried value
Stop if solution found, or backtracked to root without untried values Or, bound search tree for future traversals if solution is impossible and backtrack to previous branching point (some variable orderings may lead to early bounding)
Or, continue
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 5
Example: f = 1Example: f = 1
a
cc
bb
1110000 0
cc
0 1
f a b c
fBinary DecisionDiagram (BDD)
bound
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 6
FAN: Fujiwara and Shimono(1983)
FAN: Fujiwara and Shimono(1983)
New concepts: Unique sensitization Stop Backtrace at head lines Multiple Backtrace
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 7
PODEM Makes Unwise Signal Assignments
PODEM Makes Unwise Signal Assignments
Blocks fault propagation due to assignment J = 0
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 8
Unique Sensitization of FAN with No Search
Unique Sensitization of FAN with No Search
FAN immediately sets necessary signals to propagate fault
Path over which fault is uniquely sensitized
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 9
HeadlinesHeadlines
Headlines H and J separate circuit into 3 parts, for which test generation can be done independently
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 10
Contrasting Decision TreesContrasting Decision Trees
PODEM decision tree
FAN decision tree
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 11
Multiple BacktraceMultiple Backtrace
FAN – breadth-firstpasses –
1 time
PODEM –depth-first
passes – 6 times
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 12
AND Gate Vote Propagation
AND Gate Vote Propagation
AND Gate Easiest-to-control Input:
# 0’s = OUTPUT # 0’s # 1’s = OUTPUT # 1’s
All other inputs: # 0’s = 0 # 1’s = OUTPUT # 1’s
[5, 3][5, 3]
[0, 3]
[0, 3]
[0, 3]
00000
1
1
1
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 13
Multiple Backtrace Fanout Stem VotingMultiple Backtrace Fanout Stem Voting
Fanout Stem -- # 0’s = Σ Branch # 0’s, # 1’s = Σ Branch # 1’s
[5, 1][1, 1][3, 2]
[4, 1]
[5, 1]
[18, 6]
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 14
PODEM Fails to Determine Unique Signals
PODEM Fails to Determine Unique Signals
Backtracing operation fails to set all 3 inputs of gate L to 1 Causes unnecessary search
sa1
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 15
FAN -- Early Determination of Unique
Signals
FAN -- Early Determination of Unique
Signals
Determine all unique signals implied by current decisions immediately Avoids unnecessary search
sa1
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 16
TOPS: DominatorsKirkland and Mercer
(1987)
TOPS: DominatorsKirkland and Mercer
(1987)
Dominator of g – all paths from g to PO must pass through the dominator Absolute -- k dominates B Relative – dominates only paths to a given PO If dominator of fault becomes 0 or 1, backtrack
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 17
SOCRATES: Learning (1988)
SOCRATES: Learning (1988)
Static and dynamic learning: a = 1 f = 1 means that we learn f = 0 a = 0 by applying the Boolean contrapositive theorem
Set each signal first to 0, and then to 1 Discover implications Learning criterion: remember f = vf only if:
f = vf requires all inputs of f to be non-controlling A forward implication contributed to f = vf
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 18
Improved Unique Sensitization Procedure
Improved Unique Sensitization Procedure
When a is only D-frontier signal, find dominators of a and set their inputs unreachable from a to 1
Find dominators of single D-frontier signal a and make common input signals non-controlling
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 19
Constructive DilemmaConstructive Dilemma
[(a = 0) (i = 0)] [(a = 1) (i = 0)] (i = 0) If both assignments 0 and 1 to a make i = 0, then i = 0
is implied independently of a
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 20
EST: Search Space Learning (Giraldi and Bushnell)
EST: Search Space Learning (Giraldi and Bushnell)
E-frontier – partial circuit functional decomposition Equivalent to a node in a BDD Cut-set between circuit part with known labels and part with X
signal labels EST learns E-frontiers during ATPG and stores them in a hash table
Dynamic programming – when new decomposition generated from implications of a variable assignment, looks it up in the hash table
Avoids repeating a search already conducted Terminates search when decomposition matches:
Earlier one that lead to a test (retrieves stored test) Earlier one that lead to a backtrack
Accelerated SOCRATES nearly 5.6 times
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 21
Fault B sa1Fault B sa1
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 22
Fault h sa1Fault h sa1
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Copyright 2001, Agrawal & Bushnell
VLSI Test: Lecture 11alt 23
SummarySummary
Algorithm
D-ALGPODEMFANTOPSSOCRATESWaicukauski et al.ESTTRANRecursive learningTafertshofer et al.
Est. speedup over D-ALG(normalized to D-ALG time)17232921574 ATPG System2189 ATPG System8765 ATPG System3005 ATPG System48525057
Year
1966198119831987198819901991199319951997
†
†
†
†
Performance improvement through 40 years of research.