Coordinator - Prof. Swapna BanerjeeCo-coordinator - Prof. Chitta Ranjan Mandal

SMDP-II Project Report

Sponsored byMinistry of Communication & Information Technology,

New Delhi

Indian Institute of Technology, KharagpurResource Center

Status of Establishment of VLSI Design Lab Laboratory space created : 15 X 7.5 (sq m.) Photograph of VLSI Lab :

Name of the Hardware Percentage of Utilization Status

High end PC Servers 100% Being UsedPC – P4 based 100% Being Used

Misc. Equipments 100% Being Used

Scanner 100% Being Used

Associated Networking 100% Being Used

UPS 100% Being UsedProjector 0% Presently Out

of Order

Hardware Utilization

Name of the Hardware Status % of Utilization

1 HP Color Laserjet Printer Purchased in March 2010

100%

256 MHz Function/Noise Generator Purchased in April 2010

100%

SIGNALMASTER DUAL (LSP155-601) LYRTECH FPGA BOARD,

Purchased in May 2011

100%

Hardware Purchased

EDA Tools Utilization Summary

S. No. Item received

Received Installed No. of persons using

the tool

Utilization Percentage

1 Cadence All Modules All Modules 180 100%

2 Synopsys All Modules All Modules 120* 0%

3 Magma All Modules All Modules 0 0%

4 Mentor All Modules All Modules 40 50%

5 Coware All Modules All Modules 0 0%

6 Xilinx All Modules All Modules 200 100%

*Synopsys licenses are not there till 14th January 2012. Temp licenese for 1 month received on 6th Feb 2012.

Books and Furniture Status

No. of books purchased under SMDP-I – 65

No. of books purchased under SMDP-II – 165 (Till Date) Furniture procured: Steel Almirahs, Computer Tables, Chairs, Sofa-Set.

Website Preparation

Website has been prepared. Address of website: http://www.smdp.iitkgp.ernet.in

The SMDP website has linked with the IIT Kharagpur main website. Address of the website: http://www.iitkgp.ac.in/acad_n_res_fac

NB: ASIC, and FPGA design flow using Xilinx, Cadence, Synopsys video has been uploaded in our website.

IEP Conducted by IIT Kharagpur IEP on VLSI Aspects in Biomedical Engineering (6-12 March 2011) (Coordinator

– Prof. Swapna Banerjee)16 participant attended from RCs and PIs

IEP on Low-Power, High-Speed Digital Subsystem Design: Spec-to-test (1st March-13th March 2010) (Coordinator - Prof. Ajit Pal)

14 participants attended from PIs

IEP on TECHNOLOGY CAD (12th May-17th May 2008) (Coordinator - Prof. C.K. Maity)

IEP on VLSI-DSP based design (24th Sep-5th Oct 2007) (Coordinator - Prof. Swapna Banerjee)

IEP on Low Power VLSI Design (11th Sep-22nd Sep 2006) (Coordinator- Prof. Ajit Pal & Prof. Swapna Banerjee)** All IEP materials are uploaded in our website (www.smdp.iitkgp.ernet.in)

CAD Tool Training Conducted at IIT Kharagpur

N/A in 2011-2012

10

International Guest Faculty Workshop

Name of the Guest Faculty

University/ Institution Affiliation

Date and Duration of the Workshop

1. Prof. Wouter A. Serdijn

2. Prof. Rajiv Gupta

3. Prof. Ram Achar

Delft Technical University, Netherlands

Massachusets Institute of Technology

Carleton University, Ottawa, Canada

January 15-16, 2007

January 4-6, 2010

December 1-3, 2011

11

International Guest Faculty Workshop

1. Name of Expert : Prof. Ram Achar

2. University/ Institution Affiliation : Carleton University, Ottawa, Canada, Ontario-K1S5B6

3. Topic of the Lecture : Fundamentals and Advances in VLSI Interconnects & Signal Integrity Methodologies

4. Date and Duration of the Workshop : 1-3 December 2011

5. No. of Participants attended the workshop : 25

6. Lecture materials/PPT slides presented to be sent to DIT : IIT KGP did not receive any notes/lecture materials yet.

Laboratory Classes Conducted using the facilities of the SMDP-VLSI Lab

Laboratory Classes Tools Used

VLSI Engineering (EC33005 ) Cadence, Synopsys, Xilinx

Solid State Circuits Lab (EC69017 ) Synopsys, TCAD

VLSI Design Laboratory (EC69010) Cadence, Synopsys, Xilinx

IC Technology and Process Simulation Lab (EC69015) Synopsys, TCAD, HSpice

VLSI CAD Lab (EC60032) Cadence, Synopsys, Xilinx

≈ 50 M.Tech/M.S/Ph.D students are doing their research works in SMDP-VLSI Lab.

Manpower Generation

Description

2010-11 2011-12

Qualified Enrolled

Type-I Ph.D in various aspects of VLSI Design & CAD 6 22

Type-II M.E./M.Tech in Microelectronics & VLSI Design. 12+24 8+28

Type-III

M.S./M.Tech in other areas of Electronics / Communication / Computer Science / Instrumentation etc., who have taken at least two courses on various aspects of VLSI Design and CAD

42 58

Type-IV

B.Tech in Electronics / Computer Science / Communication / Instrumentation etc. who have taken graduate-level courses on VLSI Design

120 120

Details of Project Staff Employed

Name Designation Salary Date of Joining Qualification

Indranil HataiJPA 14,525 13th June, 2006 M.S

Completed

JPO 18,900 1st Jan, 2011 Ph.D Continuing

Santosh Patnaik JPO 18,90015th March, 2007(Resigned on 5th

Jan 2012)Ph.D (Thesis Submitted)

Rakesh Biswas JPA 17,000 12th May 2011 M.S Continuing

INDIA CHIP PROGRAMME

Technology - UMCs 180m CMOS Total area - 1.525mm x 1.525mmFoundry - IMEC, BelgiumPackage type - DIL 40 Number of packaged chips - 10 Current Status - ReceivedThe fabrication cost has been paid by IISc BangaloreNumber of Blocks - 5IIT Kharagpur - 2 [10-bit THA] & [4-bit Adder]NIT Durgapur - 1 [6th Order Filter]Jadavpur University - 1 [Chopper Amplifier]BESU - 1 [Clock Generator]Number of pins - 40 [4x10]Power supply - 1.8V (Single)

Die Photograph : ICP-KGP-I

Chip-I (ICP-KGP-I)

Complete Layout with Pads and FillersICP-KGP-I

1. Clock Generator - BESU2. 10-bit THA - IIT Kharagpur 3. Chopper Amplifier - Jadavpur University 4. 6th Order Filter - NIT Durgapur 5. 4-bit Adder - IIT Kharagpur

10-Bit, 500MSample/S Track and Hold AmplifierDesigned at IIT Kharagpur

Designed by Santosh Kumar Patnaik

Parameters Value

Technology 180nm CMOS

Sampling Rate 500 MS/s

Resolution 10 Bit

Input Swing 1V (p-p)

Input Signal Frequency 100MHz

THD 62dB

Power Consumption 57mW

Supply Voltage 1.8V

Test Results

Designed by Santosh Kumar Patnaik

Track/Hold OutputInput Sinusoidal Signal (Fin = 500KHz)

Sampling Frequency (FS) = 2.5MHz

Track/Hold OutputInput Sinusoidal Signal (Fin = 4MHz)Sampling Frequency (FS) = 15MHz

4-Bit secure efficient asynchronous adderDesigned at IIT Kharagpur

Parameters usedInput rise time = fall time

100 ps

Load capacitance 10 fFOperating temperature

-65° to 140° C

ResultsAverage current for 32 bits

225.2*

Area (353*198Average case propagation delay (32 bit)

1.775 nsDesign is not working properly after fabrication

Technology - UMCs 180m CMOS Total area - 1.525mm x 1.525mmFoundry - IMEC, BelgiumPackage type - DIL 40 Number of packaged chips - 10 Current Status - ReceivedFabrication and Packaging Cost - 3160.00 Euro Custom Duty - 13070.00 RupeesClearance Charge - 5178.00 RupeesPayment – Done [≈ 2,28,166 Rupees]Number of Blocks - 4IIT Kharagpur - 2 [4-bit ADC] & [4-bit Multiplier]NIT Durgapur - 1 [NOC Generator]Jadavpur University - 1 [Sense Amplifier]Number of pins - 40 [4x10]Power supply - 1.8V (Dual- Analog VDD, Digital VDD)

Chip-II (ICP-KGP-II)

Die Photograph : ICP-KGP-II

Complete Layout with Pads

1. NOC Generator - NIT Durgapur 2. 4-bit SR-ADC - IIT Kharagpur 3. Sense Amplifier - Jadavpur University 4. 4-bit Multiplier - IIT Kharagpur

4-Bit, 500MSample/S Switched Reference ADCDesigned at IIT Kharagpur

Designed by Santosh Kumar Patnaik

Parameters Value

Technology 180nm CMOS

Sampling Rate 500 MS/s

Resolution 4 Bit

Input Swing 1V (p-p)

Input Signal Frequency 100MHz

THD 29dB

Power Consumption 22mW

Supply Voltage 1.8V

Test Results

Designed by Santosh Kumar Patnaik

Binary OutputInput Sinusoidal Signal (Fin = 15MHz)

Sampling Frequency (FS) = 80MHz

Binary OutputInput Sinusoidal Signal (Fin = 5MHz)Sampling Frequency (FS) = 30MHz

4-Bit Area-power efficient asynchronous adderDesigned at IIT Kharagpur

Parameters usedInput rise time = fall time 100 psLoad capacitance 10 fFOperating temperature -65° to 140° C

ResultsAverage power for 32 bits 226 µwArea (number of transistors for 2 bits)

62

Average case propagation delay

4 ns

Designed by Partha De with Prof C Mandal

Pin Number

Pin Name Input value (volt)

Output value (volt)

Expecting value(volt)

3 GND-Digital 0.11 0.14 0.114 VDD-Digital 1.79 1.78 1.7910 GND-Digital 0.11 0.13 0.1111 VDD-Digital 1.79 1.78 1.7920 GND-Digital 0.11 0.13 0.1121 VDD-Digital 1.79 1.76 1.79

Test Results

Input OutputCarry Sum 0 Sum1 Sum2 Sum3 Done

A B Pre Clk Original

Expecting

Original

Expecting

Original

Expecting

Original

Expecting

Original

Expecting

Original

Expecting

0.11v 0.11v 1.79v 10 MHz

0.11v 0.16v 0.11v 0.15v 0.11v 0.18v 0.11v 0.19v 0.11v 0.12v 1.79v 1.77v

1.79v 0.11v 1.79v 10 MHz

0.11v 0.19v 1.79v 1.78v 1.79v 1.76v 1.79v 1.77v 1.79v 1.75v 1.79v 1.78v

0.11v 1.79v 1.79v 10 MHz

0.11v 0.19v 1.79v 1.78v 1.79v 1.76v 1.79v 1.76v 1.79v 1.76v 1.79v 1.78v

1.79v 1.79v 1.79v 10 MHz

1.79v 1.76v 0.11v 0.12v 1.79v 1.76v 1.79v 1.76 1.79v 1.78v 1.79v 1.77v

i) Papers Presented in National / International Conference s in which SMDP-II Financial Support have been used

Financial Year Detail of Publication in the format as shown : Quantum of support obtained from SMDP (Rs.)

2011 I. Hatai, I. Chakrabarti, S Banerjee 5,000

2010 S.K. Patnaik, S. Banerjee (5) 1,500

2010 I. Hatai, I. Chakrabarti 32,000

2010 C. Karfa, D. Sarkar,C.R. Mandal (4) 32,000

2008 S. Sarkar, S Banerjee (1) 35,000

2007 S N Pradhan, S Chattapadhayay 2,500

2008 S N Pradhan, S Chattapadhayay 40,300

2008 C. Karfa, D. Sarkar,C.R. Mandal,P. Kumar (2) 32,000

2008 Prashant Agarwal, Ajit Pal(3) 20,000

Papers/Publications

*** All Papers are listed in our smdp-2 website ****

Best M.Tech Thesis Award

i. Nomination for the best thesis for the academic year 2010-11 from RC

M.Tech. Thesis Title Name of Student Name of Supervisor

No Nomination in this Year N/A N/A

The date of submission of thesis to DIT

N/A

Thesis uploaded in SMDP website N/A

Best M.Tech Thesis Award contd….

ii. Nomination for the best thesis for the academic year 2010-11 from PI

M.Tech. Thesis Title Name of Student Name of Supervisor

FPGA Based Network Security Architecture for High Speed Networks

Sourav Mukherjee Prof. Bibhudatta Sahoo, NIT Rourkela

The date of submission of thesis to DIT

1st February 2012

Thesis uploaded in SMDP website No

Best M.Tech Thesis Award contd….

iii. Nomination for the best thesis for the academic year 2010-11 from PI

M.Tech. Thesis Title Name of Student Name of Supervisor

Optimization and Length Scaling of Tunnel FET

Jahnvi Sen Mrs. Brinda Bhowmik, and Prof. S. Baishya, NIT Silchar

The date of submission of thesis to DIT

1st February 2012

Thesis uploaded in SMDP website No

Financial Status

FYGIA Release

dFund Utilized

Interest Earned against Fund

released

Utilization Certificate Sent

2005-06 17,65,500 1,12,946 0.0 Y

2006-07 6,50,000 13,81,997 0.0 Y

2007-08 16,52,944 18,14,690 0.0 Y

2008-09 14,35,000 17,26,010 0.0 Y

2009-10 16,00,000 14,38,937 0.0 Y

2010-11 14,75,000 12,84,849 0.0 Y

2011-12 14,46,800 5,30,000 0.0 N

** Till 31st January 2012

VLSI Placements

Name of The Company No of StudentARM Embedded Tech. 4

Brocade Communication 7Intel 8

Qualcomm 10Texas Instrument 4

National Instrument 1Xilinx 6

Philips Research 2Ericsson R&D 5

Name of The Company No of Student

Samsung 14

BEL CRL 6

Cypress Semiconductor 4

Coreel Technologies 2

Ittiam 3

KLA Tencor 1

Analog Devices 4

Sandisk 3

VLSI Placements

Reasons for Continuation Manpower Development: Every year more than 200 students are graduated in

the field of VLSI who have used the resource of SMDP research lab.

Many MS and PhD students are using the facilities available in the SMDP lab for their research work.

Few designed chips are on way. Few IP cores has already been generated for specific applications e.g. Biomedical Application, Wireless Communication Application, etc. (One chip has won the Cadence Design Contest 2010 in the Masters Category) ( One design has been awarded as Best paper in TechSym 2011)

Every year IEP has been conducted to train the trainer.

Few EDA tool training has been organized to cope with the latest VLSI technology.

Few International Guest Faculty Programme has been conducted to know the latest research trends in outside of India.

Problem Faced

Installation of the software and licensing took more than the scheduled time.

8 HCL Client PC gone down. HCl is taking too much time to repair it.

More storage per PC is required for better utilization of the software.

Lack of proper EDA tool training programme.

Lack of EDA tool up-gradation and licensing ( We don’t have PrimeTime-Power Calculation license).

Chips to Systems Proposal Contour

1. Project Name - An embedded high resolution ultrasonography system using fundamental and harmonic imaging

2. Total Outlay – 541 Lakhs (Including all institute)3. Duration – 5 Years4. Manpower Requirement –

@ RC: 2 Research Consultant, 2 Senior Project Assistant, 1 Technician for testing, 1 Job Assistant

@PI: 2 Guest Faculty per PI

Cadence: 5 year subscription for 20 licenses of each module indicated below •Full Custom/Analog/Mixed Signal/RFIC Design Flow tool set•Functional verification tool set•System design and verification tool set•Logic Design tool set•Digital Implementation tool set•Manufacturability Signoff tool set•IC packaging and SiP design tool set•PCB Design tool set Synopsys: 5 year subscription for 10 licenses of each module indicated below•System Level Design tool set•Digital and analog verification tool set•Implementation and signoff tool set•Manufacturing tool set•TCAD process and device simulation tool setMentor Graphics: 5 year subscription for tool set available under Mentor Higher Education ProgrammeXilinx: 5 year subscription for 50 licenses of each module indicated below Software Requirements: Xilinx Latest version with system editionHardware Requirements: Virtex-6 and Spartan-6 boards

Software Required for C2S

Main output from the project:i. Development of JPEG-2000 on ASIC. (IIT KGP, BESU)ii. Development of FFT/IFFT unit (IIT KGP) iii. Development of knowledge base system. (IIT KGP)iv. Telemedicine solution along with the system. (IIT KGP, BESU )v. CAM Memory Design (JU)vi. DSP/DIP chips (NIT DGP, IIT KGP, BESU, JU)vii. Portable Low-Cost Ultrasound System design (IIT KGP, PSG College

Tech.)viii.Design & Development of image and video processing algorithm (IIT KGP,

PSG Coll. Tech, NIT DGP, BESU, JU)ix. Over all System Integration (IIT KGP).

Application area in which system would find use: Healthcare

Objective of C2S

Manpower at Ph.D & Masters level proposed to be generated as a secondary outcome of the project: Same as SMDP-II

Name of the PIs along with whom collaborative development work would be carried out for designing the identified targeted system: (a) IIT Kharagpur, (b) BESU, Howrah, (c) Jadavpur University, (d) NIT Durgapur, (e) PSG College of Tech. Coimbatore

Year wise Outputs of the C2S

Work Plan Months0 6 12 18 24 30 36 42 48 54 60

1. Literature Survey

2. Procurement of capital equipment and Software3. System level simulation4. FPGA realizations for beam forming algorithms5. Algorithm development for image compression6. FPGA realization of image compression7. Software development for telemedicine8. System integration9. Prototype design and testing

THANK YOU FOR YOUR KIND ATTENTION