converter topologies for power distribution

7/27/2019 Converter Topologies for Power Distribution

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08-2011 Simone Buso - Converter topologies for power distribution in theSLHC trackers

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Converter topologies for powerdistribution in the SLHC trackers

Simone Buso, Giorgio SpiazziUniversity of Padova

Dept. of Information Engineering DEI

Speaker: Simone Buso

[email protected]


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Summary

Introduction

Motivation Design constraints

Circuit topologies for POL converters Two phase buck with integral voltage divider

Switched capacitor topologies

Conclusions


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The Large Hadron Collider - LHC


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The Large HadronCollider (LHC) islocated inside a

circular tunnel, 27km in circumference.The tunnel is buried

around 50 to 175 munderground. Itcrosses the Swissand French borderson the outskirts ofGeneva.



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Four experimentsare currently usingthe LHC

infrastructure.

The largest ones are

ATLAS and CMS, bothdedicated to thestudy of high energy(up to 14 TeV)collisions ofprotons(quest of the Higgsboson ...).



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Modern High Energy Physics experiments consist of hugedetectors that have to be built with minimum amounts of non-sensitive material, so as to maximize the coverage of sensorsand to minimize the unwanted interaction between insensitiveinfrastructural materials and the particles.

A detector such as the CMS experiment tracker consists of 10

cylindrical layers of thin (3-500 m) semiconductor sensors, but

also of several tons of copper and other metals to bring power tothe electronics and consequently to cool it.

The presence of this material is structurally essential, but

degrades the precision of the particle position measurementthrough various phenomena, such as multiple scattering andnuclear interactions.



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Motivation

The planned increase in the sensitivity of the instrumentationemployed in the Large Hadron Collider (LHC) experiments atCERN, calls for a thorough re-design of the power distribution

networks architecture.

The powering scheme implemented in the LHC, based on theindividual powering of every front-end module from remotepower supplies, cannot be applied in the future super LHCbecause of its inefficiency and of the extra cabling and coolingmaterial that would be required.

One of the considered alternatives involves the development ofa distributed power supply network, where integrated point ofload converters are to be deployed inside the trackers, in ahighly hostile environment.


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Design constraints

PS

The converters will be placed insidethe tracker, therefore they will beexposed to

radiationradiation (> 250Mrad total dose) magnetic fieldsmagnetic fields (2T - 4T)

Commercial converters cannot survive

because they are not radiation tolerantand use ferromagnetic materials, that

saturate at this external magnetic field

level.

It is therefore necessary to develop

custom converters, based on ASICs,

that meet the HEP requirements

Cross section of ATLASCross section of ATLAS


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Radiation toleranceRadiation toleranceThe specifications require the use of a technology capable tosustain up to 15-20 V (at least). Commercial high voltagetechnologies are typically conceived for automotive

applications. Some of them can be made radiation tolerant bydesign.

Magnetic field toleranceMagnetic field tolerance

We are compelled to use coreless (air-core) inductors becauseall the ferromagnetic materials are not usable with an externalmagnetic field of 2-4 T. This implies the use of very highswitching frequencies (> 1 MHz).

Design constraints


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Detector

Read-outhybrid

FrontFront--End readout ASICEnd readout ASIC- Idigital Ianalog (current projection for ATLAS Short

Strip readout is Ianalog ~ 20mA, Idigital ~ 60-100mA)

- 2 power domains: Van=1.25V, Vdig=0.9-0.8V(as low as possible)

- Clock gating might be used => switching load

Hybrid/Module controllerHybrid/Module controller

- Ensures communication (data, timing, trigger,possibly DCS)

- Digital functions only- It might require I/Os at 2.5V

Other than the rod/stave controllerrod/stave controller,, optoelectronicsoptoelectronics componentscomponents willalso have to be used, requiring an additional power domain (2.5-3V)

Detector moduleDetector module

Rod/staveRod/stave

Power Distribution in the sLHC


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Conversion stage 2

Detector moduleDetector module


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High frequency commutated (> 1MHz), minimum

inductance (air core) buck converters (for conversion

stage 1).

Switched capacitor (SC) converters (for conversion stage2, placed inside the ASIC chips).

Our design optionsOur design options


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RAD-HARD Switch Technology

Phase 1 of the research is the identification of a suitable

CMOS technology, allowing the design of both low

voltage logic and high voltage (up to 20V) vertical or LD

MOS.


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RAD-HARD Switch Technology

Displacement damage is due to the impact of neutrons

with the crystal lattice. It implies the creation of

recombination centers, decreasing the number of

available minority carriers. In CMOS processes, thiseffect is negligible (majority carrier devices) up to very

high particle flux levels.

Total Ionizing Dose (TID) effects are related to the long

term deterioration of the crystal lattice and, in CMOS

devices, imply threshold voltage shift and leakage

current amplification. Both can be compensated, to acertain extent, by suitable design rules (hardness by

design).


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Topologies for POL converters

Phase 2 of the research is the identification of suitable

converter topologies to perform the function of Point of

Load (POL) voltage regulators.

From the devised power distribution architecture we see

that step-down (buck) converters are required.

The minimization of inductor size and value, together

with the need for minimum ripple call for high frequency

(> 1 MHz) operation and, possibly, multi phasearrangements (interleaving).


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Point of Load Converter Specifications

7.5 WOutput power, Pout

2.5 VOutput voltage, Uout

12 VInput voltage, Uin

Power Switch Specifications

2000 pFTypical input capacitance

160 mTypical on-state resistance @25C

3 AMaximum RMS current

20 VMaximum drain to sourcevoltage



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S1

+

S2Uin UoutCout

L1

Rout-

iL1

Synchronous buckSynchronous buck



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S1

+

S2Uin UoutCout

L1

Rout-

iL1


S1

+S2

S3

S4

Uin UoutCout

L1

L2

Rout-

iL1

iL2

Interleaved buck (2 phases)Interleaved buck (2 phases)



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S1

+

S2Uin UoutCout

L1

Rout-

iL1


S1

+S2

S3

S4

Uin UoutCout

L1

L2

Rout-

iL1

iL2

Interleaved buck (2 phases)Interleaved buck (2 phases)

S1

+S2

S3

S4Uin UoutC1Cout

L1

L2Rout -

iL1

iL2

+UC1

-

Interleaved buck with integral voltage dividerInterleaved buck with integral voltage divider (2PBIVD)(2PBIVD)


l i f


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Converter analysis and key waveforms determination.

Preliminary design based on basic specifications,

considering:

different switching frequencies;

different operating modes (CCM versus QSW).

Calculation of average, peak and RMS currents in theswitches and inductors.

Tentative efficiency estimation, including also:

switching losses (by SPECTRE simulations of switchcommutations);

skin and proximity effects.


2PBIVD


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2PBIVD converter

0 < D < 0.50 < D < 0.5

L

UUUout1Cin

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

outi

iL1+i

L2

t

t

0

L

Uout

L

UUout1C

L

Uout

iL2

-iL1

2

TSS

DTS

T

S1

+

S2

S3

S4Uin UoutC1

Cout

L1

L2

Rout-

iL1

iL2

+

UC1

-

2PBIVD t


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2PBIVD converter

0.5 < D < 10.5 < D < 1

S1

+

S2

S3

S4Uin UoutC1

Cout

L1

L2

Rout-

iL1

iL2

+

UC1

-

t

t

t

1Li

iL2

t

2Li

iL1

31 S,S

42 S,S

iC1

outi

iL1+i

L2

t

t

0

L

UUUout1Cin

L

Uout

L

UU outC 1

iL2

-iL1

2

ST

2

1DTS S

DTS

T

L

Uout

L

UU outin

2PBIVD t


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2PBIVD converter

converter topologies for power distribution

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