control unit design new (1)
TRANSCRIPT
-
8/9/2019 Control Unit Design New (1)
1/31
Introduction to CPU DesignComputer Organization&Assembly Language Programming
-
8/9/2019 Control Unit Design New (1)
2/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 2
OutlineIntroductionData Path Design
Register Trans erRegister Trans er Timing!ingle "us CPU Design
T#o "us CPU Design Three "us CPU Design
Control Unit Design$ard#ired Control%icroprogrammed Control
!imple CPU Design 'ample
-
8/9/2019 Control Unit Design New (1)
3/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 3
IntroductionA CPU is decomposed into t#omain parts( data path & controlunit)Data path consists o registers*arithmetic bloc+s andinterconnections)
The ,o# o data bet#eenregisters & arithmeticoperations are per ormed inthe data path)
-
8/9/2019 Control Unit Design New (1)
4/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 4
IntroductionData path is controlled by a set o signals to causeactions to ta+e place)'amples o such signals are
strobe signals to load registerssignals to control the connecti-ity o outputs to a bus)
In order to per orm an operation on the data path*it is re.uired to generate the control signals in thecorrect order to a/ect the correct data pathacti-ity)
The control unit recei-es signals that describe thestate o the data path and the control unit sendscontrol signals to the data path)
-
8/9/2019 Control Unit Design New (1)
5/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 5
Register Trans er The process o instruction e'ecution can bedescribed as a set o register trans er operations)In each cloc+* one or more register trans eroperations are per ormed)
!ome register trans er operations can0t beimplemented in one cloc+ cycle and ha-e to bebro+en into a number o register trans eroperations that ha-e to be per ormed in ase.uence)'ample( ADD A1* "1
2) 3 4 A15) 6 4 3 7 "1 8) A1 4 6
-
8/9/2019 Control Unit Design New (1)
6/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 6
!ingle "us CPU The data path is 29:bit#ide) It consists o our generalpurpose registers* R2* R5*R8* and R;)It contains ProgramCounter
-
8/9/2019 Control Unit Design New (1)
7/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 7
>etch Control !e.uence The etch:e'ecute process can be summarized as
ollo#s(2) >etch the content o memory location pointedby PC and load it into IR? IR 4 @PC
5) Increment the content o PC by 2? PC4 PC 7 2Instruction size is assume 2 byte or simplicity
8) 'ecute the instruction based on the contento IR)
>etch Control !e.uence
-
8/9/2019 Control Unit Design New (1)
8/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 8
>etch Control !e.uence The Bait %emory >unction CompleteC= signal is acti-ated to in orm the
control unit to remain in T5 until thememory nishes the re.uested readoperation)
T5 ma+e ta+e more than one cloc+ cycledepending on the number o cloc+ cyclesneeded by the memory to nish the read
operation) A ter the memory nishes its unction* it #illput the re.uested -alue
-
8/9/2019 Control Unit Design New (1)
9/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 9
!ynchronous -s)Asynchronous %emory Trans erData trans er bet#een the CPU and memory can
be either synchronous or asynchronous)In the synchronous trans er* it is assumed that amemory trans er operation
-
8/9/2019 Control Unit Design New (1)
10/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 10
!ynchronous -s)
Asynchronous %emory Trans erIn the asynchronus trans er* the CPU a ter re.uestinga memory operation #aits until the memory indicatesthat it completed the re.uested operation by settinga memory unction complete signal to 2)
>etch control se.uence or both asynchronous andsynchronous memory trans er is sho#n) It is assumedthe memory read operation #ill ta+e t#o cloc+ cyclesto complete)
Cpu%emInter )s#
-
8/9/2019 Control Unit Design New (1)
11/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 11
'ecution Control !e.uence
or Add InstructionConsider the instruction ADD R2* @R8
-
8/9/2019 Control Unit Design New (1)
12/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 12
'ecution Control !e.uence
or F%P InstructionConsider the instruction F%P Label
-
8/9/2019 Control Unit Design New (1)
13/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 13
'ecution Control !e.uenceor Conditional F%PInstructionconsider the branch on Hegati-e
instruction F%PH Label
-
8/9/2019 Control Unit Design New (1)
14/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 14
'ecution Control !e.uenceor Additional Instructions
ADD R2* 5
1C$J R2* R5
-
8/9/2019 Control Unit Design New (1)
15/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 15
'ecution Control !e.uenceor Additional Instructions
IHC @R2
C%P R2* R5
It is assumed here that there #ill be a >LAJ! register that #illstore the ,ags and there #ill be a unit to compute the ,ags)
-
8/9/2019 Control Unit Design New (1)
16/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 16
'ecution Control !e.uenceor Additional Instructions
LOOP He't
it is assumed that the loop counter isstored in register R2
-
8/9/2019 Control Unit Design New (1)
17/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 17
Per ormance Considerations The e'ecution time o a program depends on(
IC( the instruction count i)e)* the number oinstructions e'ecuted in the programCPI( the number o cloc+s needed or e'ecutionper instruction
τ( the cloc+ period'ecution time o a program* TG IC ' CPI ' τ
To reduce the e'ecution time o a program(
2) Reduce number o instructions in the program)5) Reduce number o cloc+s re.uired ore'ecuting each instruction)8) Reduce the cloc+ period)
-
8/9/2019 Control Unit Design New (1)
18/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 18
Control unitStep Action
2 PC out * %ARin * Read* !elect;* Add* 6 in
5 6 out * PCin * 3in * B%> C8 %DR out * IRin
; R8 out * %ARin * Read
K R2out * 3in * B%> C
9 %DR out * !elect3*Add* 6 in
L 6 out * R2in * &nd
>igure L)9) Control se.uenceore'ecutiono the instructionAdd
-
8/9/2019 Control Unit Design New (1)
19/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 19
P C i
n
P C o u t
M A R i
n
R e a d
M D R o
u t
I R i n
Y i n
S e l e c t
A d d
Z i n
Z o u t
R 1 o
u t
R 1 i
n
R 3 o
u t
W M F C
E n d
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
0
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
0
0
1
0
0
Micro -instruction
1
2
3
4
5
6
7
Figure 7.15 An example of microinstructions for Figure 7.6.
-
8/9/2019 Control Unit Design New (1)
20/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 20
StepAction
2 PCout * %ARin * Read*!elect;*Add*6 in
5 6out * PCin * 3in * B%> C
8 %DRout * IRin
; O/set: eld:o :IR out * Add*6in
K 6out * PCin * nd
>igure ) ) Control se.uence or an unconditional branch instruction)
-
8/9/2019 Control Unit Design New (1)
21/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 21
Figure 7.10. Control unit organization.
CLKClock Control step
IR encoderDecoder/
Control signals
codes
counter
inputs
Condition
External
-
8/9/2019 Control Unit Design New (1)
22/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 22
Externalinputs
Figure 7.11. Separation of the decoding and encoding functions.
Encoder
ResetCLKClock
Control s ignals
counter
Run End
Conditioncodes
decoderInstruction
Step decoder
Control step
IR
T 1 T2 Tn
INS 1INS 2
INS m
-
8/9/2019 Control Unit Design New (1)
23/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 23
Figure 7.13. Generation of the End control signal.
T 7
Add BranchBranch
-
8/9/2019 Control Unit Design New (1)
24/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 24
Figure 7.12. Generation of the Z i n control signal for the processor in Figure 7.1.
T1
AddBranch
T4 T6
-
8/9/2019 Control Unit Design New (1)
25/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 25
Figure 7.16. Basic organization of a microprogrammed control unit.
storeControl
generator
Starting
address
CW
Clock µP C
IR
-
8/9/2019 Control Unit Design New (1)
26/31
-
8/9/2019 Control Unit Design New (1)
27/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 27
AddressMicroinstruction
M PCout * %ARin * Read*!elect;*Add*6 in
2 6 out * PCin * 3in * B%>C
5 %DRout * IRin8 "ranchtostartingaddressoappropriate microroutine) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) ) )5K I HGM* thenbranchtomicroinstructionM
59 O/set: eld:o :IR out *!elect3* Add* 6 in5 6 out * PCin * nd
>igure )2 ) %icroroutine or the instruction "ranchNM)
-
8/9/2019 Control Unit Design New (1)
28/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 28
F2 (3 bit s)
000: No transfer001: PC in010: IR in011: Z in100: R0 in101: R1 in110: R2 in111: R3 in
F1 F2 F3 F4 F5
F1 (4 bi ts ) F3 (3 bi ts) F4 (4 b its) F5 (2 b i ts)
0000 : No t ransfer0001: PC o u t 0010: MDR ou t 0011: Z o ut 0100: R0 o u t 0101: R1 o u t 0110: R2 o u t 0111: R3 o u t
1010: TEMP o u t 1011 : Offset ou t
000: No transfer001: MAR in010: MDR in011: TE MP in100 : Y in
0000 : Add0001: Sub
1111: XOR
16 ALUfunctions
00: No action01: Read10: Write
F6 F7 F8
F6 (1 b i t) F7 (1 bi t) F8 (1 bi t)
0: SelectY
1: Select4
0: No action
1: W MFC
0: Continue
1 : End
Figure 7.19. An example of a partial format for field-encoded mi croinstructions.
Microinstruction
-
8/9/2019 Control Unit Design New (1)
29/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 29
-
8/9/2019 Control Unit Design New (1)
30/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 30
F1 (3 bits )
000: N o transfer001: PC ou t 010: MDR o ut 011: Z ou t 100: Rsrc ou t 101: Rdst ou t 110: TEMP ou t
F0 F1 F2 F3
F0 (8 bi t s) F2 (3 bi ts ) F3 (3 b it s )
000: N o transfer001: PC in010: IR in011: Z in100: Rsrc in
000: No transfer001: MAR in
F4 F5 F6 F7
F5 (2 bit s)F4 (4 bi ts ) F6 (1 b it )
0000: Add0001: Sub
0: SelectY1: Select4
00: No action01: Read
Microinstruction
Address of nextmicroinstruction
101: Rdst in
010: MDR in011: TEMP in100: Y in
1111: XOR
10: Write
F8 F9 F1 0
F8 (1 bit )
F7 (1 bit)
F9 (1 b i t) F10 (1 b it )
0: No action1: W MFC
0: No action1: OR indsrc
0: No action1: OR mode
0: N extAdrs1: InstDec
Figure 7.23. Format for microinstructions in the example of Section 7.5.3.
-
8/9/2019 Control Unit Design New (1)
31/31
Introduction to CPU Design Computer Organization & Assembly Language Programming slide 31
Figure 7.22. Microinstruction-sequencing organization.
Conditioncodes
IR
Decodi ng circuits
Control store
Next address
Microinstruction decoder
Control signals
InputsExternal
µ AR
µ I R