CONTINUOUS ASSIGNMENTS

COMBINATIONAL LOGIC CIRCUITS

each output of a Combinational Logic Circuit A function of the inputs - Mapping functions (fo,

f1, f2, …fm) the outputs are updated immediately after the

inputs change Don’t forget the propagation delay in real

circuits

CombinationalLogic Circuit:

:

I0

I1

In

::

f0(I1, I2, In)

f1(I0, I2, I4, I7)

fm(I2, In)

f0 ~ fm are mapping functions

DATAFLOW MODELLING

only model behaviour of combinational logic circuits

assign a value to a net using continuous assignment (CA) statement continuous assignment corresponds to

combinational logic, without requiring explicit instantiation of gates flip-flops and latches can NOT be created using

continuous assignment continuous assignments are always active

source order of the CA statements does not impact the design CA statements are executed concurrently

CONTINUOUS ASSIGNMENTS MEANING

A continuous assignment is the most basic statement in dataflow modeling, used to drive a value onto a net.

A continuous assignment replaces gates in the

description of the circuit and describes the circuit at a higher level of abstraction.

A continuous assignment statement starts with the keyword assign.

A SIMPLE DATAFLOW EXAMPLE

Assign c = a&&b;

“assign” is the keyword carrying out the assignment operation. This types of assignment is called a continuous assignment.

a and b are operands – typically single-bit logic variables.

“&&” is a logic operator. It does the bit-wise AND operation on the two operands a and b.

“=“ is an assignment activity carried out. C is a net representing the signal which is the

result of the assignment.

CONTINUOUS ASSIGNMENTS SYNTAX

//Syntax of assign statement in the simplest form<continuous assign> ::= assign <drive strength> ?

<delay>?<list of assignments>; Example: / / Continuous assign. out is a net. i1 and i2 are nets.

assign out = i1 & i2;

// Continuous assign for vector nets. addr is a 16-bit vector net

// addrl and addr2 are 16-bit vector registers.

assign addr[l5:0] = addrl_bits[l5:0] * addr2_bits[l5:0];

// Concatenation. Left-hand side is a concatenation of a scalar

// net and a vector net.

assign {c_out, sum[3:0]) = a[3:0] + b[3:0] + c_in;

DATAFLOW EXAMPLE AND-OR-INVERT

8

2-to-1MUX

OUT

A

SEL

B

1

0

module MUX2TO1 (OUT, A, B, SEL);output OUT;input A, B, SEL;

assign OUT = SEL ? A : B;

endmoduleMUX2TO1

EXAMPLE: MULTIPLEXER

9

EXAMPLE

module HALF_ADDER(COUT, SUM, A, B);output COUT, SUM;input A, B;

assign SUM = A ^ B;assign COUT = A & B;

endmodule

A

BSUM

COUT

HALF_ADDER

Continuous Assignment with keyword 'assign'

Example: Half Adder

module HALF_ADDER(COUT, SUM, A, B);output COUT, SUM;input A, B;

assign {COUT, SUM} = A + B;

endmodule

A

BSUM

COUT

HALF_ADDER

Continuous Assignment with keyword 'assign'

Compare the two Verilog modules and comment their final

implementations.Ans: The ‘+’ operator is not bound directly to physical gates

module ADDER4(CO, SUM, A, B, CI);output [3:0] SUMoutput CO;input [3:0] A, B;input CI;

assign {CO, SUM} = A + B + CI;

endmodule

Example: Full AdderFull

Adder

A

B

SUM

COCI

Carry-outCarry

-in

ADDER4

Example: Given: Tpd(AND) = 10ns

Tpd(XOR) = 15ns

`timescale 1ns/100psmodule Half_Adder (CO, SUM, A, B);output CO, SUM;input A, B;

assign #10 CO = A & B;assign #15 SUM = A ^ B;

endmodule

A

BSUM

Half_Adder

COCarry-

out

EXAMPLE : 4X1 MUX USING LOGIC EQUATIONS

// Module 4-to-1 multiplexer using data flow logic equation

// Compare to gate-level model

module mux4_to_1 (out, i0, i1, i2, i3, s1, s0);

// Port declarations from the I/O diagram

output out;input i0, i1, i2, i3;

input s1, s0;

// Logic equation for outassign out = (~s1 & ~s0 & i0) | (~s1 & s0 & i1) |

(s1 & ~s0 & i2) |(s1 & s0 & i3) ;

4-TO-1 MULTIPLEXER, USING CONDITIONAL OPERATORS

/ / Module 4-to-1 multiplexer using data flow. Conditional operator.

/ / Compare to gate-level model

module multiplexer4-to-1 (out, i0, i1, i2, i3, s1, s0);

/ / Port declarations from the I/O diagram

output out;input i0, i1, i2, i3;

input s1, s0;/ / Use nested conditional operator

assign out = s1? ( s0 ? i3 : i2) : (s0 ? il : i0) ;

endmodule