consistent modeling technique for accurate transaction level models
TRANSCRIPT
Consistent Modeling Technique for Accurate
Transaction Level ModelsTransaction Level Models(Master Thesis)
Hui Chen
Professor : Prof. Dr.-Ing. Ulf Schlichtmann
Ad isors Prof Dr Ing Wolfgang EckerAdvisors : Prof. Dr.-Ing. Wolfgang Ecker,
Dipl.-Ing. Michael Velten
April 22, 2008
Institute for EDACOM BTS MT SD
Motivation
Complex SoC design, but limited time to marketStart software development and validation before RTL is availableRaise design to higher abstraction levels: Transaction Level (TL)Early availability of TL Models due to high degree of abstraction
Existent RTL legacy in new SoCs => Need to be modeled at TL too
Not only functional but also timing accurate TL models:To ensure the order of interrupts, to analyze the system performance, …
Obtaining TL models
TL TL TL
....switch(base_addr) {case 2: pbus_read(...); break;case 1: ...} TL TL TL
TLTL
... }...
Functional ModelTL
Component
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A Complete TL SoC DesignRTLComponent
Task DescriptionF IP "Pl "
Plasma VHDL Modelenhancement /bug fixes alignment
Plasma C Model
Free IP "Plasma"
SPINNI VHDL Model
restructure
SPINNI C Model refinement ....
it h(b dd ) {
f ti l i
switch(base_addr) {case 2: pbus_read(...); break;case 1: ...
... }...
SPINNI TL Modelfunctional comparison
SPINNI Timed TL Model
timing comparison
Page 3Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Presentation Part
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 4Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 5Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Principles of TL Modeling
Initiator Targetinitiator_port target_port
remote function call implements a function
Transactions : communication between modules via function calls
Synchronization : no toggling clock, time-based or event-based
Modules : basic building blocks
Ports : bind modules and channels
Page 6Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Ports : bind modules and channels
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 7Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
SPINNI VHDL & C Models
SPINNI: Restructure Plasma
Get a clear architectureGet a clear architecture
Plasma Model SPINNI Model
restructure
Make the modules traceable and comparable
Make the model extensible
Page 8Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
SPINNI VHDL & C Models
SPINNI VHDL Model
irq_sigCPU
Main_Bustimer_irq
gpio_irq
uart_irq4
2
ICU
GPIO
Periph_Bus
2GPIO
Timer
UART
RAM XRAM
TBE2TBE1
Page 9Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Fig. 2.1: Block Diagram of the SPINNI VHDL Model
SPINNI VHDL & C Models
irq_sigCPU
SPINNI C Model
cpu_run
Main_Bustimer_irq
gpio_irq
uart_irq4
22
ICU
GPIO
Ti
main_bus_writemain_bus_read RAM XRAM
Periph_Bus
TBE2TBE1
Timer
UART
periph_bus_writeperiph_bus_read
xram_writexram_read
ram_writeram_read
uart_writet d
gpio_writei d
Page 10Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
uart_read gpio_read
Fig. 2.2: Hierarchical Function Calls
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 11Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Refinement from C to TL
SPINNI C Model
Structure Based Refinement
uart_readuart write
Module Access Type
SPINNI C Model
uart_writeram_read... ...
SPINNI TL UART ModuleModule Access
Page 12Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Refinement from C to TL
Combining Created TL Modules
irq_sigCPU
Main_Bus ICU timer_irqgpio_irq
uart_irq4
22GPIO
RAM XRAMPeriph_Bus
UART
2
Timer
UART
TBE2TBE1: sc_port : sc_export
UART
Page 13Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Fig. 3.1: Block Diagram of the SPINNI TL Model
Refinement from C to TL
Implementation of C Functions in Module Interfaces
irq_sigCPU
Main_Bus ICU timer_irqgpio_irq
uart_irq4
2ead
h_bu
s_re
admain_bus_read
RAM XRAMPeriph_Bus
22GPIO
Timer
gpio
_re
xram_read perip
ram_read
dRAM XRAMUART
: sc port : sc export
UART
uart
_rea
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TBE2TBE1: sc_port : sc_export
Refinement from C to TL
SPINNI TL Model
Reflects the functionality of the SPINNI VHDL model
Enables SW development, co-simulation of HW and SW
No timing information
no prediction for the overall performance of the system
Page 15Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 16Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Timing Accuracy
Measure & add timing information
TL ModelVHDL RTL ModelTiming
Information
TL ModelVHDL RTL Model
time
time
time
Basic ways to add timingy g¬ Time-based: wait(time)
¬ Event-based: event_name.notify(time)
Page 17Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
¬ …
Timing Accuracy
Selected Problem Cases
1. How to align timing after reset ?
2. How to align instruction processing timing ?
Page 18Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Timing Accuracy
Align Timing after Reset
lreset
i t 1
n cycles
0 4register1(a) In the SPINNI VHDL Model
void initialize() {
0 4
triggervoid initialize() {register1 = 0;
}
void module_run() {register1 = 4;}
// notify event// after n cycles
trigger
(b) In the SPINNI TL Modelregister1 0 4
Page 19Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
* assuming the reset lasts n clock cycles in the SPINNI VHDL model
(b) In the SPINNI TL Model
Timing Accuracy
Align Instruction Processing Timing
Clock Cycle # 0 1 2 3 4 5
Stage 1: Instruction Fetch
Stage 2: Execution
(a) Two Pipeline Stages in the SPINNI VHDL Model
(b) No Pipeline Stage in the SPINNI TL Model
wait (time)
Page 20Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Note: “time” in “wait (time)” equals to 1 clock period of the SPINNI VHDL Model
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 21Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Validation of Concept
Regression Automation for Functional Comparison
50 test cases k-th Test Case
C Model
N VHDL E ti N TL E ti
VHDL Model TL Models
CNew VHDL Execution
InstructionTrace
MemoryDumps
New TL Execution
InstructionTrace
MemoryDumps
New C Execution
InstructionTrace
MemoryDumps
Golden Reference
InstructionT
MemoryD
Page 22Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Trace Dumps
Validation of Concept
Selected Test Simulation Time VHDL (ns) Simulation Time TL (ns)
Algorithmic Test 42942800 42942800
I/O Test 5441500 5441500
IRQ Test 7331400 7331400
Fig. 5.1: Simulation Time Comparison between VHDL & Timed TL Models
404550 User CPU Time VHDL (s)
User CPU Time TL (s)
2025303540
Selected Test
User CPU Time VHDL (sec.)
User CPU Time TL (sec.)
Factor
Algorithmic 40.87 2.87 14
05
101520 g
Test0.87 .87
I/O Test 14.40 1.25 12
IRQ Test 18.21 1.51 12
Page 23Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Test case 1 Test case 2 Test case 3
Fig. 5.2: User CPU Time Comparison between VHDL & Timed TL Models
Outline
1. Principles of TL Modeling
2. SPINNI VHDL & C Models
3. Refinement from C to TL
4. Timing Accuracy
5. Validation of Concept
6. Conclusion & Outlook
Page 24Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Conclusion & Outlook
Conclusion
SPINNI system with a clear architectureSPINNI system with a clear architecture
Shown how to refine C to TL model
Ways for adding timing information to the TL modelWays for adding timing information to the TL model
Cases to make the timing accurate using RTL model
Method for functional comparison results of timing comparisonMethod for functional comparison, results of timing comparison
Outlook
Adopt the forthcoming TLM standard v2.0 for further improvement of performance
Develop a methodology for fully automatic timing integration
Page 25Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008
Develop a methodology for fully automatic timing integration
Thank You!
Any Question?Any Question?
Contact: Hui Chen [email protected]
Page 26Consistent Modeling Technique for Accurate Transaction Level ModelsApril 22, 2008