connecting a ccd camera to sopc

© 2004 Xilinx, Inc. All Rights Reserved© 2004 Xilinx, Inc. All Rights Reserved

Implemented by :Alon Ben Shalom Yoni Landau

Project supervised by: Mony Orbach

High speed digital systems laboratory

Technion - Israel institute of technologydepartment of Electrical Engineering

A single semester ProjectA single semester Project

Final PresentationFinal Presentation

Spring 2007

© 2004 Xilinx, Inc. All Rights Reserved

Agenda Project Goals Devices & Environment Block Diagram Config Module Capture Module Frame capture algorithm Troubleshooting & Solutions Conclusions


Project Goals•Capture a single frame through a CCD camera and forward it to SOPC memory (BRAM) using Virtex II PRO.•Study VirtexIIpro development environment ( EDK 9.1) and the design tools ( HDL designer, Modelsim )

External power supply

ov5017

Adapter

XUP

Vertex II PROCCD Camera


CCD Camera - ¼ ” Monochrome digital camera

The M4088 digital camera is based on OV5017 CCD chip manufactured by OmniVision.Chip Interface : M4088 camera module.

M4088

Development Environment

FPGA - Xilinx VirtexIIpro EDK - platform studio 9.1 VHDL code was created using HDL Designer 2007.1

Logic simulation - Modelsim

Devices & Enviroment


Adapter is composed of 2 “Fairchild” buffers

Devices & Enviroment(Cont.)

CAMERABUFFERS

Connector to FPGA

Connector to Logic Analyzer

Buffers Ground

Buffers Vcc

Camera VCC & Ground


Block Diagram

CPU

OCM memory

PLB bus

OPB bus

PLB to OPB bridge

OUR COREBRAM memory

UART

SOPC structureModule is connected directly to PLB(Max throughput)CPU, using burst, samples core data and writes it to memory OCM – CPU’s instructionmemory


Core Block Diagram

We need to mux the signals since the high-Z state is not available inside the VERTEX IP.

Muxed signals are connected to the same connectors

Config

Capture

FPGA inputs MUX

Camera outputs

Address,OEB,CSB,WEB

Camera outputs

Data

FPGA output

Data,ready

Camera inputs


Config ModuleIn order to get a frame there’s a need to configure the

camera to user needs.It’s done by writing to a specific register in camera at

address “0101”.

The following figure illustrates a single byte write to a specific register.


Config Module (Cont.)The user configure the camera through C code. Data is delivered to

theConfig Module by the CPU, when start signal rise to ‘1’ the module

sets The relevant data to camera and the configuration is implemented.

The module is a state machine setting the data to camera


From C command to Module32 bit registers were

allocated by EDKData is transferred

from C code through the registers to Modules

No need to recompile HW whenever data changes

C code to Module interaction example

8

32 bit register – slv_reg00 31

Config module

Bits 0 to 7

Data to be written to camera register

Bits 8 to 11

Register address

4

WEB

OEB

Bit 12

reset start

Bit 30 Bit 31

Write command from the C code


After the user configured the camera he sets start to ‘1’ (through C Code) , the module starts setting the outputs to camera so the

frame data is Received from camera. Frame is composed of 384*288 pixels

(pixel is a byte) The following figure illustrates a frame data stream – It’s actually

reading A data register

Capture Module


The Module is composed of several sub modules interacting with each other in Order to synchronize FPGA with camera.

Capture Module (Cont.)

controller

Shift register

FIFO

coordinator

inputs outputs


Start rise to ‘1’ – Controller sets the Camera to data stream. When a new frame starts controller send “in_win” signal to shift Register for start storing data and send it to FIFO

Shift register counts 4 pixels (pixel=byte), it converts The 4 bytes to a 32 bits word and send a “ready” signal to FIFO

FIFO accumulates 8 words (32 bits each), when finished It sends “all_ready” signal to coordinator, which in response raises the

“all_reg_trig” signal to FIFO in order to move the 8 words to the second level in the FIFO and signal to the CPU to start reading. Coordinator waits for the CPU to write the Data to memory, when CPU finishes it sends to the Coordinator ACK signal

Capture Module – Behavioral Description

controller

Shift register

FIFO

coordinator

inputs outputs


The following diagram illustrates the stages of a frame capture

Frame capture algorithm

User pressed center key

Configure the camera

Do we have pixels to capture

* RESET the modules

* Direction control set to IN

* write ‘1’ to the start capture bit

Do we have data block ready to be

read?YES

NO

* Read all 8 32bit pixel data from the capture module

* Store the DATA at the bram memory

YES

Print to terminal the DATA from the bram memory

NO


Troubleshooting & SolutionsModule was originally connected to OPB - CPU didn’t

succeed writing data to memory on time due to the fact it should go over the PLB/OPB bridge (Real time system complication)

Module was moved to PLB

CPU

PLB bus

OPB bus

PLB to OPB bridge

BRAM memory

UART OUR CORE

BRAM memoryFor CPU


Troubleshooting & Solutions - Cont’d CPU instruction memory was connected to PLB – Bus is very

active Instruction memory was replaced by OCM – Low competition

over the PLB resourceOCM memory

CPU

PLB bus

OPB bus

PLB to OPB bridge

BRAM memory

UART

BRAM memoryFor CPU

OUR CORE


Troubleshooting & Solutions - Cont’dRead/Write bus access was too slow for data rateUsing Read/Write burst bus access to improve

throughput

Unreliable synchronization signal behavior of camera

Logic solution (debouncer)

Voltage mismatch between camera to FGPA

connectorsWe built an adapter to resolve this issue


Conclusions

A better solution for capturing a frame could be moving the data using DMA. This way there were much less bus transactions, therefore a much faster solution.


Thank you for your time!

connecting a ccd camera to sopc

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