Computer OrganizationCS224

Fall 2012

Lesson 26

Summary of Control Signals

add sub ori lw sw beq jRegDstALUSrcMemtoRegRegWriteMemWriteBranchJumpExtOpALUctr<1:0>

1001000x

Add

1001000x

Sub

01010000

Or

01110001

Add

x1x01001

Add

x0x0010x

Sub

xxx0001x

xxx

funcop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

coding from green card

10 0000 10 0010 Not Important

Multilevel Decoding

12-input control will be very large (212 = 4096)

To keep decoder size smaller, decode some control lines in each stage

Since only R-type instructions (with op = 000000) need function field bits, give these to ALU control

func

MainControl

op

6

ALUControl(Local)

N

6ALUop

ALUctr

2

AL

U

Control signals to datapath

Multilevel Decoding: Main Control Table

R-type ori lw sw beq jRegDstALUSrcMemtoRegRegWriteMemWriteBranchJumpExtOp

ALUop<1:0>

1001000x

“R-type”

01010000

Or

01110001

Add

x1x01001

Add

x0x0010x

Sub

xxx0001x

xx

op 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010

(compare with Fig 4.22)

ALU Control

ALU used for Load/Store: F = add Branch: F = subtract R-type: F depends on funct field

§4.4 A S

imple Im

plementation S

cheme

ALU control Function

0000 AND

0001 OR

0010 add

0110 subtract

0111 set-on-less-than

1100 NOR

ALU Control

Assume 2-bit ALUOp derived from opcode Combinational logic derives ALU control

opcode ALUOp Operation funct ALU function ALU control

lw 00 load word XXXXXX add 0010

sw 00 store word XXXXXX add 0010

beq 01 branch equal XXXXXX subtract 0110

ori 11 OR immediate XXXXXX or 0001

R-type 10 add 100000 add 0010

subtract 100010 subtract 0110

AND 100100 AND 0000

OR 100101 OR 0001

set-on-less-than 101010 set-on-less-than 0111

The Main Control Unit

Control signals derived from instruction

0 rs rt rd shamt funct

31:26 5:025:21 20:16 15:11 10:6

35 or 43 rs rt address

31:26 25:21 20:16 15:0

4 rs rt address

31:26 25:21 20:16 15:0

R-type

Load/Store

Branch

opcode always read

read, except for load

write for R-type and load

sign-extend and add

Datapath With Control

R-Type Instruction

Load Instruction

Branch-on-Equal Instruction

Implementing Jumps

Jump uses word address

Update PC with concatenation of Top 4 bits of old PC 26-bit jump address 00

Need an extra control signal decoded from opcode

2 address

31:26 25:0

Jump

Datapath With Jumps Added

Figure 4.24

5 5 5

Putting It All Together

32

ALUctr

Clk

busW

RegWr

3232

busA

32busB

Rw Ra Rb32 32-bitRegisters

Rs Rt

RegDst

Exten

der

3216imm16

ALUSrc

ExtOp

MemtoReg

Clk

Data InWrEn

32Adr

DataMemory

32

MemWr

InstructionFetch Unit

Clk

Zero

Instruction[31:0]

JumpBranch [21:25]

[16:20]

[11:15]

[0:15]

Imm16RdRsRt

MU

X

MU

X

AL

U

RtRd

Mux1 0

0

1

0

1

MainControl

op6

ALUControl func

6

3ALUop

ALUctr3

RegDst

ALUSrc

:Instr[5:0]

Instr[31:26]

Single Cycle Processor

Advantages Single cycle per instruction makes logic and clock simple All machines would have a CPI of 1

Disadvantages Inefficient utilization of memory and functional units since different

instructions take different lengths of time- Each functional unit is used only once per clock cycle

- e.g. ALU only computes values a small amount of the time

Cycle time is the worst case path long cycle times!- Load instruction

– PC CLK-to-Q + – instruction memory access time + – register file access time + – ALU delay + – data memory access time + – register file setup time + – clock skew

All machines would have a CPI of 1, with cycle time set by the longest instruction!

Performance Issues

Longest delay determines clock period Critical path: load instruction Instruction memory register file ALU data memory

register file

Not feasible to vary period for different instructions

Violates design principle Making the common case fast

We will improve performance by pipelining

Single cycle datapath => CPI=1, CCT => long

5 steps to design a processor

• 1. Analyze instruction set => datapath requirements

• 2. Select set of datapath components & establish clock methodology

• 3. Assemble datapath meeting the requirements

• 4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.

• 5. Assemble the control logic

Control is the hard part

MIPS makes control easier

• Instructions same size

• Source registers always in same place

• Immediates same size, location

• Operations always on registers/immediates

Summary

Control

Datapath

Memory

ProcessorInput

Output