computer function-and-interconnection 3
DESCRIPTION
my reportTRANSCRIPT
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Top Level View of Computer Function and Interconnection
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Program ConceptHardwired systems are inflexibleGeneral purpose hardware can do different
tasks, given correct control signalsInstead of re-wiring, supply a new set of
control signals
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What is a program?A sequence of stepsFor each step, an arithmetic or logical
operation is doneFor each operation, a different set of control
signals is needed
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Function of Control UnitFor each operation a unique code is provided
e.g. ADD, MOVEA hardware segment accepts the code and
issues the control signals
We have a computer!
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ComponentsThe Control Unit and the Arithmetic and
Logic Unit constitute the Central Processing Unit
Data and instructions need to get into the system and results outInput/output
Temporary storage of code and results is neededMain memory
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Computer Components:Top Level View
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Instruction Cycle (Processing for a single instruction)Two steps:
FetchExecuteHalt if machine is turned off, unrecoverable
error
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Fetch CycleProgram Counter (PC) holds address of next
instruction to fetchProcessor fetches instruction from memory
location pointed to by PCIncrement PC
Unless told otherwiseInstruction loaded into Instruction Register
(IR)Processor interprets instruction and performs
required actions
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Execute CycleProcessor-memory
Data transfer between CPU and main memoryProcessor I/O
Data transfer between CPU and I/O moduleData processing
Some arithmetic or logical operation on dataControl
Alteration of sequence of operationse.g. jump
Combination of above
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Example of Program Execution
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Instruction Cycle State Diagram
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InterruptsMechanism by which other modules (e.g. I/O)
may interrupt normal sequence of processingProgram
e.g. overflow, division by zeroTimer
Generated by internal processor timerUsed in pre-emptive multi-tasking
I/Ofrom I/O controller
Task completion, variety of errorsHardware failure
e.g. Power failure, memory parity error
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InterruptsA way to improve the processing efficiency Slow peripherals can not comprehend speedy
processorProcessor remains in stall state until device catches upDifferent tasks interleaved with WRITE
Without interrupts, program would wait for IO to complete
May Periodically pole the device.
With interrupts, user can execute other instructions while IO is performed
OS and Processor manage the suspension and resumption of program
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Program Flow Control
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Interrupt CycleAdded to instruction cycleProcessor checks for interrupt
Indicated by an interrupt signalIf no interrupt, fetch next instructionIf interrupt pending:
Suspend execution of current program Save context (address of next instruction to be
executed)Set PC to start address of interrupt handler routineProcess interruptRestore context and continue interrupted program
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In the Interrupt handler routineFetch interrupt handler instructions from
memoryInterrupt handler routines are part of OS Extra instructions are executed but still save
processing power
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Transfer of Control via Interrupts
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Instruction Cycle with Interrupts
Hanggan d2 lng report ko mwaah
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Program TimingShort I/O Wait
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Program TimingLong I/O Wait
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Instruction Cycle (with Interrupts) - State Diagram
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Multiple Interrupts-IWe may have more than one interrupts
A program receiving data from communication line and printing data to a printing device
Option to handle multiple interrupts
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Multiple Interrupts-IIDisable interrupts
Processor will ignore further interrupts whilst processing one interrupt
Interrupts remain pending and are checked after first interrupt has been processed
Interrupts handled in sequence as they occur (No Priority task) Data arriving from communication line should be absorbed
immediatelyDefine priorities
Low priority interrupts can be interrupted by higher priority interrupts
When higher priority interrupt has been processed, processor returns to previous interrupt E.g. Printer 2, disk 4, communication line 5
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Multiple Interrupts - Sequential
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Multiple Interrupts – Nested
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Time Sequence of Multiple Interrupts
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ConnectingAll the units must be connectedDifferent type of connection for different type
of unitMemoryInput/OutputCPU
Collection of paths connecting various structures are called interconnection structures.
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Computer Modules
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Memory ConnectionReceives and sends dataReceives addresses (of locations)Receives control signals
ReadWriteTiming
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Input/Output Connection(1)Similar to memory from computer’s
viewpointOutput
Receive data from computerSend data to peripheral
InputReceive data from peripheralSend data to computer
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Input/Output Connection(2)Receive control signals from computerSend control signals to peripherals
e.g. spin diskReceive addresses from computer
e.g. port number to identify peripheralSend interrupt signals (control)
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CPU ConnectionReads instruction and dataWrites out data (after processing)Sends control signals to other unitsReceives (& acts on) interrupts
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BusesThere are a number of possible
interconnection systemsSingle and multiple BUS structures are most
commone.g. Control/Address/Data bus (PC)e.g. Unibus (DEC-PDP)
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What is a Bus?A communication pathway connecting two or
more devicesOften grouped
A number of channels in one buse.g. 32 bit data bus is 32 separate single bit
channelsPower lines may not be shown
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Data BusCarries data
Remember that there is no difference between “data” and “instruction” at this level
Width is a key determinant of performance8, 16, 32, 64 bit
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Address busIdentify the source or destination of datae.g. CPU needs to read an instruction (data)
from a given location in memoryBus width determines maximum memory
capacity of systeme.g. 8080 has 16 bit address bus giving 64k
address space
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Control BusControl and timing information
Memory read/write signalIO Read/WriteTransfer Ack.Interrupt request (indicates interrupt is pending)Interrupt Ack. (pending intrrupt acknowledged)Sending and requesting data requires:
Request use of bus Transfer of data via bus
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Bus Interconnection Scheme
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ArrangementWhat do buses look like?
Parallel lines on circuit boardsRibbon cablesStrip connectors on mother boardsOn Chip and board wires
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Physical Realization of Bus Architecture
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Single Bus ProblemsLots of devices on one bus leads to:
Propagation delays Long data paths mean that co-ordination of bus use
can adversely affect performance Bus may become a bottleneck as aggregate
aggregate data transfer approaches bus capacity Increase the data rate (32-bit,64-bit) Still growing application demands can t be met
Most systems use multiple buses to overcome these problems
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•Devices with high speed demand are closer to processor•But independent of processor ( Processor’s Architectural changes have no affect on high speed bus)
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Bus TypesDedicated
Separate data & address linesMultiplexed (time multiplexing)
Shared linesAddress valid or data valid control lineAdvantage - fewer lines, cost benefit Disadvantages
More complex control Ultimate performance
Physical Dedication (IO bus connects IO modules only)
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Bus ArbitrationMore than one module controlling the buse.g. CPU and DMA controllerOnly one module may control bus at one timeArbitration may be centralised or distributed
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Centralised or Distributed ArbitrationCentralised
Single hardware device controlling bus access Bus Controller Arbiter
DistributedEach module may claim the busControl logic on all modules
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TimingCo-ordination of events on busSynchronous
Events determined by clock signalsControl Bus includes clock lineA single 1-0 is a bus cycleAll devices can read clock lineUsually sync on leading edgeUsually a single cycle for an event
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PCI BusPeripheral Component InterconnectionIntel released to public domain32 or 64 bit50 lines
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PCI Bus Lines (required)Systems lines
Including clock and resetAddress & Data
32 time mux lines for address/dataInterrupt & validate lines
Interface ControlArbitration
Not sharedDirect connection to PCI bus arbiter
Error lines
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PCI Bus Lines (Optional)Interrupt lines
Not sharedCache support64-bit Bus Extension
Additional 32 linesTime multiplexed2 lines to enable devices to agree to use 64-bit
transferJTAG/Boundary Scan
For testing procedures
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PCI CommandsTransaction between initiator (master) and
targetMaster claims busDetermine type of transaction
e.g. I/O read/writeAddress phaseOne or more data phases
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Foreground ReadingStallings, chapter 3 (all of it)www.pcguide.com/ref/mbsys/buses/
In fact, read the whole site!www.pcguide.com/