computer-aided design (cad) logic synthesis tutorial

ComputerComputer--Aided Design (CAD) Aided Design (CAD) Logic Synthesis TutorialLogic Synthesis Tutorial

Prepared by Prepared by –– Ray CheungRay Cheung

What is Logic Synthesis?What is Logic Synthesis?�� Logic SynthesisLogic Synthesis --Takes the circuit Takes the circuit description at the description at the RTL level and RTL level and generates an optimal generates an optimal implementation in implementation in terms of an terms of an interconnection of interconnection of logic gates.logic gates.

Tutorial Outline:Tutorial Outline:�� SIS TutorialSIS Tutorial�� Combinational & Sequential CircuitCombinational & Sequential Circuit�� Rewiring TutorialRewiring Tutorial�� ATPG techniqueATPG technique�� RAMBO, REWIRE, RAMBO, REWIRE, �� RAMFIRE, GBAWRAMFIRE, GBAW�� GBAW lab exercisesGBAW lab exercises

Part 1: Introduction to SIS packagePart 1: Introduction to SIS packageSequential Interactive Synthesis Sequential Interactive Synthesis

Outline : SISOutline : SIS�� Elements inside SISElements inside SIS�� Interactive SIS vs. SIS libraryInteractive SIS vs. SIS library�� BLIF & SIS file formatsBLIF & SIS file formats�� XX--Windows based SIS (XSIS)Windows based SIS (XSIS)�� SIS automated scriptsSIS automated scripts�� Technology mapping librariesTechnology mapping libraries

What is SIS?What is SIS?�� SIS is an interactive tool for synthesis and SIS is an interactive tool for synthesis and optimization of sequential and combinational optimization of sequential and combinational circuits.circuits.�� Why it is so important?Why it is so important?�� It serves as a framework for various algorithms It serves as a framework for various algorithms can be tested and compared.can be tested and compared.�� It can be used standalone or integrated into other It can be used standalone or integrated into other programs.programs.�� It provides a wellIt provides a well--defined library for us.defined library for us.�� The current RAMBO and GBAW are both The current RAMBO and GBAW are both implemented on top of the SIS library.implemented on top of the SIS library.

The History of SISThe History of SIS�� It was born in UC BerkeleyIt was born in UC Berkeley�� Built on top of MIS package which is a Built on top of MIS package which is a logic optimization system in 90logic optimization system in 90’’ ..

�� The latest SIS version is The latest SIS version is ““ sissis--1.41.4”” ..�� It is particularly useful for synthesizing It is particularly useful for synthesizing and optimizing sequential circuits.and optimizing sequential circuits.

SIS FamilySIS Family�� It containsIt contains�� NOVA (State assignment)NOVA (State assignment)�� JEDI (State assignment)JEDI (State assignment)�� STAMINA (State minimization)STAMINA (State minimization)�� SRED (State minimization)SRED (State minimization)�� ESPRESSO (Boolean function minimization)ESPRESSO (Boolean function minimization)�� BLIF2VST (BLIF to structural VHDL translator)BLIF2VST (BLIF to structural VHDL translator)�� VST2BLIF (structural VHDL to BLIF translator)VST2BLIF (structural VHDL to BLIF translator)�� XSIS (a graphical interface to SIS)XSIS (a graphical interface to SIS)

SIS PackageSIS Package

SIS CapabilitiesSIS Capabilities�� All the capabilities are controlled All the capabilities are controlled interactively by the user, include:interactively by the user, include:�� State minimizationState minimization�� State assignmentState assignment�� Optimization for area and delay by using Optimization for area and delay by using retimingretiming�� Optimization by using the standard Optimization by using the standard algebraic and Boolean combinational algebraic and Boolean combinational techniques from MISII, techniques from MISII, ……

SIS ShellSIS Shell

� Input your command here

SISSIScommands?commands?

Our concern Our concern –– SIS LibrarySIS Library

SIS LibrarySIS LibraryModel the circuit

Model the logic gates

A closer look A closer look –– SIS librarySIS library

Library PathLibrary Path

BLIF FormatBLIF Format�� What is BLIF?What is BLIF?�� Berkeley Logic Interchange FormatBerkeley Logic Interchange Format�� Is it the same as our *.sis files?Is it the same as our *.sis files?�� Yes, just different extension.Yes, just different extension.�� It is used to describe a logicIt is used to describe a logic--level level

hierarchical circuit in textual form.hierarchical circuit in textual form.�� The circuit can be an arbitrary The circuit can be an arbitrary combinational or sequential network.combinational or sequential network.

BLIF filesBLIF files

BLIF formatBLIF format

Exercise : Can you sketch the circuit?

XSISXSIS

SIS ScriptsSIS Scripts�� Some carefully crafted standard scripts Some carefully crafted standard scripts of of misIImisII operations.operations.

�� Used to automate the process and Used to automate the process and guide the optimization steps.guide the optimization steps.

�� They are developed by experienced They are developed by experienced experts. experts.

�� Any novice designer can easily use Any novice designer can easily use these scripts.these scripts.

SIS ScriptsSIS Scripts

GenlibGenlib FormatFormat�� Used to specify library gates in SIS.Used to specify library gates in SIS.

Logic function

Delay and load information

How to Map Circuit?How to Map Circuit?�� Technology mapping issueTechnology mapping issue

Map by mcnc1.genlib

How about mcnc11.genlib?How about mcnc11.genlib?Map into 2-input gates

Interactive EnvironmentInteractive Environment

Mapping LibraryMapping Library

Script.booleanScript.boolean Reduce the number of literals

Script.algebraicScript.algebraic

Area calculationArea calculation

�� A)A) F = XF = X’’YZ + XYZ + X’’YZYZ’’ + XZ+ XZ�� 8 literals (X8 literals (X’’ , Y, Z, X, Y, Z, X’’ , Y, Z, Y, Z’’ , X, Z), X, Z)�� B) F = XB) F = X’’Y(Z + ZY(Z + Z’’ ) + XZ = X) + XZ = X’’Y + XZY + XZ�� 4 literals (X4 literals (X’’ , Y, X, Z), Y, X, Z)

Part 2: Combinational and Part 2: Combinational and Sequential Circuit SynthesisSequential Circuit Synthesis

Outline : Circuit SynthesisOutline : Circuit Synthesis�� Logic Synthesis FundamentalsLogic Synthesis Fundamentals�� Combinational CircuitCombinational Circuit�� It has outputs that depend only on the current It has outputs that depend only on the current value of the inputs.value of the inputs.�� Sequential CircuitSequential Circuit�� Composes of combinational logic blocks and Composes of combinational logic blocks and registers.registers.�� It has outputs that may depend upon the past It has outputs that may depend upon the past value as well as the current input values.value as well as the current input values.

Logic Synthesis FundamentalsLogic Synthesis Fundamentals�� Refer to CEG 5330 course materialsRefer to CEG 5330 course materials�� Cover, minimum cover, prime, Cover, minimum cover, prime, ……�� The Espresso MinimizerThe Espresso Minimizer�� Cube, Kernel, CoCube, Kernel, Co--kernelkernel�� TwoTwo--level logic minimizationlevel logic minimization�� MultiMulti--level logic minimizationlevel logic minimization�� Sequential vs. CombinationalSequential vs. Combinational�� Technology mapping, Technology mapping, ……

Combinational CircuitCombinational Circuit

Synchronous circuit & Synchronous circuit & its representationits representation

SDC, ODC & EDCSDC, ODC & EDC�� Satisfiability donSatisfiability don’’ t care sets (SDC)t care sets (SDC)�� It captures conditions which can never It captures conditions which can never

happen in the network.happen in the network.�� Observability donObservability don’’ t care sets (ODC)t care sets (ODC)�� It captures changes which may occur It captures changes which may occur

without affecting the outputs.without affecting the outputs.�� External donExternal don’’ t care sets (EDC)t care sets (EDC)�� UserUser--specified specified

State Transition Graph (STG)State Transition Graph (STG)�� Each state is symbolicEach state is symbolic�� STG and its logic representationSTG and its logic representation

STG ManipulationsSTG Manipulations�� From STG to From STG to netlistnetlist�� State minimizationState minimization�� Produce a machine with fewer statesProduce a machine with fewer states�� State assignmentState assignment�� Assign a binary code for each symbolic stateAssign a binary code for each symbolic state�� A latch is used to store each bit of the binary codeA latch is used to store each bit of the binary code�� STG extractionSTG extraction�� Inverse of state assignmentInverse of state assignment�� Extract the STG from the logic Extract the STG from the logic netlistnetlist�� SIS command: SIS command: ““ stg_extractstg_extract””

Sequential Circuit OptimizationSequential Circuit Optimization�� State minimization & assignment of FSMState minimization & assignment of FSM�� Retiming techniquesRetiming techniques�� Reduce cycle timeReduce cycle time�� Minimize the number of registersMinimize the number of registers�� CycleCycle--Time MinimizationTime Minimization�� ResynthesisResynthesis�� Particularly use between registersParticularly use between registers�� RewiringRewiring

Rewiring Rewiring ExampleExampleBoth logic Both logic gates and the gates and the number of FF number of FF are reduced.are reduced.

Part 3: Rewiring EnginesPart 3: Rewiring Engines

Outline : Rewiring EnginesOutline : Rewiring Engines�� IntroductionIntroduction�� ATPG TechniqueATPG Technique�� RAMBORAMBO�� REWIREREWIRE�� RAMFIRERAMFIRE�� Graph based TechniqueGraph based Technique�� GBAWGBAW

Introduction Introduction –– Alternative WiringAlternative Wiring�� What is Alternative Wire?What is Alternative Wire?�� Add a redundant wire into a circuit (so as to make) Add a redundant wire into a circuit (so as to make) �� Another wire (Another wire (target wiretarget wire) becomes redundant) becomes redundant�� Remove Remove target wiretarget wire..�� Without changing the circuit functionality.Without changing the circuit functionality.�� 2 fundamentally different approaches2 fundamentally different approaches�� RAMBO/RAMFIRE RAMBO/RAMFIRE –– Automatic Test Pattern Automatic Test Pattern Generation (ATPG)Generation (ATPG)--basedbased�� GBAW GBAW –– GraphGraph--basedbased

Alternative Wiring Alternative Wiring -- Application 1Application 1�� Useful in different areasUseful in different areas�� Logic Optimization Logic Optimization �� final circuit becomes smallerfinal circuit becomes smaller c g4

b g1 redundant d g5 O1

e alternative c’ g2 g6 wa wire

d wr O2

a g7 g8 g9 b g3

f

target wire

b g1 d g5 O1

e c’ g2 g6

c

a g8 g9 O2

b g3

f

Alternative Wiring Alternative Wiring -- Application 2Application 2�� Circuit PartitioningCircuit Partitioning�� the interconnect wires between partitions is reduced the interconnect wires between partitions is reduced from 3 to 2.from 3 to 2. e f a b O1

O2

c d

(a) An alternative wire in an irredundant circuit

e f a b O1

O2

c d

(b) No gain for logic synthesis, but gain for partitioning

ATPGATPGa

b

c

d

e

f•Logic Circuit

•A Fault

•A Fault values-a-1

•A Test Vector

Test Vector: (a, b, c, d, e) = (1, 0, 0, 1, 0)

11

00

00

00

11

11(0/1)(0/1)

(0/1)(0/1)11

00

DefinitionDefinition�� Transitive Transitive FaninFanin & & FanoutFanout�� If there is a path connected from If there is a path connected from nini to to njnj�� nini is the transitive is the transitive faninfanin of of njnj�� njnj is the transitive is the transitive fanoutfanout of of nini

ni nj

Propagation path

DefinitionDefinition�� Transitive Transitive FaninFanin & & FanoutFanout ConeCone�� FaninFanin Cone of wire w are the wires Cone of wire w are the wires

connecting the transitive connecting the transitive faninsfanins of of nini�� FanoutFanout Cone of wire w are the wires Cone of wire w are the wires connecting the transitive connecting the transitive fanoutsfanouts of of njnj

ni njw

Transitive FaninTransitive FaninNot Transitive

DefinitionDefinition�� Dominator d of a wire wDominator d of a wire w�� All paths from w to any primary outputs All paths from w to any primary outputs

have to pass through dhave to pass through d

POw

Dominator

Not Dominator

DefinitionDefinition�� Controlling ValueControlling Value�� It determines the output value of a gate It determines the output value of a gate

without considering the side inputswithout considering the side inputs�� 0 for AND gate0 for AND gate�� 1 for OR gate1 for OR gate�� Sensitizing/nonSensitizing/non--controlling valuecontrolling value�� Complement of controlling valueComplement of controlling value�� 1 for AND gate1 for AND gate�� 0 for OR gate0 for OR gate

TestingTesting�� Single StuckSingle Stuck--at (SSA) faultat (SSA) fault�� The wire will always give 0 or 1The wire will always give 0 or 1�� StuckStuck--at fault Testat fault Test�� Propagate the faultPropagate the fault�� Set the dominatorsSet the dominators’’ side inputs to sensitizing value side inputs to sensitizing value

to propagate the fault to any primary outputto propagate the fault to any primary output�� Activate the faultActivate the fault�� Set the wire under test to 0 for sSet the wire under test to 0 for s--aa--1 or 1 for s1 or 1 for s--aa--00

TestingTesting

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9

For d->g6 stuck at 1 testPropagate the fault

11

00

Activate the fault

D

D

D D

Test for stuck-at 1

0 D

0

1

1

10

0

0

TestingTesting�� The values are called Mandatory The values are called Mandatory

Assignment (MA)Assignment (MA)�� MAs must be satisfiedMAs must be satisfied�� The MAs that used to propagate the The MAs that used to propagate the

fault are called Observability Mandatory fault are called Observability Mandatory AssigmentAssigment (OMA)(OMA)

TestingTesting

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9

1

1

11

00

0 D

D

D

D D

Green is OMA!!!1

00

0

0

How RAMBO worksHow RAMBO works

a

b

c

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g7g8 g9

Wire becomes redundant

g6d

REWIREREWIRE�� Proposed by Professor Proposed by Professor S.C.ChangS.C.Chang in in

““ Fast Boolean Optimization by Fast Boolean Optimization by RewiringRewiring”” in 1996in 1996

�� ATPGATPG--based algorithmbased algorithm�� Speed: Speed: �� GBAW > REWIRE > RAMBOGBAW > REWIRE > RAMBO�� AWsAWs Searching Power: Searching Power: �� RAMBO > REWIRE > GBAWRAMBO > REWIRE > GBAW

How REWIRE worksHow REWIRE works

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9

Every node is a destination node, nd

Find OMA for nd

1. Set all the dominators side input to non-controlling value

1

1

0 2. Recursive forward implication3. Recursive backward implication

11

Generate an array of wt

How REWIRE works (2)How REWIRE works (2)

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9


Find OMA for nd


Filter irredundant wire from wt

1

0

1

11

1

1. Transitive fanin cone of nd2. Transitive fanout cone of nd

3. k levels of transitive fanin of dominator of nd

17 wires in wt

How REWIRE works (3)How REWIRE works (3)

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9


Find OMA for nd



1

0

1

11

1

All the direct inputs of an AND {OR} gate are irredundant if the AND gate has an OMA of 0 {1}

If one of the input node of an AND {OR} gate has an OMA of 0 {1}, all other input wires are irredundant

12 wires in wt

00 0

0

D_ D_

D_D_

How REWIRE works (4)How REWIRE works (4)vv

a

b

c

d

d

ec

b

f

o1

o2

g1

g2

g3

g4

g5

g6g7

g8 g9


Find OMA for nd



Perform stuck-at-fault test at wt

Determination of alternative wires

Suppose we consider d->g60

0

11

1 1Finally, we get the alternative wire g1->g6 and o1->g6 for target wire d->g6

D_

RAMFIRE RAMFIRE -- SingleSingle--Pass Redundancy Pass Redundancy Addition And RemovalAddition And Removal

�� Operation 1Operation 1: Given a target wire to : Given a target wire to be removed, which redundant wires, be removed, which redundant wires, when added, will make redundant?when added, will make redundant?

�� Operation 2Operation 2: After the addition of a : After the addition of a redundant wire , which wires become redundant wire , which wires become redundant and hence removable?redundant and hence removable?

�� RAMFIRE identifies redundant wires in RAMFIRE identifies redundant wires in one pass without trialone pass without trial--andand--error search.error search.

tw

tw

aw

GBAWGBAW** ---- No Need of Boolean KnowledgeNo Need of Boolean Knowledge..�� High High Locality propertiesLocality properties on on AWsAWs observed in benchmarks observed in benchmarks (analogy: RISC v.s. CISC)(analogy: RISC v.s. CISC)�� TopologicalTopological locality: locality: 96% 196% 1stst. . AwsAws are 2are 2--locallocal�� PatternPattern locality: very locality: very uneven appearanceuneven appearance of of AWsAWspatternspatterns�� ApplicationApplication locality: probably no need to try all patternslocality: probably no need to try all patterns�� A PreA Pre--analyzed Pattern (graph) analyzed Pattern (graph) -- based AW Schemebased AW Scheme�� Methodology: pattern matchingMethodology: pattern matching�� Advantage: Advantage: Fast, As EffectiveFast, As Effective

No need for porting ATPG packageNo need for porting ATPG packageEqually easy to do Equally easy to do backwardbackward transformations transformations �� **received received Honorable Mention AwardHonorable Mention Award of of IEEE International VLSI Design 2000IEEE International VLSI Design 2000

GBAWGBAW�� Most Most AWsAWs are close to target wiresare close to target wires�� GraphGraph--based AW schemebased AW scheme�� Search alternative wire by Search alternative wire by isomorphismisomorphism between between local sublocal sub--networks and the prenetworks and the pre--defined patterns.defined patterns.�� EasyEasy for both forward and backward search.for both forward and backward search.�� Use Use ConfigurationConfiguration to denote a Boolean network.to denote a Boolean network.�� No need of Boolean implication/operationsNo need of Boolean implication/operations..�� Powerful in finding alternative wires and Powerful in finding alternative wires and Very Very Fast!Fast!

GBAW GBAW –– ConfigurationConfiguration

(AND,2,1) (AND,2,2)

D1

a

bc

g1 g2

(b) A configuration of S

(AND,dc,1) (AND,dc,dc)

D2

a

bc

g1 g2

(c) Another configuration of S

�� A Boolean network G with its subA Boolean network G with its sub--network S. Below shows the mapping network S. Below shows the mapping from network to from network to configurationconfiguration..�� Node y define as a triplet Node y define as a triplet ((opop, , dd--((yy), ), dd++((yy))))�� op is the Boolean operator (AND, OR, NAND, NOR)op is the Boolean operator (AND, OR, NAND, NOR)�� dd--((yy) is the ) is the inin--degreedegree of y, of y, dd++((yy) is the ) is the outout--degreedegree of y.of y.�� (AND, dc, dc) (AND, dc, dc) �� both both faninsfanins or or fanoutsfanouts are also are also dondon’’ t caret care..g1

g2g3

GS

a

b

cd

f1

f2

(a) Boolean network G

How GBAW worksHow GBAW works�� Pattern MatchingPattern Matching�� No Boolean implicationNo Boolean implication

g1

g5

g2

g4

a

b g3

c

g6

g7g8

2-Local Pattern

00--local patternlocal pattern�� Bold line Bold line �� target wiretarget wire�� Dotted line Dotted line �� alternative wirealternative wire�� 00--local means the edge distance between local means the edge distance between target and alternative wire is 0.target and alternative wire is 0.

(op1,k,dc) (dc,dc,dc)

a2

g1 g2a1

ak

(op3,k,dc)

g3

(dc,dc,dc)

g4

11--local patternslocal patterns(op1,dc,1)

g1

(op2,dc,dc)

g2a

AND AND (or NAND)

(a) Case 1-1, op1=AND, op2 =AND (or NAND); or op1=OR, op2=OR(or NOR)

g1

g2

(op1,k,dc)

(op2,k,dc)

a1

a2

ak

.

.

.

(b) Case 1-2, op1=AND, op2 =AND (or NAND); or op1=OR, op2=OR(or NOR)

(op1,dc,1)

g1

(op2,dc,dc)

g2a

AND AND (or NAND)

(c) Case 1-3, op1=NOR, op2 =NAND (or AND); or op1=NAND, op2=OR(or NOR)

22--local patternslocal patterns(NOR,dc,1)

g1

(NOR,dc,dc)

g3a

(a) Case 2-1

g2

(NAND,dc,1)

g1

g4

(OR,dc,1)

(AND,k,dc)

a1

a2

ak

.

.

.

(b) Case 2-2

g2 g2

(AND,dc,1)

(NOR,dc,dc)or

(OR,dc,dc)

(OR,dc,h) (OR,dc,dc)

(c) Case 2-3

(AND,t,1)

(OR,s,dc)

(AND,h,dc)

(AND,s,dc)

dc

dc

dc

dc

dc

1...

t-1

1...

s-1

Forward alternative wire

Backward alternative wire

Forward & Backward capabilitiesForward & Backward capabilities�� Implement Reverse SearchingImplement Reverse Searching�� Increase Increase GBAWGBAW’’ss search powersearch power

Backward Order

Search from fanout to fanin

Search from fanin to fanout

Forward Order

Verification of 2Verification of 2--local patternlocal pattern

�� Target wire exists: gTarget wire exists: g33 = (((a*x)= (((a*x)’’ *y)*z)*y)*z)’’ = (((a= (((a’’ +x+x’’ )*y)*z))*y)*z)’’= ((= ((aa’’ yy + + xx’’ yy)*z))*z)’’�� Alternative wire exists: gAlternative wire exists: g33 = ((= ((aa’’ yy))’’ *(*(xx’’ yy))’’ *z)*z)’’ = original g= original g33

x (a*x)’ ((a*x)’*y)’y z

(((a*x)’*y)’*z)’

Pattern ClustersPattern Clusters�� What is the meaning of pattern Clusters?What is the meaning of pattern Clusters?

a

b2

bn

b1

g3a

b

g5

g1 g2

g4

g3

2-Local Pattern (Cluster 3 Set 6a)

2-Local Pattern (Cluster 1)

Pattern LocalityPattern Locality��Very uneven Very uneven appearance of AW appearance of AW patternspatterns

��Top figure:Top figure:�� Pattern Locality for 1Pattern Locality for 1--LocalLocal

��Bottom figure:Bottom figure:�� Pattern Locality for 2Pattern Locality for 2--LocalLocal

448 13 5691 181 2843010002000300040005000600011 12 13 111 131

MatchingFoundPattern Name

02004006008001000120021 23 24 26 2_2a 2_3a 2_4a 2_5 2_n3_2 2_n3_4 2_n3_6Matching Found

Pattern Name

Rewiring GUI interfaceRewiring GUI interface

�� The current user interface allows users interactively The current user interface allows users interactively locate any possible redundant rewires in the circuit by locate any possible redundant rewires in the circuit by using either GBAW, RAMBO and REWIRE.using either GBAW, RAMBO and REWIRE.

Benchmark:

small.blif

Rewiring GUI interfaceRewiring GUI interface

�� The system is built on top of Java and C languages.The system is built on top of Java and C languages.

Benchmark:

des.blif

Rewiring FrameworkRewiring Framework

design methodology

efficient rewire engine

application

Application-independent rewiring engine provides efficient routines for logic alternative exploration

Application-independent rewiring engine provides efficient routines for logic alternative exploration

Logical/Physical Co-Design

application

?

RAMBO / GBAW / …

AreaArea

3

Power

2

Delay

1

?

5

?

4

Part 4 Part 4 –– Implementation detailsImplementation detailsChecking fanChecking fan--in and fanin and fan--out andout andlab exerciseslab exercisesUsing sr_local2_n3_6.c as an example, we show how Using sr_local2_n3_6.c as an example, we show how the code run and how the node is namedthe code run and how the node is named

main()main()……

[program initialization][program initialization]……

sramsram();();……

[statistic reporting][statistic reporting]……

sramsram()()for a wire <for a wire <node1node1 --> > fanout1fanout1>>

transformtransformxxxxxx(wire(wire););[match different AW patterns][match different AW patterns]

For greedy simplificationFor greedy simplificationsramsram()()for a wire <for a wire <node1node1 --> > fanout1fanout1>>transformtransformxxxxxx(wire(wire););[match different AW patterns][match different AW patterns][transform the first matched pattern][transform the first matched pattern]

For incremental perturbationFor incremental perturbationsramsram()()for a wire <for a wire <node1node1 --> > fanout1fanout1>>transformtransformxxxxxx(wire(wire););[match different AW patterns][match different AW patterns][record all matched patterns][record all matched patterns]transform_incremental();transform_incremental();[transform the min[transform the min--cost pattern]cost pattern]

/*** fanout1 ***/if (!is_node_ok(fanout1))

return MY_FAIL;if (gate_type(fanout1) != T_NOT)

return MY_FAIL;

fo1_not = fanout1;fanout1 = node_get_fanout(fo1_not, 0);

if (!is_node_ok(fanout1))return MY_FAIL;

if (gate_type(fanout1) == T_PO)return MY_FAIL;

if (node_num_fanin(fanout1) != 2)return MY_FAIL;

if (node_num_fanout(fanout1) != 1)return MY_FAIL;

/*** fanout2 ***/fanout2 = node_get_fanout(fanout1, 0);if (!is_node_ok(fanout2))

return MY_FAIL;if (gate_type(fanout2) == T_PO)

return MY_FAIL;if (node_num_fanout(fanout2) != 1)

return MY_FAIL;if (node_num_fanin(fanout2) != 2)

return MY_FAIL;



return MY_FAIL;

Check if any element with the structure is NULL(Function is_node_ok is defined in sr_util.c)

b g4a g1 g2 g3

g5fanout1node1Not yet checkedCheckingRequire further checkingCheckedNot yet checkedCheckingRequire further checkingChecked



return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Check whether the fan-out of fanout1 is a NOT gate

b g4a g1 g2 g3

g5fanout1node1



return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Rename fanout1 to fo1_notfanout1 now become the fan-out of the NOT gate

b g4a g1 g2 g3

g5fo1_notnode1 fanout1



return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Again check if any element with the structure is NULL

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Fan-out of fanout cannot be Primary Output

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

fanout1 must have 2 fan-in(s)

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

fanout1 must have 1 fan-out

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Name fanout2 be the fan-out of fanout1

b g4a g1 g2 g3

g5fo1_notnode1 fanout1 fanout2



return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Check if any element with the structure is NULL

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Fan-out of fanout2 cannot be Primary Output

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Number of fan-out of fanout2 must be 1

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Number of fan-in(s) of fanout2 must be 2

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Name fan-out of fanout2 be fanout3

b g4a g1 g2 g3

g5fo1_notnode1 fanout1 fanout2 fanout3



return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

Check if any element with the structure is NULL

b g4a g1 g2 g3




return MY_FAIL;










return MY_FAIL;



return MY_FAIL;

fanout3 itself cannot be Primary Output

b g4a g1 g2 g3


gt_fo1 = gate_type(fanout1);gt_fo2 = gate_type(fanout2);gt_fo3 = gate_type(fanout3);

/*** fanin1 ***/match=0;

foreach_fanin(fanout2,j1,temp){if (temp == fanout1)

continue;fanin1 = temp;

if (!is_node_ok(fanin1))continue;

if (gate_type(fanin1) == T_PO)continue;

if (node_num_fanout(fanin1) != 1)continue;

gt_fi1 = gate_type(fanin1);

foreach_fanin(fanin1,j2,temp){fanin2 = temp;if (!is_node_ok(fanin2))

continue;if (gate_type(fanin2) == T_PO)

continue;if (gate_type(fanin2) != T_NOT)

continue;node2 = node_get_fanin(fanin2, 0);if (!is_node_ok(node2))

continue;if (gate_type(node2) == T_PO)

continue;foreach_fanin(fanout1,j3,temp){

fanin3 = temp;if (!is_node_ok(fanin3))


continue;if (!strcmp(fanin3->name, node1->name))

continue;if (!strcmp(fanin3->name, node2->name)){

match=1;break;

}if (match==1) break;


}if (match==1) break;}

if (match==0) return MY_FAIL;

Now, let’s consider this block of codesName the other fan-in of fanout2 be fanin1Check if fanin1 a non-primary output and has only 1 fan-out

b g4a g1 g2 g3

g5fo1_notnode1 fanout1 fanout2 fanout3fanin1

gt_fo1 = gate_type(fanout1);gt_fo2 = gate_type(fanout2);gt_fo3 = gate_type(fanout3);

/*** fanin1 ***/match=0;

foreach_fanin(fanout2,j1,temp){if (temp == fanout1)

continue;fanin1 = temp;

if (!is_node_ok(fanin1))continue;

if (gate_type(fanin1) == T_PO)continue;

if (node_num_fanout(fanin1) != 1)continue;

gt_fi1 = gate_type(fanin1);

foreach_fanin(fanin1,j2,temp){fanin2 = temp;if (!is_node_ok(fanin2))


continue;if (gate_type(fanin2) != T_NOT)

continue;node2 = node_get_fanin(fanin2, 0);if (!is_node_ok(node2))

continue;if (gate_type(node2) == T_PO)

continue;foreach_fanin(fanout1,j3,temp){

fanin3 = temp;if (!is_node_ok(fanin3))


continue;if (!strcmp(fanin3->name, node1->name))

continue;if (!strcmp(fanin3->name, node2->name)){

match=1;break;




if (match==0) return MY_FAIL;

Here are 3 nested for-loop (Marco)Name the fan-in of fanin1 to fanin2fanin2 must be a NOT gate and must be be a Primary OutputName the fan-in of fanin2 to node2match is a flag that check whether node2 is also fan-in of fanout1

b g4a g1 g2 g3

g5fo1_notnode1 fanout1 fanout2 fanout3fanin1fanin2node2

/*** g4 ***//*** cluster a ***/match=0;foreach_fanout(node1, gen1, fanout11) {

if (!is_node_ok(fanout11))continue;

if (gate_type(fanout11) == T_PO)continue;

if (!strcmp(fo1_not->name, fanout11->name))continue;

if (node_num_fanin(fanout11) != 2)continue;

foreach_fanout(node2, gen3, fanout12) {if (!is_node_ok(fanout12))

continue;if (gate_type(fanout12) == T_PO)

continue;if (node_num_fanin(fanout12) != 2)

continue;if (!strcmp(fanout1->name, fanout12->name))

continue;if (!strcmp(fanout11->name, fanout12->name)){

if (((gt_fo3 == T_NAND)||(gt_fo3 == T_AND))&& (((gt_fi1 == T_OR)&&(gt_fo2 == T_NAND)&&(gt_fo1 == T_OR))||((gt_fi1 == T_NOR)&&(gt_fo2 == T_OR)&&(gt_fo1 == T_NOR))

)){if (gate_type(fanout12) == T_OR){

not = 0;match=1;break;

}else if (gate_type(fanout12) == T_NOR){


}}else if (((gt_fo3 == T_NOR)||(gt_fo3 == T_OR))&& (

((gt_fi1 == T_OR)&&(gt_fo2 == T_AND)&&(gt_fo1 == T_OR))||((gt_fi1 == T_NOR)&&(gt_fo2 == T_NOR)&&(gt_fo1 == T_NOR))

)){if (gate_type(fanout12) == T_NOR){


}else if (gate_type(fanout12) == T_OR){


}}else if (((gt_fo3 == T_NAND)||(gt_fo3 == T_AND))&&(

((gt_fi1 == T_AND)&&(gt_fo2 == T_OR)&&(gt_fo1 == T_AND))||((gt_fi1 == T_NAND)&&(gt_fo2 == T_NAND)&&(gt_fo1 == T_NAND))

)){if (gate_type(fanout12) == T_NAND){


}else if (gate_type(fanout12) == T_AND){


}}else if (((gt_fo3 == T_NOR)||(gt_fo3 == T_OR))&&(

((gt_fi1 == T_AND)&&(gt_fo2 == T_NOR)&&(gt_fo1 == T_AND))||((gt_fi1 == T_NAND)&&(gt_fo2 == T_AND)&&(gt_fo1 == T_NAND))

)){if (gate_type(fanout12) == T_AND){


}else if (gate_type(fanout12) == T_NAND){


}}



Here are also several nested for-loopAfter performing some checking, we determine whether both node1 and node2 eventually meet at g4 after passing through a NOT gate.Finally, we check whether the combination of logic gates match the possible patterns

g4a g1 g2 g3

g5fo1_notnode1 fanout1 fanout2 fanout3fanin1fanin2node2b

#ifdef WIREprintf("2_n3_6 add: %s to %s\n",fanout11->name, fanout3->name);printf("2_n3_6 rm: %s to %s\n",fo1_not->name, fanout1->name);printf("2_n3_6 rm: %s to %s\n",fanin2->name, fanin1->name);

#endif#ifdef TRANSFORM_ALL_AW

if (not == 0) do_add(fanout11,fanout3,T_BUF,0);else if (not == 1) do_add(fanout11,fanout3,T_NOT,0);do_rm(fo1_not,fanout1);do_rm(fanin2,fanin1);

#endif#ifdef LOGIC_OPTIMIZATION

add_aw(node1, fanout1, node1, fanout2, T_BUF,0,12301);#endif

return MY_OK; If the 2_n3_6 pattern is found, the result will be display in stdout, perform redundancy addition and removal and logic optimizationg4

a g1 g2 g3g5fo1_notnode1 fanout1 fanout2 fanout3fanin1fanin2node2b

WarmWarm--up exerciseup exercise

Answer of warming up exerciseAnswer of warming up exerciseFinding the occurrence of pattern 2_n3_6 in circuit Finding the occurrence of pattern 2_n3_6 in circuit C7552.sisC7552.sis

How to get the answerHow to get the answer�� Consider the code segment in Consider the code segment in sr_main.csr_main.c

�� After pattern is found, After pattern is found, ““Local 2_n3_6Local 2_n3_6”” will be will be printed to printed to stdoutstdout�� ././gbaw.testgbaw.test /test/C7552.sis | /test/C7552.sis | grepgrep ““Local Local 2_n3_62_n3_6””�� Number of lines give the number of pattern Number of lines give the number of pattern foundfound

#ifdef NEW_CLUSTER_3flag1 = transform2_n3_6(node1, fanout1);if (flag1 == MY_OK) {#ifdef WIRE printf("Local 2_n3_6: Node %s -> Node %s.\n",node1_name,fanout1_name);#endif

How to get the answer (How to get the answer (concon’’ tt))�� OutputOutput

�� Totally 18 pattern is matchedTotally 18 pattern is matched

Local 2_n3_6: Node [60016] -> Node [61726].Local 2_n3_6: Node [60292] -> Node [61970].Local 2_n3_6: Node [60294] -> Node [62480].Local 2_n3_6: Node [60317] -> Node [62350].Local 2_n3_6: Node [60319] -> Node [62397].Local 2_n3_6: Node [60321] -> Node [62289].Local 2_n3_6: Node [60323] -> Node [62408].Local 2_n3_6: Node [60365] -> Node [61983].Local 2_n3_6: Node [60367] -> Node [62433].Local 2_n3_6: Node [60339] -> Node [62241].Local 2_n3_6: Node [60341] -> Node [62523].Local 2_n3_6: Node [60274] -> Node [61806].Local 2_n3_6: Node [60276] -> Node [61885].Local 2_n3_6: Node [60270] -> Node [61796].Local 2_n3_6: Node [60272] -> Node [61859].Local 2_n3_6: Node [60230] -> Node [61850].Local 2_n3_6: Node [60226] -> Node [61839].Local 2_n3_6: Node [60228] -> Node [62027].

Topological Statistics ExerciseTopological Statistics Exercise�� To change the Distribution Locality To change the Distribution Locality Version into Topological Locality Version Version into Topological Locality Version & obtain statistics for both versions on & obtain statistics for both versions on circuits starts with C, e.g. C3540.sis, circuits starts with C, e.g. C3540.sis, etc etc ……

�� Verification of Stat can be found in Verification of Stat can be found in ICCAD_02.doc document.ICCAD_02.doc document.

File hierarchyFile hierarchy�� Source codeSource code�� Technical papersTechnical papers�� FYP ReportsFYP Reports�� FYP PresentationsFYP Presentations�� TodayToday’’ s slidess slides�� GBAW statisticsGBAW statistics�� TodayToday’’ s benchmarks benchmark

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computer-aided design (cad) logic synthesis tutorial

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