comp541 datapaths ii & single-cycle mips
DESCRIPTION
COMP541 Datapaths II & Single-Cycle MIPS. Montek Singh Apr 2, 2012. Topics. Complete the datapath Add control to it Create a full single-cycle MIPS! Reading Chapter 7 Review MIPS assembly language Chapter 6 of course textbook Or, Patterson Hennessy (inside flap). Top-Level CPU (MIPS). - PowerPoint PPT PresentationTRANSCRIPT
1
COMP541COMP541
Datapaths II &Datapaths II &Single-Cycle MIPSSingle-Cycle MIPS
Montek SinghMontek Singh
Apr 2, 2012Apr 2, 2012
TopicsTopics Complete the datapathComplete the datapath Add control to itAdd control to it Create a full single-cycle MIPS!Create a full single-cycle MIPS!
ReadingReading Chapter 7Chapter 7 Review MIPS assembly languageReview MIPS assembly language
Chapter 6 of course textbookChapter 6 of course textbookOr, Patterson Hennessy (inside flap)Or, Patterson Hennessy (inside flap)
2
Top-Level CPU (MIPS)Top-Level CPU (MIPS)
3
MIPSInstr
MemoryData
Memory
pc[31:2]
instr
memwrite
dataadr
readdata
writedata
clk clkreset
Top-Level CPU: VerilogTop-Level CPU: Verilogmodule top(input clk, reset, module top(input clk, reset,
output … ); output … ); // add signals here for debugging// add signals here for debugging
wire [31:0] pc, instr, readdata, writedata, dataadr;wire [31:0] pc, instr, readdata, writedata, dataadr;
wire memwrite;wire memwrite;
mips mips(clk, reset, pc, instr, memwrite, dataadr, mips mips(clk, reset, pc, instr, memwrite, dataadr,
writedata, readdata);writedata, readdata); // processor// processor
imem imem(pc[31:2], instr);imem imem(pc[31:2], instr); // instr memory// instr memory
dmem dmem(clk, memwrite, dataadr, writedata,dmem dmem(clk, memwrite, dataadr, writedata,
readdata);readdata); // data memory// data memory
endmoduleendmodule
4
Top Level Schematic (ISE)Top Level Schematic (ISE)
5
MIPS
imem
dmem
One level down: Inside MIPSOne level down: Inside MIPSmodule mips(input clk, reset,module mips(input clk, reset,
output [31:0] pc,output [31:0] pc,
input [31:0] instr,input [31:0] instr,
output memwrite,output memwrite,
output [31:0] aluout, writedata,output [31:0] aluout, writedata,
input [31:0] readdata);input [31:0] readdata);
wire memtoreg, branch, pcsrc,wire memtoreg, branch, pcsrc,
alusrc, regdst, regwrite, jump;alusrc, regdst, regwrite, jump;
wire [4:0] alucontrol;wire [4:0] alucontrol; // depends on your ALU// depends on your ALU
wire [3:0] flags;wire [3:0] flags; // flags = {Z, V, C, N}// flags = {Z, V, C, N}
controller c(instr[31:26], instr[5:0], flags,controller c(instr[31:26], instr[5:0], flags,
memtoreg, memwrite, pcsrc,memtoreg, memwrite, pcsrc,
alusrc, regdst, regwrite, jump,alusrc, regdst, regwrite, jump,
alucontrol);alucontrol);
datapath dp(clk, reset, memtoreg, pcsrc,datapath dp(clk, reset, memtoreg, pcsrc,
alusrc, regdst, regwrite, jump,alusrc, regdst, regwrite, jump,
alucontrol,alucontrol,
flags, pc, instr,flags, pc, instr,
aluout, writedata, readdata);aluout, writedata, readdata);
endmoduleendmodule
6
A Note on FlagsA Note on Flags Book’s design only uses Z (zero)Book’s design only uses Z (zero)
simple version of MIPSsimple version of MIPS allows allows beq, bne, sltbeq, bne, slt type of tests type of tests
Our design uses { Z, V, C, N } flagsOur design uses { Z, V, C, N } flags Z = zeroZ = zero V = overflowV = overflow C = carry outC = carry out N = negativeN = negative Allows richer variety of instructionsAllows richer variety of instructions
see next slidesee next slidewherever you see “zero” in these slides, it should probably wherever you see “zero” in these slides, it should probably
read “flags”read “flags”
7
A Note on FlagsA Note on Flags 4 flags produced by ALU:4 flags produced by ALU:
Z (zero): result is = 0Z (zero): result is = 0 big NOR gatebig NOR gate
N (negative): result is < 0N (negative): result is < 0 SSN-1N-1
C (carry): indicates that most C (carry): indicates that most significant position produced a carry, significant position produced a carry, e.g., “1 + (-1)”e.g., “1 + (-1)” Carry from last FACarry from last FA
V (overflow): indicates answer doesn’t V (overflow): indicates answer doesn’t fitfit precisely:precisely:
To compare A and B, perform A–B and usecondition codes:
Signed comparison: LT NV LE Z+(NV) EQ Z NE ~Z GE ~(NV) GT ~(Z+(NV)) Unsigned comparison: LTU C LEU C+Z GEU ~C GTU ~(C+Z)
To compare A and B, perform A–B and usecondition codes:
Signed comparison: LT NV LE Z+(NV) EQ Z NE ~Z GE ~(NV) GT ~(Z+(NV)) Unsigned comparison: LTU C LEU C+Z GEU ~C GTU ~(C+Z)
-or-
DatapathDatapath
9
flags(3:0)
MIPS State ElementsMIPS State Elements
10
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
CLK
32 3232 32
32
32
32 32
32
32
5
5
5
We’ll fill out the datapath and control logic for basic single cycle MIPS• first the datapath• then the control logic
Single-Cycle Datapath: Single-Cycle Datapath: lwlw Let’s start by implementing Let’s start by implementing lwlw instruction instruction
11
Single-Cycle Datapath: Single-Cycle Datapath: lwlw First consider executing First consider executing lwlw
How does How does lw lw work?work?
STEP 1: Fetch instructionSTEP 1: Fetch instruction
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
Instr
CLK
Single-Cycle Datapath: Single-Cycle Datapath: lwlw STEP 2: Read source operands from register STEP 2: Read source operands from register
filefile
Instr
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
RegisterFile
A RD
DataMemory
WD
WEPCPC'
25:21
CLK
Single-Cycle Datapath: Single-Cycle Datapath: lwlw STEP 3: Sign-extend the immediateSTEP 3: Sign-extend the immediate
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
CLK
Single-Cycle Datapath: Single-Cycle Datapath: lwlw STEP 4: Compute the memory addressSTEP 4: Compute the memory address
SignImm
CLK
A RD
InstructionMemory
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB
ALUResult
SrcA Zero
CLK
ALUControl2:0
ALU
010
Note Control
Single-Cycle Datapath: Single-Cycle Datapath: lwlw STEP 5: Read data from memory and write it STEP 5: Read data from memory and write it
back to register fileback to register file
A1
A3
WD3
RD2
RD1WE3
A2
SignImm
CLK
A RD
InstructionMemory
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
Single-Cycle Datapath: Single-Cycle Datapath: lwlw STEP 6: Determine the address of the next STEP 6: Determine the address of the next
instructioninstruction
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
15:0
SrcB20:16
ALUResult ReadData
SrcA
PCPlus4
Result
RegWrite
Zero
CLK
ALUControl2:0
ALU
0101
LetLet’’s be Clear: CPU is Single-s be Clear: CPU is Single-Cycle!Cycle! Although the slides said Although the slides said ““STEPSTEP”” … …
… … all that stuff is executed in all that stuff is executed in one cycle!!!one cycle!!!
LetLet’’s look at s look at swsw next … next … … … and then R-type instructionsand then R-type instructions
18
Single-Cycle Datapath: Single-Cycle Datapath: swsw Write data in Write data in rtrt to memory to memory
nothing is written back into the register filenothing is written back into the register file
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
A RD
DataMemory
WD
WEPCPC' Instr
25:21
20:16
15:0
SrcB20:16
ALUResult ReadData
WriteData
SrcA
PCPlus4
Result
MemWriteRegWrite
Zero
CLK
ALUControl2:0
ALU
10100
Single-Cycle Datapath: R-type Single-Cycle Datapath: R-type instrinstr R-Type instructions:R-Type instructions:
Read from Read from rsrs and and rtrt Write ALUResult to register fileWrite ALUResult to register file Write to Write to rdrd (instead of (instead of rtrt))
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PCPC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
ALUResult ReadData
WriteData
SrcA
PCPlus4WriteReg4:0
Result
RegDst MemWrite MemtoRegALUSrcRegWrite
Zero
CLK
ALUControl2:0
ALU
0varies1 001
Single-Cycle Datapath: Single-Cycle Datapath: beqbeq Determine whether values in Determine whether values in rsrs and and rtrt are equal are equal Calculate branch target address: Calculate branch target address: BTA = (sign-extended immediate << 2) + (PC+4)BTA = (sign-extended immediate << 2) + (PC+4)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1
PC' Instr25:21
20:16
15:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
RegDst Branch MemWrite MemtoRegALUSrcRegWrite
Zero
PCSrc
CLK
ALUControl2:0
ALU
01100 x0x 1
Complete Single-Cycle Processor Complete Single-Cycle Processor (w/control)(w/control)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
Note: Difference due to FlagsNote: Difference due to Flags Our Control Unit will be slightly differentOur Control Unit will be slightly different
… … because of the extra flagsbecause of the extra flags
All flags (Z, V, C, N) are All flags (Z, V, C, N) are inputs to the control unitinputs to the control unit Signals such as PCSrc are produced Signals such as PCSrc are produced inside the control inside the control
unitunit
23
Control UnitControl Unit Generally as shown belowGenerally as shown below
but some differences because our ALU is more but some differences because our ALU is more sophisticatedsophisticated
RegDst
Branch
MemWrite
MemtoReg
ALUSrcOpcode5:0
ControlUnit
ALUControl2:0Funct5:0
MainDecoder
ALUOp1:0
ALUDecoder
RegWriteflags[3:0]
PCSrc
Note: This will be 5 bits for our full-feature ALU!
Note: This will be different for our full-feature ALU!
Review: Lightweight ALU from Review: Lightweight ALU from bookbook
ALU
N N
N
3
A B
Y
F
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
Review: Lightweight ALU from Review: Lightweight ALU from bookbook
+
2 01
A B
Cout
Y
3
01
F2
F1:0
[N-1] S
NN
N
N
N NNN
N
2
Ze
roE
xtend
F2:0 Function
000 A & B
001 A | B
010 A + B
011 not used
100 A & ~B
101 A | ~B
110 A - B
111 SLT
Review: Our “full feature” ALUReview: Our “full feature” ALU Full-feature ALU from COMP411:Full-feature ALU from COMP411:
FlagsV,C
A B
R
BidirectionalBarrelShifter
BooleanAdd/SubSub
Bool
Shft
Math
1 0
1 0 …
NFlag
ZFlag
Sub Bool Shft Math OP 0 XX 0 1 A+B 1 XX 0 1 A-B X X0 1 1 0 X X1 1 1 1 X 00 1 0 B<<A X 10 1 0 B>>A X 11 1 0 B>>>A X 00 0 0 A & B X 01 0 0 A | B X 10 0 0 A ^ B X 11 0 0 A | B
0 1
5-bit ALUFN
Review: R-Type instructionsReview: R-Type instructions Register-typeRegister-type
3 register operands:3 register operands: rs, rt: source registersrs, rt: source registers rd: destination registerrd: destination register
Other fields:Other fields:op:op: the operation code or opcode (0 for R-type the operation code or opcode (0 for R-type
instructions)instructions) funct:funct: the function the function
– together, together, opop and and functfunct tell the computer which operation to tell the computer which operation to performperform
shamt:shamt: the shift amount for shift instructions, otherwise it the shift amount for shift instructions, otherwise it is 0is 0
op rs rt rd shamt funct6 bits 5 bits 5 bits 5 bits 5 bits 6 bits
R-Type
Controller (2 modules)Controller (2 modules)module controller(input [5:0] op, funct,module controller(input [5:0] op, funct,
input [3:0] flags,input [3:0] flags,
output memtoreg, memwrite,output memtoreg, memwrite,
output pcsrc, alusrc,output pcsrc, alusrc,
output regdst, regwrite,output regdst, regwrite,
output jump,output jump,
output [2:0] alucontrol); output [2:0] alucontrol); // 5 bits for our ALU!!// 5 bits for our ALU!!
wire [1:0] aluop; wire [1:0] aluop; // This will be different for our ALU// This will be different for our ALU
wire branch;wire branch;
maindec md(op, memtoreg, memwrite, branch,maindec md(op, memtoreg, memwrite, branch,
alusrc, regdst, regwrite, jump, aluop);alusrc, regdst, regwrite, jump, aluop);
aludec ad(funct, aluop, alucontrol);aludec ad(funct, aluop, alucontrol);
assign pcsrc = branch & flags[3]; assign pcsrc = branch & flags[3]; // flags = {Z, V, C, N}// flags = {Z, V, C, N}
endmoduleendmodule
29
Main DecoderMain Decodermodule maindec(input [5:0] op,module maindec(input [5:0] op,
output memtoreg, memwrite, branch, alusrc,output memtoreg, memwrite, branch, alusrc,
output regdst, regwrite, jump,output regdst, regwrite, jump,
output [1:0] aluop);output [1:0] aluop); // different for our ALU// different for our ALU
reg [8:0] controls;reg [8:0] controls;
assign {regwrite, regdst, alusrc,assign {regwrite, regdst, alusrc,
branch, memwrite,branch, memwrite,
memtoreg, jump, aluop} = controls;memtoreg, jump, aluop} = controls;
always @(*)always @(*)
case(op)case(op)
6'b000000: controls <= 9'b110000010; //Rtype6'b000000: controls <= 9'b110000010; //Rtype
6'b100011: controls <= 9'b101001000; //LW6'b100011: controls <= 9'b101001000; //LW
6'b101011: controls <= 9'b001010000; //SW6'b101011: controls <= 9'b001010000; //SW
6'b000100: controls <= 9'b000100001; //BEQ6'b000100: controls <= 9'b000100001; //BEQ
6'b001000: controls <= 9'b101000000; //ADDI6'b001000: controls <= 9'b101000000; //ADDI
6'b000010: controls <= 9'b000000100; //J6'b000010: controls <= 9'b000000100; //J
default: controls <= 9'bxxxxxxxxx; //???default: controls <= 9'bxxxxxxxxx; //???
endcaseendcase
endmoduleendmodule
30
Why do this?
This entire coding may
be different in our design
ALU DecoderALU Decodermodule aludec(input [5:0] funct,module aludec(input [5:0] funct,
input [1:0] aluop,input [1:0] aluop,
output reg [2:0] alucontrol); output reg [2:0] alucontrol); // 5 bits for our ALU!!// 5 bits for our ALU!!
always @(*)always @(*)
case(aluop)case(aluop)
2'b00: alucontrol <= 3'b010; // add2'b00: alucontrol <= 3'b010; // add
2'b01: alucontrol <= 3'b110; // sub2'b01: alucontrol <= 3'b110; // sub
default: case(funct) // RTYPEdefault: case(funct) // RTYPE
6'b100000: alucontrol <= 3'b010; // ADD6'b100000: alucontrol <= 3'b010; // ADD
6'b100010: alucontrol <= 3'b110; // SUB6'b100010: alucontrol <= 3'b110; // SUB
6'b100100: alucontrol <= 3'b000; // AND6'b100100: alucontrol <= 3'b000; // AND
6'b100101: alucontrol <= 3'b001; // OR6'b100101: alucontrol <= 3'b001; // OR
6'b101010: alucontrol <= 3'b111; // SLT6'b101010: alucontrol <= 3'b111; // SLT
default: alucontrol <= 3'bxxx; // ???default: alucontrol <= 3'bxxx; // ???
endcaseendcase
endcaseendcase
endmoduleendmodule
31
This entire coding will be
different in our design
Control Unit: ALU DecoderControl Unit: ALU Decoder
ALUOp1:0 Meaning
00 Add
01 Subtract
10 Look at Funct
11 Not Used ALUOp1:0 Funct ALUControl2:0
00 X 010 (Add)
X1 X 110 (Subtract)
1X 100000 (add) 010 (Add)
1X 100010 (sub) 110 (Subtract)
1X 100100 (and) 000 (And)
1X 100101 (or) 001 (Or)
1X 101010 (slt) 111 (SLT)
This entire coding will be
different in our design
Control Unit: Main DecoderControl Unit: Main DecoderInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 0 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
Note on controllerNote on controller The actual number and names of control The actual number and names of control
signals may be somewhat different in our/your signals may be somewhat different in our/your designdesign compared to the one given in the bookcompared to the one given in the book because we are implementing more because we are implementing more
features/instructionsfeatures/instructions
SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!SO BE VERY CAREFUL WHEN YOU DESIGN YOUR CPU!
34
Single-Cycle Datapath Example: Single-Cycle Datapath Example: oror
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0010
01
0
0
1
0
Extended Functionality: Extended Functionality: addiaddi No change to datapathNo change to datapath
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
Control Unit: Control Unit: addiaddiInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 0 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …
addi 001000 1 0 1 0 0 0 …
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
Adding Jumps: Adding Jumps: jj
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC'
Instr25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
Control Unit: Main DecoderControl Unit: Main DecoderInstruction Op5:0 RegWrite RegDst AluSrc Branch MemWrite MemtoReg ALUOp1:0 Jump
R-type 000000 1 1 0 0 0 0 …lw 100011 1 0 1 0 0 0 …sw 101011 0 X 1 0 1 X …beq 000100 0 X 0 1 0 X …
j 000100 0 X X X 0 X XX 1
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC'
Instr25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU
0
1
25:0 <<2
27:0 31:28
PCJump
Jump
Review: Processor PerformanceReview: Processor Performance
Program Execution Time = Program Execution Time = (# (#
instructions)(cycles/instruction)(seconds/cycle)instructions)(cycles/instruction)(seconds/cycle)
= # instructions x CPI x TC= # instructions x CPI x TC
Single-Cycle PerformanceSingle-Cycle Performance TTCC is limited by the critical path is limited by the critical path (lw)(lw)
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
AL
U
1
010
01
0
1
0 0
Single-Cycle PerformanceSingle-Cycle Performance• Single-cycle critical path:Single-cycle critical path:
• TTcc = = ttpcq_PCpcq_PC + + ttmemmem + max( + max(ttRFRFreadread, , ttsextsext + + ttmuxmux) + ) + ttALUALU + + ttmemmem + + ttmuxmux + + ttRFRFsetupsetup
• In most implementations, limiting paths are: In most implementations, limiting paths are: – memory, ALU, register file. memory, ALU, register file.
– TTcc = = ttpcq_PCpcq_PC + 2 + 2ttmemmem + + ttRFRFreadread + + ttALUALU + + ttRFRFsetupsetup + + ttmuxmux
SignImm
CLK
A RD
InstructionMemory
+
4
A1
A3
WD3
RD2
RD1WE3
A2
CLK
Sign Extend
RegisterFile
0
1
0
1
A RD
DataMemory
WD
WE0
1
PC0
1PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
ControlUnit
Zero
PCSrc
CLK
ALUControl2:0
ALU1
010
01
0
1
0 0
Single-Cycle Performance Single-Cycle Performance ExampleExample
Tc = tpcq_PC + 2tmem + tRFread + tmux + tALU + tRFsetup
= [30 + 2(250) + 150 + 25 + 200 + 20] ps = 925 ps
What’s the max clock frequency?
Single-Cycle Performance Single-Cycle Performance ExampleExample For a program with 100 billion instructions For a program with 100 billion instructions
executing on a single-cycle MIPS processor,executing on a single-cycle MIPS processor, Execution TimeExecution Time
= # instructions x CPI x T= # instructions x CPI x TCC
= (100 × 10= (100 × 1099)(1)(925 × 10)(1)(925 × 10-12-12 s) s)= 92.5 seconds= 92.5 seconds
Next TimeNext Time Next class:Next class:
WeWe’’ll look at multi-cycle MIPSll look at multi-cycle MIPS Adding functionality to our designAdding functionality to our design
Next lab:Next lab: Implement single-cycle CPU!Implement single-cycle CPU!
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