comp203/nwen201 2009 memory technologies 0 plan for memory technologies topic static ram (sram)...

COMP203/NWEN201 2009 Memory Technologies 1

Plan for Memory Technologies Topic

• Static RAM (SRAM)• Dynamic RAM (DRAM)• Memory Hierarchy• DRAM Accelerating Techniques

– Reading B.5


Static Random Access Memory (SRAM)

• Registers are not cost-effective for main memory– Too much logic per bit– SRAM and DRAM used instead

• SRAM– Static Random access memory

• Made of D-latches

• Contents persists as long as power is on

• Read and write times are constant

– Described by height (number of cells) × width (bits per cell)– e.g. 256K x 1 or even 1G x 1

• 18 address inputs or 30 address inputs

• 1 output (1 bit of data per cell)


A Simplified Layout of a Memory Matrix

w

o

r

d

l

i

n

e

s

memory cell(physical word)

memory

element

(1 bit)

2 bit line SRAM

1 bit line DRAM

bit lines (input/output)


Example: A Typical SRAM Chip

• Chip select is used to turn this particular chip on - required prior to R or W

• Output enable allows the selected cell to assert its contents on Dout

• Write enable makes the selected cell update itself

• Typical spec– 5 - 25 ns read time– 4M x 1 (1997)– 512Mx1 (2003)– 1G X 1 (2008)

Address

Chip select

Output enable

Write enable

Din7 - Din0

15

8

SRAM32K x 8

Dout7 - Dout08


Three-State (or Tri-State) Buffers

register 0

register 1 32-to-1multiplexor

Dout

• The register file used a 32-to-1 multiplexor to ensure only one register drives Dout

• For a 64Kx1 SRAM a ‘centralised’ multiplexor is not practical

• Instead we let multiple memory elements drive each output via a three-state buffer

• As long as only one tri-state buffer is enabled all others will have a high impedance output

Dout

Select 0

Data 0elem 0

Select 1

Data 1elem 1

32

32

register 31

.

.

.

Tri-statebuffer


Decoding Addresses in SRAMs

• This design is okay for small SRAM

• But for large SRAMs the decoder becomes the limiting factor

• Solution: two-level decoding (next slide)


Example: Two-Level Decoding 32 KB

• In the first level each SRAM enables one 64-bit cell out of 512 cells– 9 address lines needed

• In second level each multiplexor chooses one bit out of 64– 6 address lines needed

• Net effect is a large savings in PLAs size


Dynamic Random Access Memory

• SRAMs use two inverters to store bits– bits can be stored indefinitely

• DRAMs use one transistor andone capacitor– much less

hardware– but charge

leaks away over time– bits need to

be refreshed • i.e. read out and

written back in

Capacitor

Pass transistor

Word line

Bit line

SRAMlatch

DRAM


Refreshing Mechanisms

• Can be done by processor– but to refresh megabytes several times a second becomes

costly

• More often done by memory chips themselves– entire rows can be refreshed at once– approximately 1% of memory cycles are lost to refreshing


Two-Level DRAM

• In the first level the decoder enables one row out of 2048– 11 address lines needed

– Each row has 2048 bits

• In the second level the multiplexor selects 1 bit out of 2048– 11 address lines needed

• Refresh involves writing a row from the column latches into the array

rowdecoder11-2048

2048 x 2048DRAM array

2048 column latches

multiplexor

Dout

Address 10 toAddress 0

Ad

dre

ss 2

1 to

Ad

dre

ss 1

1 R

e

f

r

e

s

h

2048

11

22

2048 bits

1


SRAM Performance in Early Sixties

• IC memory chips appeared in early sixties:– Capacity (size): 128 bits– Time to read (speed): ~ 1 microsecond– Power consumption: ~ 1 mW

• The same time Morris Mini was very popular:– Capacity: 4 persons– Speed: 100 km/hour– Consumption: 5 liters/100 km


SRAM Performance After Fifty Years

• Capacity (size): 1.0 Gbits• Time to read (speed): ~ 5 nanoseconds• Power consumption: ~ 1 microWatt

• The net result of the development:– Capacity increase: 10 million times– Speed increase: 500 times– Consumption decrease: 1000 times


What about Morris Mini?

• Morris Mini is still running on our streets

• What if it had undergone the same neck breaking development?– Capacity: 40 000 000 persons (10 times the whole NZ)– Speed: 15 000 km/hour– Consumption: 5 mill liters/100 km


Example Memory Architecture

CPURegisters

(Flip-Flops)

L1 Cache

(SRAM)

MainMemory(DRAM)

Fastest, most expensive, smallest

Slower, less expensive,

greater

HardDisk

Even slower, even less

expensive, even greater


Modern DRAM

• To access 1 bit: must set row and then column address– Fast page-mode DRAMS

• Provide faster access to subsequent bits on same row• First access sets row and column addresses• Subsequent accesses only change column address

– Nibble-mode DRAMs go better • Automatically generate next 3 column addresses• So, each row access reads 4 bits sequentially

– No need to wait for new column either

– Extended Data Out (EDO) DRAM• Similar to Fast page-mode• But, can start loading new row address while still reading from previous

row• Provides ~50% speedup of page-mode

– Bursting – fast delivering several consecutive words


Summary

• SRAM– D-latches as memory elements– Separate word, bit input and bit output lines– Address decoding, 2-level decoding– Tri-state buffers– Very fast, but not very dense

• DRAM– Transistor/capacitor elements, need for refreshing– Word lines and common bit input/output lines– Slower but very dense– FPM, EDO, SDRAM

• Bursting

comp203/nwen201 2009 memory technologies 0 plan for memory technologies topic static ram (sram)...

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